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Sergei Poselenov5d108ac2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020011 */
12
13/*
14 * Socrates
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
u-boot@bugs.denx.dee99b6072008-09-11 15:40:01 +020020/* new uImage format support */
21#define CONFIG_FIT 1
22#define CONFIG_OF_LIBFDT 1
23#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
24
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020025/* High Level Configuration Options */
26#define CONFIG_BOOKE 1 /* BOOKE */
27#define CONFIG_E500 1 /* BOOKE e500 family */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020028#define CONFIG_MPC8544 1
29#define CONFIG_SOCRATES 1
30
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#define CONFIG_SYS_TEXT_BASE 0xfff80000
32
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020033#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000034#define CONFIG_PCI_INDIRECT_BRIDGE
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020035
36#define CONFIG_TSEC_ENET /* tsec ethernet support */
37
38#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Detlev Zundel3e79b582008-08-15 15:42:12 +020039#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020040
41#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
42
43/*
44 * Only possible on E500 Version 2 or newer cores.
45 */
46#define CONFIG_ENABLE_36BIT_PHYS 1
47
48/*
49 * sysclk for MPC85xx
50 *
51 * Two valid values are:
52 * 33000000
53 * 66000000
54 *
55 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
56 * is likely the desired value here, so that is now the default.
57 * The board, however, can run at 66MHz. In any event, this value
58 * must match the settings of some switches. Details can be found
59 * in the README.mpc85xxads.
60 */
61
62#ifndef CONFIG_SYS_CLK_FREQ
63#define CONFIG_SYS_CLK_FREQ 66666666
64#endif
65
66/*
67 * These can be toggled for performance analysis, otherwise use default.
68 */
69#define CONFIG_L2_CACHE /* toggle L2 cache */
70#define CONFIG_BTB /* toggle branch predition */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020071
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020073
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
75#define CONFIG_SYS_MEMTEST_START 0x00400000
76#define CONFIG_SYS_MEMTEST_END 0x00C00000
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020077
Timur Tabie46fedf2011-08-04 18:03:41 -050078#define CONFIG_SYS_CCSRBAR 0xE0000000
79#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020080
Kumar Galabe0bd822008-08-26 22:56:56 -050081/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070082#define CONFIG_SYS_FSL_DDR2
Kumar Galabe0bd822008-08-26 22:56:56 -050083#undef CONFIG_FSL_DDR_INTERACTIVE
84#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
85#define CONFIG_DDR_SPD
86
87#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
88#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
89
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Galabe0bd822008-08-26 22:56:56 -050092#define CONFIG_VERY_BIG_RAM
93
94#define CONFIG_NUM_DDR_CONTROLLERS 1
95#define CONFIG_DIMM_SLOTS_PER_CTLR 1
96#define CONFIG_CHIP_SELECTS_PER_CTRL 2
97
98/* I2C addresses of SPD EEPROMs */
Anatolij Gustschin562788b2008-09-17 11:45:51 +020099#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200100
101#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
102
103/* Hardcoded values, to use instead of SPD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
105#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
106#define CONFIG_SYS_DDR_TIMING_0 0x00260802
107#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
108#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
109#define CONFIG_SYS_DDR_MODE 0x00480432
110#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
111#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
112#define CONFIG_SYS_DDR_CONFIG 0xC3008000
113#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
114#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200115
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200116/*
117 * Flash on the LocalBus
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_FLASH0 0xFE000000
122#define CONFIG_SYS_FLASH1 0xFC000000
123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
126#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
129#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
130#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
131#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200134#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
137#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
138#undef CONFIG_SYS_FLASH_CHECKSUM
139#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
140#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200141
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200142#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
145#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
146#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
147#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_INIT_RAM_LOCK 1
150#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200151#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200152
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200153#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200155
Detlev Zundel47106ce2010-04-14 11:32:20 +0200156#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
Detlev Zundel3e79b582008-08-15 15:42:12 +0200158
159/* FPGA and NAND */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_FPGA_BASE 0xc0000000
161#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
162#define CONFIG_SYS_HMI_BASE 0xc0010000
163#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
164#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
Detlev Zundel3e79b582008-08-15 15:42:12 +0200165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
167#define CONFIG_SYS_MAX_NAND_DEVICE 1
Detlev Zundel3e79b582008-08-15 15:42:12 +0200168#define CONFIG_CMD_NAND
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200169
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200170/* LIME GDC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_LIME_BASE 0xc8000000
172#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
173#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
174#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200175
176#define CONFIG_VIDEO
177#define CONFIG_VIDEO_MB862xx
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200178#define CONFIG_VIDEO_MB862xx_ACCEL
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200179#define CONFIG_CFB_CONSOLE
180#define CONFIG_VIDEO_LOGO
181#define CONFIG_VIDEO_BMP_LOGO
182#define CONFIG_CONSOLE_EXTRA_INFO
183#define VIDEO_FB_16BPP_PIXEL_SWAP
Wolfgang Grandegger229b6dc2009-10-23 12:03:15 +0200184#define VIDEO_FB_16BPP_WORD_SWAP
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200185#define CONFIG_VGA_AS_SINGLE_DEVICE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200187#define CONFIG_VIDEO_SW_CURSOR
188#define CONFIG_SPLASH_SCREEN
189#define CONFIG_VIDEO_BMP_GZIP
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200191
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200192/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
193#define CONFIG_SYS_MB862xx_CCF 0x10000
194/* SDRAM parameter */
195#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
196
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200197/* Serial Port */
198
199#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_NS16550
201#define CONFIG_SYS_NS16550_SERIAL
202#define CONFIG_SYS_NS16550_REG_SIZE 1
203#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
206#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200207
208#define CONFIG_BAUDRATE 115200
209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_BAUDRATE_TABLE \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
212
213#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500214#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200216
217
218/*
219 * I2C
220 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200221#define CONFIG_SYS_I2C
222#define CONFIG_SYS_I2C_FSL
223#define CONFIG_SYS_FSL_I2C_SPEED 102124
224#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
225#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
226#define CONFIG_SYS_FSL_I2C2_SPEED 102124
227#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
228#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Detlev Zundel3e79b582008-08-15 15:42:12 +0200229
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200230/* I2C RTC */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200231#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200233
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200234/* I2C W83782G HW-Monitoring IC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200236
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200237/* I2C temp sensor */
238/* Socrates uses Maxim's DS75, which is compatible with LM75 */
239#define CONFIG_DTT_LM75 1
240#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_DTT_MAX_TEMP 125
242#define CONFIG_SYS_DTT_LOW_TEMP -55
243#define CONFIG_SYS_DTT_HYSTERESIS 3
244#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200245
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200246/*
247 * General PCI
248 * Memory space is mapped 1-1.
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200251
Sergei Poselenov5e1882d2008-05-27 13:47:00 +0200252/* PCI is clocked by the external source at 33 MHz */
253#define CONFIG_PCI_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
255#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
256#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
257#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
258#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
259#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200260
261#if defined(CONFIG_PCI)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200262#define CONFIG_PCI_PNP /* do pci plug-and-play */
Sergei Poselenovd39e6852008-06-06 15:42:39 +0200263#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200264#endif /* CONFIG_PCI */
265
266
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200267#define CONFIG_MII 1 /* MII PHY management */
268#define CONFIG_TSEC1 1
269#define CONFIG_TSEC1_NAME "TSEC0"
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200270#define CONFIG_TSEC3 1
271#define CONFIG_TSEC3_NAME "TSEC1"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200272#undef CONFIG_MPC85XX_FEC
273
274#define TSEC1_PHY_ADDR 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200275#define TSEC3_PHY_ADDR 1
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200276
277#define TSEC1_PHYIDX 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200278#define TSEC3_PHYIDX 0
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200279#define TSEC1_FLAGS TSEC_GIGABIT
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200280#define TSEC3_FLAGS TSEC_GIGABIT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200281
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200282/* Options are: TSEC[0,1] */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200283#define CONFIG_ETHPRIME "TSEC0"
284#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
285
Sergei Poselenove18575d2008-05-07 15:10:49 +0200286#define CONFIG_HAS_ETH0
287#define CONFIG_HAS_ETH1
288
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200289/*
290 * Environment
291 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200292#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200293#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200295#define CONFIG_ENV_SIZE 0x4000
296#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
297#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200298
299#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200301
302#define CONFIG_TIMESTAMP /* Print image info with ts */
303
304
305/*
306 * BOOTP options
307 */
308#define CONFIG_BOOTP_BOOTFILESIZE
309#define CONFIG_BOOTP_BOOTPATH
310#define CONFIG_BOOTP_GATEWAY
311#define CONFIG_BOOTP_HOSTNAME
312
313
314/*
315 * Command line configuration.
316 */
Detlev Zundel47106ce2010-04-14 11:32:20 +0200317#define CONFIG_CMD_BMP
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200318#define CONFIG_CMD_DATE
319#define CONFIG_CMD_DHCP
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200320#define CONFIG_CMD_DTT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200321#undef CONFIG_CMD_EEPROM
Detlev Zundel47106ce2010-04-14 11:32:20 +0200322#define CONFIG_CMD_EXT2 /* EXT2 Support */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200323#define CONFIG_CMD_I2C
Detlev Zundel3e79b582008-08-15 15:42:12 +0200324#define CONFIG_CMD_SDRAM
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200325#define CONFIG_CMD_MII
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200326#define CONFIG_CMD_PING
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200327#define CONFIG_CMD_SNTP
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200328#define CONFIG_CMD_USB
Becky Bruce199e2622010-06-17 11:37:25 -0500329#define CONFIG_CMD_REGINFO
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200330
331#if defined(CONFIG_PCI)
332 #define CONFIG_CMD_PCI
333#endif
334
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200335#undef CONFIG_WATCHDOG /* watchdog disabled */
336
337/*
338 * Miscellaneous configurable options
339 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_LONGHELP /* undef to save memory */
341#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200342
343#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200345#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200347#endif
348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
350#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
351#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200352
353/*
354 * For booting Linux, the board info and command line data
355 * have to be in the first 8 MB of memory, since this is
356 * the maximum mapped by the Linux kernel during initialization.
357 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200359
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200360#if defined(CONFIG_CMD_KGDB)
361#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200362#endif
363
364
365#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
366
Detlev Zundel3e79b582008-08-15 15:42:12 +0200367#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200368
369#define CONFIG_PREBOOT "echo;" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200370 "echo Welcome on the ABB Socrates Board;" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200371 "echo"
372
373#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
374
375#define CONFIG_EXTRA_ENV_SETTINGS \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200376 "netdev=eth0\0" \
377 "consdev=ttyS0\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200378 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
379 "bootfile=/home/tftp/syscon3/uImage\0" \
380 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
381 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
382 "uboot_addr=FFFA0000\0" \
383 "kernel_addr=FE000000\0" \
384 "fdt_addr=FE1E0000\0" \
385 "ramdisk_addr=FE200000\0" \
386 "fdt_addr_r=B00000\0" \
387 "kernel_addr_r=200000\0" \
388 "ramdisk_addr_r=400000\0" \
389 "rootpath=/opt/eldk/ppc_85xxDP\0" \
390 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200391 "nfsargs=setenv bootargs root=/dev/nfs rw " \
392 "nfsroot=$serverip:$rootpath\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200393 "addcons=setenv bootargs $bootargs " \
394 "console=$consdev,$baudrate\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200395 "addip=setenv bootargs $bootargs " \
396 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
397 ":$hostname:$netdev:off panic=1\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200398 "boot_nor=run ramargs addcons;" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200399 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200400 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
401 "tftp ${fdt_addr_r} ${fdt_file}; " \
402 "run nfsargs addip addcons;" \
403 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200404 "update_uboot=tftp 100000 ${uboot_file};" \
405 "protect off fffa0000 ffffffff;" \
406 "era fffa0000 ffffffff;" \
407 "cp.b 100000 fffa0000 ${filesize};" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200408 "setenv filesize;saveenv\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200409 "update_kernel=tftp 100000 ${bootfile};" \
410 "era fe000000 fe1dffff;" \
411 "cp.b 100000 fe000000 ${filesize};" \
412 "setenv filesize;saveenv\0" \
413 "update_fdt=tftp 100000 ${fdt_file};" \
414 "era fe1e0000 fe1fffff;" \
415 "cp.b 100000 fe1e0000 ${filesize};" \
416 "setenv filesize;saveenv\0" \
417 "update_initrd=tftp 100000 ${initrd_file};" \
418 "era fe200000 fe9fffff;" \
419 "cp.b 100000 fe200000 ${filesize};" \
420 "setenv filesize;saveenv\0" \
421 "clean_data=era fea00000 fff5ffff\0" \
422 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
423 "load_usb=usb start;" \
424 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
425 "boot_usb=run load_usb usbargs addcons;" \
426 "bootm ${kernel_addr_r} - ${fdt_addr};" \
427 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200428 ""
Detlev Zundel3e79b582008-08-15 15:42:12 +0200429#define CONFIG_BOOTCOMMAND "run boot_nor"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200430
Sergei Poselenove18575d2008-05-07 15:10:49 +0200431/* pass open firmware flat tree */
432#define CONFIG_OF_LIBFDT 1
433#define CONFIG_OF_BOARD_SETUP 1
434
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200435/* USB support */
436#define CONFIG_USB_OHCI_NEW 1
437#define CONFIG_PCI_OHCI 1
438#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
Yuri Tikhonove90fb6a2008-09-04 11:19:05 +0200439#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
441#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
442#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200443#define CONFIG_DOS_PARTITION 1
444#define CONFIG_USB_STORAGE 1
445
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200446#endif /* __CONFIG_H */