blob: 523cf4da59b747879071f524adda4fbbba01d119 [file] [log] [blame]
Wolfgang Denkad5bb452007-03-06 18:08:43 +01001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26/*
27 * CPU test
28 * Shift instructions: rlwnm
29 *
30 * The test contains a pre-built table of instructions, operands and
31 * expected results. For each table entry, the test will cyclically use
32 * different sets of operand registers and result registers.
33 */
34
35#ifdef CONFIG_POST
36
37#include <post.h>
38#include "cpu_asm.h"
39
40#if CONFIG_POST & CFG_POST_CPU
41
42extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
43 ulong op2);
44extern ulong cpu_post_makecr (long v);
45
46static struct cpu_post_rlwnm_s
47{
48 ulong cmd;
49 ulong op1;
50 ulong op2;
51 uchar mb;
52 uchar me;
53 ulong res;
54} cpu_post_rlwnm_table[] =
55{
56 {
57 OP_RLWNM,
58 0xffff0000,
59 24,
60 16,
61 23,
62 0x0000ff00
63 },
64};
65static unsigned int cpu_post_rlwnm_size =
66 sizeof (cpu_post_rlwnm_table) / sizeof (struct cpu_post_rlwnm_s);
67
68int cpu_post_test_rlwnm (void)
69{
70 int ret = 0;
71 unsigned int i, reg;
72 int flag = disable_interrupts();
73
74 for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++)
75 {
76 struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i;
77
78 for (reg = 0; reg < 32 && ret == 0; reg++)
79 {
80 unsigned int reg0 = (reg + 0) % 32;
81 unsigned int reg1 = (reg + 1) % 32;
82 unsigned int reg2 = (reg + 2) % 32;
83 unsigned int stk = reg < 16 ? 31 : 15;
84 unsigned long code[] =
85 {
86 ASM_STW(stk, 1, -4),
87 ASM_ADDI(stk, 1, -24),
88 ASM_STW(3, stk, 12),
89 ASM_STW(4, stk, 16),
90 ASM_STW(reg0, stk, 8),
91 ASM_STW(reg1, stk, 4),
92 ASM_STW(reg2, stk, 0),
93 ASM_LWZ(reg1, stk, 12),
94 ASM_LWZ(reg0, stk, 16),
95 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me),
96 ASM_STW(reg2, stk, 12),
97 ASM_LWZ(reg2, stk, 0),
98 ASM_LWZ(reg1, stk, 4),
99 ASM_LWZ(reg0, stk, 8),
100 ASM_LWZ(3, stk, 12),
101 ASM_ADDI(1, stk, 24),
102 ASM_LWZ(stk, 1, -4),
103 ASM_BLR,
104 };
105 unsigned long codecr[] =
106 {
107 ASM_STW(stk, 1, -4),
108 ASM_ADDI(stk, 1, -24),
109 ASM_STW(3, stk, 12),
110 ASM_STW(4, stk, 16),
111 ASM_STW(reg0, stk, 8),
112 ASM_STW(reg1, stk, 4),
113 ASM_STW(reg2, stk, 0),
114 ASM_LWZ(reg1, stk, 12),
115 ASM_LWZ(reg0, stk, 16),
116 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) |
117 BIT_C,
118 ASM_STW(reg2, stk, 12),
119 ASM_LWZ(reg2, stk, 0),
120 ASM_LWZ(reg1, stk, 4),
121 ASM_LWZ(reg0, stk, 8),
122 ASM_LWZ(3, stk, 12),
123 ASM_ADDI(1, stk, 24),
124 ASM_LWZ(stk, 1, -4),
125 ASM_BLR,
126 };
127 ulong res;
128 ulong cr;
129
130 if (ret == 0)
131 {
132 cr = 0;
133 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
134
135 ret = res == test->res && cr == 0 ? 0 : -1;
136
137 if (ret != 0)
138 {
139 post_log ("Error at rlwnm test %d !\n", i);
140 }
141 }
142
143 if (ret == 0)
144 {
145 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
146
147 ret = res == test->res &&
148 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
149
150 if (ret != 0)
151 {
152 post_log ("Error at rlwnm test %d !\n", i);
153 }
154 }
155 }
156 }
157
158 if (flag)
159 enable_interrupts();
160
161 return ret;
162}
163
164#endif
165#endif