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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ben Whittenb2e01ff2017-11-23 13:47:48 +00002/*
3 * Configuation settings for the WB50N CPU Module.
Ben Whittenb2e01ff2017-11-23 13:47:48 +00004 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
9#include <asm/hardware.h>
10
Ben Whittenb2e01ff2017-11-23 13:47:48 +000011/* ARM asynchronous clock */
12#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
13#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
14
15#define CONFIG_ARCH_CPU_INIT
16
17#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
18#define CONFIG_SETUP_MEMORY_TAGS
19#define CONFIG_INITRD_TAG
20
21#ifndef CONFIG_SPL_BUILD
22#define CONFIG_SKIP_LOWLEVEL_INIT
23#endif
24
Ben Whittenb2e01ff2017-11-23 13:47:48 +000025/* general purpose I/O */
26#define CONFIG_AT91_GPIO
27
28/* serial console */
29#define CONFIG_ATMEL_USART
30#define CONFIG_USART_BASE ATMEL_BASE_DBGU
31#define CONFIG_USART_ID ATMEL_ID_DBGU
32
33/*
34 * BOOTP options
35 */
36#define CONFIG_BOOTP_BOOTFILESIZE
Ben Whittenb2e01ff2017-11-23 13:47:48 +000037
38/* SDRAM */
Ben Whittenb2e01ff2017-11-23 13:47:48 +000039#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
40#define CONFIG_SYS_SDRAM_SIZE 0x04000000
41
42#ifdef CONFIG_SPL_BUILD
43#define CONFIG_SYS_INIT_SP_ADDR 0x310000
44#else
45#define CONFIG_SYS_INIT_SP_ADDR \
46 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
47#endif
48
49#define CONFIG_SYS_MEMTEST_START 0x21000000
50#define CONFIG_SYS_MEMTEST_END 0x22000000
Ben Whittenb2e01ff2017-11-23 13:47:48 +000051
52/* NAND flash */
Ben Whittenb2e01ff2017-11-23 13:47:48 +000053#define CONFIG_SYS_MAX_NAND_DEVICE 1
54#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
55/* our ALE is AD21 */
56#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
57/* our CLE is AD22 */
58#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
59#define CONFIG_SYS_NAND_ONFI_DETECTION
60/* PMECC & PMERRLOC */
61#define CONFIG_ATMEL_NAND_HWECC
62#define CONFIG_ATMEL_NAND_HW_PMECC
63#define CONFIG_PMECC_CAP 8
64#define CONFIG_PMECC_SECTOR_SIZE 512
65
66/* Ethernet Hardware */
67#define CONFIG_MACB
68#define CONFIG_RMII
69#define CONFIG_NET_RETRY_COUNT 20
70#define CONFIG_MACB_SEARCH_PHY
71#define CONFIG_RGMII
72#define CONFIG_ETHADDR C0:EE:40:00:00:00
73#define CONFIG_ENV_OVERWRITE 1
74
75#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
76
77#define CONFIG_EXTRA_ENV_SETTINGS \
78 "autoload=no\0" \
79 "autostart=no\0"
80
81/* bootstrap + u-boot + env in nandflash */
82#define CONFIG_ENV_OFFSET 0xA0000
83#define CONFIG_ENV_OFFSET_REDUND 0xC0000
84#define CONFIG_ENV_SIZE 0x20000
85#define CONFIG_BOOTCOMMAND \
86 "nand read 0x22000000 0x000e0000 0x500000; " \
87 "bootm"
88
89#define CONFIG_BOOTARGS \
90 "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
91
92#define CONFIG_BAUDRATE 115200
93
94#define CONFIG_SYS_CBSIZE 1024
95#define CONFIG_SYS_MAXARGS 16
96#define CONFIG_SYS_PBSIZE \
97 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Ben Whittenb2e01ff2017-11-23 13:47:48 +000098
99/* Size of malloc() pool */
100#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
101
102/* SPL */
Ben Whittenb2e01ff2017-11-23 13:47:48 +0000103#define CONFIG_SPL_TEXT_BASE 0x300000
104#define CONFIG_SPL_MAX_SIZE 0x10000
105#define CONFIG_SPL_BSS_START_ADDR 0x20000000
106#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
107#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
108#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
109
110#define CONFIG_SYS_MONITOR_LEN (512 << 10)
111
112#define CONFIG_SPL_NAND_DRIVERS
113#define CONFIG_SPL_NAND_BASE
114#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
115#define CONFIG_SYS_NAND_5_ADDR_CYCLE
116#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
117#define CONFIG_SYS_NAND_PAGE_COUNT 64
118#define CONFIG_SYS_NAND_OOBSIZE 64
119#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
120#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
121#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
122
123#endif