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wdenk3a473b22004-01-03 00:43:19 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
wdenk3a473b22004-01-03 00:43:19 +000031/* This define must be before the core.h include */
32#define CONFIG_DB64460 1 /* this is an DB64460 board */
33
34#ifndef __ASSEMBLY__
35#include "../board/Marvell/include/core.h"
36#endif
37
38/*-----------------------------------------------------*/
39/* #include "../board/db64460/local.h" */
40#ifndef __LOCAL_H
41#define __LOCAL_H
42
43#define CONFIG_ETHADDR 64:46:00:00:00:01
wdenke2ffd592004-12-31 09:32:47 +000044#define CONFIG_HAS_ETH1
wdenk3a473b22004-01-03 00:43:19 +000045#define CONFIG_ETH1ADDR 64:46:00:00:00:02
wdenke2ffd592004-12-31 09:32:47 +000046#define CONFIG_HAS_ETH2
wdenk3a473b22004-01-03 00:43:19 +000047#define CONFIG_ETH2ADDR 64:46:00:00:00:03
48
49#define CONFIG_ENV_OVERWRITE
50#endif /* __CONFIG_H */
51
52/*
53 * High Level Configuration Options
54 * (easy to change)
55 */
56
57#define CONFIG_74xx /* we have a 750FX (override local.h) */
58
59#define CONFIG_DB64460 1 /* this is an DB64460 board */
60
61#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
62/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
63 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
64 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
65 see sdram_init.c */
66#undef CONFIG_ECC /* enable ECC support */
67#define CONFIG_MV64460_ECC
68
69/* which initialization functions to call for this board */
70#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
wdenkc837dcb2004-01-20 23:12:12 +000071#define CONFIG_BOARD_EARLY_INIT_F
wdenk3a473b22004-01-03 00:43:19 +000072
73#define CFG_BOARD_NAME "DB64460"
74#define CONFIG_IDENT_STRING "Marvell DB64460 (1.0)"
75
76/*#define CFG_HUSH_PARSER */
77#undef CFG_HUSH_PARSER
78
79#define CFG_PROMPT_HUSH_PS2 "> "
80
81/*
82 * The following defines let you select what serial you want to use
83 * for your console driver.
84 *
85 * what to do:
86 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
87 * cable onto the second DUART channel, change the CFG_DUART port from 1
88 * to 0 below.
89 *
90 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
91 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
92 */
93
94#define CONFIG_MPSC_PORT 0
95
96/* to change the default ethernet port, use this define (options: 0, 1, 2) */
97#define CONFIG_NET_MULTI
98#define MV_ETH_DEVS 3
99
100/* #undef CONFIG_ETHER_PORT_MII */
101#if 0
102#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
103#else
104#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
105#endif
106#define CONFIG_ZERO_BOOTDELAY_CHECK
107
108
109#undef CONFIG_BOOTARGS
110/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
111
112/* ronen - autoboot using tftp */
113#if (CONFIG_BOOTDELAY >= 0)
114#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
115 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
116 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
117
118#define CONFIG_BOOTARGS "console=ttyS0,115200"
119
120#endif
121
122/* ronen - the u-boot.bin should be ~0x30000 bytes */
123#define CONFIG_EXTRA_ENV_SETTINGS \
124 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
125cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
126 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
127cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
128 "bootargs_root=root=/dev/nfs rw\0" \
129 "bootargs_end=:::DB64460:eth0:none \0"\
130 "ethprime=mv_enet0\0"\
131 "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
132ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
133
134/* --------------------------------------------------------------------------------------------------------------- */
135/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
136
137#define CONFIG_IPADDR 10.2.40.90
138
139#define CONFIG_SERIAL "No. 1"
140#define CONFIG_SERVERIP 10.2.1.126
141#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
142
143
144#define CONFIG_TESTDRAMDATA y
145#define CONFIG_TESTDRAMADDRESS n
146#define CONFIG_TESETDRAMWALK n
147
148/* --------------------------------------------------------------------------------------------------------------- */
149
150#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
151#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
152
153#undef CONFIG_WATCHDOG /* watchdog disabled */
154#undef CONFIG_ALTIVEC /* undef to disable */
155
156#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
157 CONFIG_BOOTP_BOOTFILESIZE)
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200158/*
159 * JFFS2 partitions
160 *
161 */
162/* No command line, one static partition, whole device */
163#undef CONFIG_JFFS2_CMDLINE
164#define CONFIG_JFFS2_DEV "nor1"
165#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
166#define CONFIG_JFFS2_PART_OFFSET 0x00000000
wdenk3a473b22004-01-03 00:43:19 +0000167
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200168/* mtdparts command line support */
169
170/* Use first bank for JFFS2, second bank contains U-Boot.
171 *
172 * Note: fake mtd_id's used, no linux mtd map file.
173 */
174/*
175#define CONFIG_JFFS2_CMDLINE
176#define MTDIDS_DEFAULT "nor1=db64460-1"
177#define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)"
178*/
wdenk3a473b22004-01-03 00:43:19 +0000179
180#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
181 | CFG_CMD_ASKENV \
182 | CFG_CMD_I2C \
183 | CFG_CMD_EEPROM \
184 | CFG_CMD_CACHE \
185 | CFG_CMD_JFFS2 \
186 | CFG_CMD_PCI \
187 | CFG_CMD_NET )
188
189/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
190#include <cmd_confdefs.h>
191
192/*
193 * Miscellaneous configurable options
194 */
195#define CFG_I2C_EEPROM_ADDR_LEN 1
196#define CFG_I2C_MULTI_EEPROMS
197#define CFG_I2C_SPEED 40000 /* I2C speed default */
198
199/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
200#define CFG_LONGHELP /* undef to save memory */
201#define CFG_PROMPT "=> " /* Monitor Command Prompt */
202#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
203#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
204#else
205#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
206#endif
207#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
208#define CFG_MAXARGS 16 /* max number of command args */
209#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
210
211/*#define CFG_MEMTEST_START 0x00400000 memtest works on */
212/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
213/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
214
215/*
216#define CFG_DRAM_TEST
217 * DRAM tests
218 * CFG_DRAM_TEST - enables the following tests.
219 *
220 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
221 * Environment variable 'test_dram_data' must be
222 * set to 'y'.
223 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
224 * addressable. Environment variable
225 * 'test_dram_address' must be set to 'y'.
226 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
227 * This test takes about 6 minutes to test 64 MB.
228 * Environment variable 'test_dram_walk' must be
229 * set to 'y'.
230 */
231#define CFG_DRAM_TEST
232#if defined(CFG_DRAM_TEST)
233#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
234/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
235#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
236#define CFG_DRAM_TEST_DATA
237#define CFG_DRAM_TEST_ADDRESS
238#define CFG_DRAM_TEST_WALK
239#endif /* CFG_DRAM_TEST */
240
241#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
242#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
243
244#define CFG_LOAD_ADDR 0x00400000 /* default load address */
245
246#define CFG_HZ 1000 /* decr freq: 1ms ticks */
247/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
248#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
249#define CFG_BUS_CLK CFG_BUS_HZ
250
251#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
252#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
253
254/*ronen - this is the Tclk (MV64460 core) */
255#define CFG_TCLK 133000000
256
257
258#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
259
260#define CFG_750FX_HID0 0x8000c084
261#define CFG_750FX_HID1 0x54800000
262#define CFG_750FX_HID2 0x00000000
263
264/*
265 * Low Level Configuration Settings
266 * (address mappings, register initial values, etc.)
267 * You should know what you are doing if you make changes here.
268 */
269
270/*-----------------------------------------------------------------------
271 * Definitions for initial stack pointer and data area
272 */
273
274/*
275 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
276 * To an unused memory region. The stack will remain in cache until RAM
277 * is initialized
278*/
279#define CFG_INIT_RAM_LOCK
280#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
281#define CFG_INIT_RAM_END 0x1000
282#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
283#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
284
285#define RELOCATE_INTERNAL_RAM_ADDR
286#ifdef RELOCATE_INTERNAL_RAM_ADDR
287 #define CFG_INTERNAL_RAM_ADDR 0xf8000000
288#endif
289
290/*-----------------------------------------------------------------------
291 * Start addresses for the final memory configuration
292 * (Set up by the startup code)
293 * Please note that CFG_SDRAM_BASE _must_ start at 0
294 */
295#define CFG_SDRAM_BASE 0x00000000
296/* Dummies for BAT 4-7 */
297#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
298#define CFG_SDRAM2_BASE 0x20000000
299#define CFG_SDRAM3_BASE 0x30000000
300#define CFG_SDRAM4_BASE 0x40000000
301#define CFG_FLASH_BASE 0xfff00000
302
303#define CFG_DFL_BOOTCS_BASE 0xff800000
304#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
305
306#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
307#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
308#define PCI0_IO_BASE_BOOTM 0xfd000000
309
310#define CFG_RESET_ADDRESS 0xfff00100
311#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
312#define CFG_MONITOR_BASE CFG_FLASH_BASE
313#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
314
315/* areas to map different things with the GT in physical space */
316#define CFG_DRAM_BANKS 4
317
318/* What to put in the bats. */
319#define CFG_MISC_REGION_BASE 0xf0000000
320
321/* Peripheral Device section */
322
323/*******************************************************/
324/* We have on the db64460 Board : */
325/* GT-Chipset Register Area */
326/* GT-Chipset internal SRAM 256k */
327/* SRAM on external device module */
328/* Real time clock on external device module */
329/* dobble UART on external device module */
330/* Data flash on external device module */
331/* Boot flash on external device module */
332/*******************************************************/
333#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
334#define CFG_DB64460_RESET_ADDR 0x14000000 /* After power on Reset the DB64460 is here */
335
336/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
337#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
338#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
339
340#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
341#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
342#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
343#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
344
345#define CFG_DEV0_SIZE _8M /* db64460 sram @ 0xfc00.0000 */
346#define CFG_DEV1_SIZE _8M /* db64460 rtc @ 0xfc80.0000 */
347#define CFG_DEV2_SIZE _16M /* db64460 duart @ 0xfd00.0000 */
348#define CFG_DEV3_SIZE _16M /* db64460 flash @ 0xfe00.0000 */
349/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
350
351/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
352#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
353#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
354#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
355#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
356#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
357
358 /* c 4 a 8 2 4 1 c */
359 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
360 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
361 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
362 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
363
364
365/* ronen - update MPP Control MV64460*/
366#define CFG_MPP_CONTROL_0 0x02222222
367#define CFG_MPP_CONTROL_1 0x11333011
368#define CFG_MPP_CONTROL_2 0x40431111
369#define CFG_MPP_CONTROL_3 0x00000044
370
371/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
372
373
374# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
375 /* gpp[31] gpp[30] gpp[29] gpp[28] */
376 /* gpp[27] gpp[24]*/
377 /* gpp[19:14] */
378
379/* setup new config_value for MV64460 DDR-RAM !! */
380# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
381
382#define CFG_DUART_IO CFG_DEV2_SPACE
383#define CFG_DUART_CHAN 1 /* channel to use for console */
384#define CFG_INIT_CHAN1
385#define CFG_INIT_CHAN2
386
387#define SRAM_BASE CFG_DEV0_SPACE
388#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
389
390
391/*-----------------------------------------------------------------------
392 * PCI stuff
393 *-----------------------------------------------------------------------
394 */
395
396#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
397#define PCI_HOST_FORCE 1 /* configure as pci host */
398#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
399
400#define CONFIG_PCI /* include pci support */
401#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
402#define CONFIG_PCI_PNP /* do pci plug-and-play */
403#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
404
405/* PCI MEMORY MAP section */
406#define CFG_PCI0_MEM_BASE 0x80000000
407#define CFG_PCI0_MEM_SIZE _128M
408#define CFG_PCI1_MEM_BASE 0x88000000
409#define CFG_PCI1_MEM_SIZE _128M
410
411#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
412#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
413
414/* PCI I/O MAP section */
415#define CFG_PCI0_IO_BASE 0xfa000000
416#define CFG_PCI0_IO_SIZE _16M
417#define CFG_PCI1_IO_BASE 0xfb000000
418#define CFG_PCI1_IO_SIZE _16M
419
420#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
421#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
422#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
423#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
424
425#if defined (CONFIG_750CX)
426#define CFG_PCI_IDSEL 0x0
427#else
428#define CFG_PCI_IDSEL 0x30
429#endif
430/*----------------------------------------------------------------------
431 * Initial BAT mappings
432 */
433
434/* NOTES:
435 * 1) GUARDED and WRITE_THRU not allowed in IBATS
436 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
437 */
438
439/* SDRAM */
440#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
441#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
442#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
443#define CFG_DBAT0U CFG_IBAT0U
444
445/* init ram */
446#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
447#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
448#define CFG_DBAT1L CFG_IBAT1L
449#define CFG_DBAT1U CFG_IBAT1U
450
451/* PCI0, PCI1 in one BAT */
452#define CFG_IBAT2L BATL_NO_ACCESS
453#define CFG_IBAT2U CFG_DBAT2U
454#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
455#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
456
457/* GT regs, bootrom, all the devices, PCI I/O */
458#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
459#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
460#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
461#define CFG_DBAT3U CFG_IBAT3U
462
463/* I2C addresses for the two DIMM SPD chips */
464#define DIMM0_I2C_ADDR 0x56
465#define DIMM1_I2C_ADDR 0x54
466
467/*
468 * For booting Linux, the board info and command line data
469 * have to be in the first 8 MB of memory, since this is
470 * the maximum mapped by the Linux kernel during initialization.
471 */
472#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
473
474/*-----------------------------------------------------------------------
475 * FLASH organization
476 */
477#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
478#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
479
480#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
481#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
482#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
483
484#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
485#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
486#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
487#define CFG_FLASH_CFI 1
488
489#define CFG_ENV_IS_IN_FLASH 1
490#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
491#define CFG_ENV_SECT_SIZE 0x10000
492#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
493/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
494
495/*-----------------------------------------------------------------------
496 * Cache Configuration
497 */
498#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
499#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
500#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
501#endif
502
503/*-----------------------------------------------------------------------
504 * L2CR setup -- make sure this is right for your board!
505 * look in include/mpc74xx.h for the defines used here
506 */
507
508#define CFG_L2
509
510
511#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
512#define L2_INIT 0
513#else
514
515#define L2_INIT 0
516/*
517#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
518 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
519*/
520#endif
521
522#define L2_ENABLE (L2_INIT | L2CR_L2E)
523
524/*
525 * Internal Definitions
526 *
527 * Boot Flags
528 */
529#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
530#define BOOTFLAG_WARM 0x02 /* Software reboot */
531
532#define CFG_BOARD_ASM_INIT 1
533
534#endif /* __CONFIG_H */