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wdenk8966f332002-10-31 23:30:59 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Config header file for Hymod board
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_HYMOD 1 /* ...on a Hymod board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050038#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk8966f332002-10-31 23:30:59 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
41
wdenk8966f332002-10-31 23:30:59 +000042#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
43
44/*
45 * select serial console configuration
46 *
47 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
48 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
49 * for SCC).
50 *
51 * if CONFIG_CONS_NONE is defined, then the serial console routines must
52 * defined elsewhere (for example, on the cogent platform, there are serial
53 * ports on the motherboard which are used for the serial console - see
54 * cogent/cma101/serial.[ch]).
55 */
56#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
57#define CONFIG_CONS_ON_SCC /* define if console on SCC */
58#undef CONFIG_CONS_NONE /* define if console on something else*/
59#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
60#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
61#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
62#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
63
64/*
65 * select ethernet configuration
66 *
67 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
68 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
69 * for FCC)
70 *
71 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
72 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
73 * from CONFIG_COMMANDS to remove support for networking.
74 */
75#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
76#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
77#undef CONFIG_ETHER_NONE /* define if ether on something else */
78#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
wdenk6dd652f2003-06-19 23:40:20 +000079#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */
80
81#ifdef CONFIG_ETHER_ON_FCC
wdenk8966f332002-10-31 23:30:59 +000082
83#if (CONFIG_ETHER_INDEX == 1)
84
85/*
86 * - Rx-CLK is CLK10
87 * - Tx-CLK is CLK11
88 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
89 * - Enable Full Duplex in FSMR
90 */
91# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
92# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
93# define CFG_CPMFCR_RAMTYPE 0
94# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
95
wdenk6dd652f2003-06-19 23:40:20 +000096# define MDIO_PORT 0 /* Port A */
97# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */
98# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */
99
wdenk8966f332002-10-31 23:30:59 +0000100#elif (CONFIG_ETHER_INDEX == 2)
101
102/*
103 * - Rx-CLK is CLK13
104 * - Tx-CLK is CLK14
105 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
106 * - Enable Full Duplex in FSMR
107 */
108# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
109# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
110# define CFG_CPMFCR_RAMTYPE 0
111# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
112
wdenk6dd652f2003-06-19 23:40:20 +0000113# define MDIO_PORT 0 /* Port A */
114# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */
115# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */
116
wdenk8966f332002-10-31 23:30:59 +0000117#elif (CONFIG_ETHER_INDEX == 3)
118
119/*
120 * - Rx-CLK is CLK15
121 * - Tx-CLK is CLK16
122 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
123 * - Enable Full Duplex in FSMR
124 */
125# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
126# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
127# define CFG_CPMFCR_RAMTYPE 0
128# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
129
wdenk6dd652f2003-06-19 23:40:20 +0000130# define MDIO_PORT 0 /* Port A */
131# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */
132# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */
133
wdenk8966f332002-10-31 23:30:59 +0000134#endif /* CONFIG_ETHER_INDEX */
135
wdenk6dd652f2003-06-19 23:40:20 +0000136#define CONFIG_MII /* MII PHY management */
137#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
138
139#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK)
140#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK)
141#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0)
142
143#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \
144 else iop->pdat &= ~MDIO_DATA_PINMASK
145
146#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \
147 else iop->pdat &= ~MDIO_CLCK_PINMASK
148
149#define MIIDELAY udelay(1)
150
151#endif /* CONFIG_ETHER_ON_FCC */
152
wdenk8966f332002-10-31 23:30:59 +0000153
154/* other options */
155#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
wdenk6dd652f2003-06-19 23:40:20 +0000156#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
wdenk8966f332002-10-31 23:30:59 +0000157
158/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
159#ifdef DEBUG
160#define CONFIG_8260_CLKIN 33333333 /* in Hz */
161#else
162#define CONFIG_8260_CLKIN 66666666 /* in Hz */
163#endif
164
165#if defined(CONFIG_CONS_USE_EXTC)
166#define CONFIG_BAUDRATE 115200
167#else
wdenk6dd652f2003-06-19 23:40:20 +0000168#define CONFIG_BAUDRATE 9600
wdenk8966f332002-10-31 23:30:59 +0000169#endif
170
171/* default ip addresses - these will be overridden */
172#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
173#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
174
wdenk6dd652f2003-06-19 23:40:20 +0000175#define CONFIG_LAST_STAGE_INIT
176
wdenk8966f332002-10-31 23:30:59 +0000177#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
178 CFG_CMD_BEDBUG | \
wdenk824a1eb2003-04-20 16:49:37 +0000179 CFG_CMD_BMP | \
wdenk8966f332002-10-31 23:30:59 +0000180 CFG_CMD_DOC | \
wdenke2ffd592004-12-31 09:32:47 +0000181 CFG_CMD_EXT2 | \
wdenk8966f332002-10-31 23:30:59 +0000182 CFG_CMD_FDC | \
wdenk2262cfe2002-11-18 00:14:45 +0000183 CFG_CMD_FDOS | \
wdenk6dd652f2003-06-19 23:40:20 +0000184 CFG_CMD_FPGA | \
wdenk8966f332002-10-31 23:30:59 +0000185 CFG_CMD_HWFLOW | \
186 CFG_CMD_IDE | \
187 CFG_CMD_JFFS2 | \
wdenkac6dbb82003-03-26 11:42:53 +0000188 CFG_CMD_NAND | \
wdenk71f95112003-06-15 22:40:42 +0000189 CFG_CMD_MMC | \
wdenk8966f332002-10-31 23:30:59 +0000190 CFG_CMD_PCMCIA | \
191 CFG_CMD_PCI | \
192 CFG_CMD_USB | \
wdenkb79a11c2004-03-25 15:14:43 +0000193 CFG_CMD_REISER | \
wdenk8966f332002-10-31 23:30:59 +0000194 CFG_CMD_SCSI | \
wdenk1d0350e2002-11-11 21:14:20 +0000195 CFG_CMD_SPI | \
wdenke2ffd592004-12-31 09:32:47 +0000196 CFG_CMD_UNIVERSE| \
wdenk48abe7b2004-06-09 10:15:00 +0000197 CFG_CMD_VFD | \
198 CFG_CMD_XIMG ) )
wdenk8966f332002-10-31 23:30:59 +0000199
200/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
201#include <cmd_confdefs.h>
202
203#ifdef DEBUG
204#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
wdenk6dd652f2003-06-19 23:40:20 +0000205#else
206#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
207#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */
208#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */
209/* Be selective on what keys can delay or stop the autoboot process
210 * To stop use: " "
211 */
212#define CONFIG_AUTOBOOT_KEYED
213#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
214 "press <SPACE> to stop\n"
215#define CONFIG_AUTOBOOT_STOP_STR " "
216#undef CONFIG_AUTOBOOT_DELAY_STR
217#define DEBUG_BOOTKEYS 0
wdenk8966f332002-10-31 23:30:59 +0000218#endif
219
220#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
221#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
222#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
223#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
224#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
225#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
226#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
227#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
228# if defined(CONFIG_KGDB_USE_EXTC)
wdenk592c5ca2003-06-21 00:17:24 +0000229#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
wdenk8966f332002-10-31 23:30:59 +0000230# else
wdenk6dd652f2003-06-19 23:40:20 +0000231#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
wdenk8966f332002-10-31 23:30:59 +0000232# endif
233#endif
234
235#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
236
237#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
238
239/*
240 * Hymod specific configurable options
241 */
242#undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */
243
244/*
245 * Miscellaneous configurable options
246 */
247#define CFG_LONGHELP /* undef to save memory */
248#define CFG_PROMPT "=> " /* Monitor Command Prompt */
249#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
250#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
251#else
252#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
253#endif
254#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
255#define CFG_MAXARGS 16 /* max number of command args */
256#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
257
258#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
259#define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
260
wdenk6dd652f2003-06-19 23:40:20 +0000261#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
262
wdenk8966f332002-10-31 23:30:59 +0000263#define CFG_LOAD_ADDR 0x100000 /* default load address */
264
265#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
266
267#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
268
269#define CFG_I2C_SPEED 50000
270#define CFG_I2C_SLAVE 0x7e
271
272/* these are for the ST M24C02 2kbit serial i2c eeprom */
273#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
274#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenk6dd652f2003-06-19 23:40:20 +0000275/* mask of address bits that overflow into the "EEPROM chip address" */
276#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
277
278#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
279#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */
280#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
281
282#define CFG_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */
283
wdenk8966f332002-10-31 23:30:59 +0000284#define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
285
286/*
wdenk6dd652f2003-06-19 23:40:20 +0000287 * standard dtt sensor configuration - bottom bit will determine local or
288 * remote sensor of the ADM1021, the rest determines index into
289 * CFG_DTT_ADM1021 array below.
290 *
291 * On HYMOD board, the remote sensor should be connected to the MPC8260
292 * temperature diode thingy, but an errata said this didn't work and
293 * should be disabled - so it isn't connected.
294 */
295#if 0
296#define CONFIG_DTT_SENSORS { 0, 1 }
297#else
298#define CONFIG_DTT_SENSORS { 0 }
299#endif
300
301/*
302 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
303 * there will be one entry in this array for each two (dummy) sensors in
304 * CONFIG_DTT_SENSORS.
305 *
306 * For HYMOD board:
307 * - only one ADM1021
308 * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
309 * - conversion rate 0x02 = 0.25 conversions/second
310 * - ALERT ouput disabled
311 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
312 * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
313 */
314#define CFG_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
315
316/*
wdenk8966f332002-10-31 23:30:59 +0000317 * Low Level Configuration Settings
318 * (address mappings, register initial values, etc.)
319 * You should know what you are doing if you make changes here.
320 */
321
322/*-----------------------------------------------------------------------
323 * Hard Reset Configuration Words
324 *
325 * if you change bits in the HRCW, you must also change the CFG_*
326 * defines for the various registers affected by the HRCW e.g. changing
327 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
328 */
329#ifdef DEBUG
330#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
331 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
332 HRCW_MODCK_H0010)
333#else
334#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
335 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
336 HRCW_MODCK_H0101)
337#endif
338/* no slaves so just duplicate the master hrcw */
339#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
340#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
341#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
342#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
343#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
344#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
345#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
346
347/*-----------------------------------------------------------------------
348 * Internal Memory Mapped Register
349 */
350#define CFG_IMMR 0xF0000000
351
352/*-----------------------------------------------------------------------
353 * Definitions for initial stack pointer and data area (in DPRAM)
354 */
355#define CFG_INIT_RAM_ADDR CFG_IMMR
356#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
357#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
358#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
359#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
360
361/*-----------------------------------------------------------------------
362 * Start addresses for the final memory configuration
363 * (Set up by the startup code)
364 * Please note that CFG_SDRAM_BASE _must_ start at 0
365 */
366#define CFG_SDRAM_BASE 0x00000000
367#define CFG_FLASH_BASE TEXT_BASE
368#define CFG_MONITOR_BASE TEXT_BASE
369#define CFG_FPGA_BASE 0x80000000
370/*
371 * unfortunately, CFG_MONITOR_LEN must include the
372 * (very large i.e. 256kB) environment flash sector
373 */
374#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
375#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
376
377/*
378 * For booting Linux, the board info and command line data
379 * have to be in the first 8 MB of memory, since this is
380 * the maximum mapped by the Linux kernel during initialization.
381 */
382#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
383
384/*-----------------------------------------------------------------------
385 * FLASH organization
386 */
387#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
388#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
389
390#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
391#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
392
wdenk8966f332002-10-31 23:30:59 +0000393#define CFG_ENV_IS_IN_FLASH 1
wdenk592c5ca2003-06-21 00:17:24 +0000394#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
wdenk8966f332002-10-31 23:30:59 +0000395#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
396#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
397
398/*-----------------------------------------------------------------------
399 * Cache Configuration
400 */
401#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
402#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
403#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
404#endif
405
406/*-----------------------------------------------------------------------
407 * HIDx - Hardware Implementation-dependent Registers 2-11
408 *-----------------------------------------------------------------------
409 * HID0 also contains cache control - initially enable both caches and
410 * invalidate contents, then the final state leaves only the instruction
411 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
412 * but Soft reset does not.
413 *
414 * HID1 has only read-only information - nothing to set.
415 */
416#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
417 HID0_IFEM|HID0_ABE)
418#ifdef DEBUG
419#define CFG_HID0_FINAL 0
420#else
421#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
422#endif
423#define CFG_HID2 0
424
425/*-----------------------------------------------------------------------
426 * RMR - Reset Mode Register 5-5
427 *-----------------------------------------------------------------------
428 * turn on Checkstop Reset Enable
429 */
430#ifdef DEBUG
431#define CFG_RMR 0
432#else
433#define CFG_RMR RMR_CSRE
434#endif
435
436/*-----------------------------------------------------------------------
437 * BCR - Bus Configuration 4-25
438 *-----------------------------------------------------------------------
439 */
440#define CFG_BCR (BCR_ETM)
441
442/*-----------------------------------------------------------------------
443 * SIUMCR - SIU Module Configuration 4-31
444 *-----------------------------------------------------------------------
445 */
446#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
447 SIUMCR_APPC10|SIUMCR_MMR11)
448
449/*-----------------------------------------------------------------------
450 * SYPCR - System Protection Control 4-35
451 * SYPCR can only be written once after reset!
452 *-----------------------------------------------------------------------
453 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
454 */
455#if defined(CONFIG_WATCHDOG)
456#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
457 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
458#else
459#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
460 SYPCR_SWRI|SYPCR_SWP)
461#endif /* CONFIG_WATCHDOG */
462
463/*-----------------------------------------------------------------------
464 * TMCNTSC - Time Counter Status and Control 4-40
465 *-----------------------------------------------------------------------
466 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
467 * and enable Time Counter
468 */
469#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
470
471/*-----------------------------------------------------------------------
472 * PISCR - Periodic Interrupt Status and Control 4-42
473 *-----------------------------------------------------------------------
474 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
475 * Periodic timer
476 */
477#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
478
479/*-----------------------------------------------------------------------
480 * SCCR - System Clock Control 9-8
481 *-----------------------------------------------------------------------
482 * Ensure DFBRG is Divide by 16
483 */
484#define CFG_SCCR (SCCR_DFBRG01)
485
486/*-----------------------------------------------------------------------
487 * RCCR - RISC Controller Configuration 13-7
488 *-----------------------------------------------------------------------
489 */
490#define CFG_RCCR 0
491
492/*
493 * Init Memory Controller:
494 *
495 * Bank Bus Machine PortSz Device
496 * ---- --- ------- ------ ------
497 * 0 60x GPCM 32 bit FLASH
498 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now)
499 * 2 60x SDRAM 64 bit SDRAM
500 * 3 Local UPMC 8 bit Main Xilinx configuration
501 * 4 Local GPCM 32 bit Main Xilinx register mode
502 * 5 Local UPMB 32 bit Main Xilinx port mode
503 * 6 Local UPMC 8 bit Mezz Xilinx configuration
504 */
505
506/*
507 * Bank 0 - FLASH
508 *
509 * Quotes from the HYMOD IO Board Reference manual:
510 *
511 * "The flash memory is two Intel StrataFlash chips, each configured for
512 * 16 bit operation and connected to give a 32 bit wide port."
513 *
514 * "The chip select logic is configured to respond to both *CS0 and *CS1.
515 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
516 * It is suggested that bank 0 be read-only and bank 1 be read/write. The
517 * FLASH will then appear as ROM during boot."
518 *
519 * Initially, we are only going to use bank 0 in read/write mode.
520 */
521
522/* 32 bit, read-write, GPCM on 60x bus */
523#define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\
524 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
525/* up to 32 Mb */
526#define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
527
528/*
529 * Bank 2 - SDRAM
530 *
531 * Quotes from the HYMOD IO Board Reference manual:
532 *
533 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
534 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
535 * dynamic random access memory organised as 4 banks by 4096 rows by 512
536 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
537 *
538 * "The locations in SDRAM are accessed using multiplexed address pins to
539 * specify row and column. The pins also act to specify commands. The state
540 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
541 * pin may function as a row address or as the AUTO PRECHARGE control line,
542 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
543 * address lines to be configured to the required multiplexing scheme."
544 */
545
546#define CFG_SDRAM_SIZE 64
547
548/* 64 bit, read-write, SDRAM on 60x bus */
549#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\
550 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
551/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
552#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\
553 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
554
555/*
556 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
557 *
558 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
559 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
560 * as bank select, A7 is output on SDA10 during an ACTIVATE command,
561 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
562 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
563 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
564 * command is 2 clocks, earliest timing for PRECHARGE after last data
565 * was read is 1 clock, earliest timing for PRECHARGE after last data
566 * was written is 1 clock, CAS Latency is 2.
567 */
568
569#define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
570 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
571 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
572 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
573 PSDMR_WRC_1C|PSDMR_CL_2)
574
575/*
576 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
577 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
578 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
579 * Prescaler, hence the P instead of the R). The refresh timer period is given
580 * by (note that there was a change in the 8260 UM Errata):
581 *
582 * TimerPeriod = (PSRT + 1) / Fmptc
583 *
584 * where Fmptc is the BusClock divided by PTP. i.e.
585 *
586 * TimerPeriod = (PSRT + 1) / (BusClock / PTP)
587 *
588 * or
589 *
590 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock
591 *
592 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
593 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
594 * = 15.625 usecs.
595 *
596 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
597 * appear to be reasonable.
598 */
599
600#ifdef DEBUG
601#define CFG_PSRT 39
602#define CFG_MPTPR MPTPR_PTP_DIV8
603#else
604#define CFG_PSRT 31
605#define CFG_MPTPR MPTPR_PTP_DIV32
606#endif
607
608/*
609 * Banks 3,4,5 and 6 - FPGA access
610 *
611 * Quotes from the HYMOD IO Board Reference manual:
612 *
613 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
614 * for configuring an optional FPGA on the mezzanine interface.
615 *
616 * Access to the FPGAs may be divided into several catagories:
617 *
618 * 1. Configuration
619 * 2. Register mode access
620 * 3. Port mode access
621 *
622 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
623 * configured only (mode 1). Consequently there are four access types.
624 *
625 * To improve interface performance and simplify software design, the four
626 * possible access types are separately mapped to different memory banks.
627 *
628 * All are accessed using the local bus."
629 *
630 * Device Mode Memory Bank Machine Port Size Access
631 *
632 * Main Configuration 3 UPMC 8bit R/W
633 * Main Register 4 GPCM 32bit R/W
634 * Main Port 5 UPMB 32bit R/W
635 * Mezzanine Configuration 6 UPMC 8bit W/O
636 *
637 * "Note that mezzanine mode 1 access is write-only."
638 */
639
640/* all the bank sizes must be a power of two, greater or equal to 32768 */
641#define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE)
642#define FPGA_MAIN_CFG_SIZE 32768
643#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
644#define FPGA_MAIN_REG_SIZE 32768
645#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
646#define FPGA_MAIN_PORT_SIZE 32768
647#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
648#define FPGA_MEZZ_CFG_SIZE 32768
649
650/* 8 bit, read-write, UPMC */
651#define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
652/* up to 32Kbyte, burst inhibit */
653#define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
654
655/* 32 bit, read-write, GPCM */
656#define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
657/* up to 32Kbyte */
658#define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
659
660/* 32 bit, read-write, UPMB */
661#define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
662/* up to 32Kbyte */
663#define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
664
665/* 8 bit, write-only, UPMC */
666#define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
667/* up to 32Kbyte, burst inhibit */
668#define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
669
670/*-----------------------------------------------------------------------
671 * MBMR - Machine B Mode 10-27
672 *-----------------------------------------------------------------------
673 */
674#define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
675
676/*-----------------------------------------------------------------------
677 * MCMR - Machine C Mode 10-27
678 *-----------------------------------------------------------------------
679 */
680#define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
681
682/*
683 * FPGA I/O Port/Bit information
684 */
685
686#define FPGA_MAIN_PROG_PORT IOPIN_PORTA
687#define FPGA_MAIN_PROG_PIN 4 /* PA4 */
688#define FPGA_MAIN_INIT_PORT IOPIN_PORTA
689#define FPGA_MAIN_INIT_PIN 5 /* PA5 */
690#define FPGA_MAIN_DONE_PORT IOPIN_PORTA
691#define FPGA_MAIN_DONE_PIN 6 /* PA6 */
692
693#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
694#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
695#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
696#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
697#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
698#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
699#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
700#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
701
702/*
wdenk6dd652f2003-06-19 23:40:20 +0000703 * FPGA Interrupt configuration
704 */
705#define FPGA_MAIN_IRQ SIU_INT_IRQ2
706
707/*
wdenk8966f332002-10-31 23:30:59 +0000708 * Internal Definitions
709 *
710 * Boot Flags
711 */
712#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
713#define BOOTFLAG_WARM 0x02 /* Software reboot */
714
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200715/*
716 * JFFS2 partitions
717 *
718 */
719/* No command line, one static partition, whole device */
720#undef CONFIG_JFFS2_CMDLINE
721#define CONFIG_JFFS2_DEV "nor0"
722#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
723#define CONFIG_JFFS2_PART_OFFSET 0x00000000
724
725/* mtdparts command line support */
726/*
727#define CONFIG_JFFS2_CMDLINE
728#define MTDIDS_DEFAULT ""
729#define MTDPARTS_DEFAULT ""
730*/
731
wdenk8966f332002-10-31 23:30:59 +0000732#endif /* __CONFIG_H */