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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +02002/*
3 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +02004 */
5
6#include <common.h>
Peng Fan994266b2017-08-09 13:09:33 +08007#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06008#include <log.h>
Haavard Skinnemoend255bb02008-05-16 11:10:31 +02009#include <malloc.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020010#include <spi.h>
Simon Glass336d4612020-02-03 07:36:16 -070011#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060012#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060013#include <linux/delay.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090014#include <linux/errno.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020015#include <asm/io.h>
Stefano Babicd8e0ca82011-08-21 10:45:44 +020016#include <asm/gpio.h>
Stefano Babic86271112011-03-14 15:43:56 +010017#include <asm/arch/imx-regs.h>
18#include <asm/arch/clock.h>
Stefano Babic552a8482017-06-29 10:16:06 +020019#include <asm/mach-imx/spi.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020020
Peng Fan994266b2017-08-09 13:09:33 +080021DECLARE_GLOBAL_DATA_PTR;
22
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020023#ifdef CONFIG_MX27
24/* i.MX27 has a completely wrong register layout and register definitions in the
25 * datasheet, the correct one is in the Freescale's Linux driver */
26
Helmut Raiger61a58a12011-06-15 01:45:45 +000027#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020028"See linux mxc_spi driver from Freescale for details."
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020029#endif
30
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +030031__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
32{
33 return -1;
34}
35
Stefano Babicc4ea1422010-07-06 17:05:06 +020036#define OUT MXC_GPIO_DIRECTION_OUT
37
Stefano Babicac87c172011-01-19 22:46:33 +000038#define reg_read readl
39#define reg_write(a, v) writel(v, a)
40
Heiko Schocherf659b572014-07-14 10:22:11 +020041#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
42#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
43#endif
44
Heiko Schocher7a3faf32019-05-26 12:15:47 +020045#define MAX_CS_COUNT 4
46
Haavard Skinnemoend255bb02008-05-16 11:10:31 +020047struct mxc_spi_slave {
48 struct spi_slave slave;
49 unsigned long base;
50 u32 ctrl_reg;
Eric Nelson08c61a52012-01-31 07:52:03 +000051#if defined(MXC_ECSPI)
Stefano Babicd205ddc2010-04-04 22:43:38 +020052 u32 cfg_reg;
53#endif
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +010054 int gpio;
Stefano Babicc4ea1422010-07-06 17:05:06 +020055 int ss_pol;
Markus Niebel027a9a02014-10-23 16:09:39 +020056 unsigned int max_hz;
57 unsigned int mode;
Peng Fan994266b2017-08-09 13:09:33 +080058 struct gpio_desc ss;
Heiko Schocher7a3faf32019-05-26 12:15:47 +020059 struct gpio_desc cs_gpios[MAX_CS_COUNT];
60 struct udevice *dev;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020061};
Haavard Skinnemoend255bb02008-05-16 11:10:31 +020062
63static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
64{
65 return container_of(slave, struct mxc_spi_slave, slave);
66}
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020067
Peng Fan994266b2017-08-09 13:09:33 +080068static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
Stefano Babicd205ddc2010-04-04 22:43:38 +020069{
Lukasz Majewski56c40462020-06-04 23:11:53 +080070#if CONFIG_IS_ENABLED(DM_SPI)
Heiko Schocher7a3faf32019-05-26 12:15:47 +020071 struct udevice *dev = mxcs->dev;
72 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
73
74 u32 cs = slave_plat->cs;
75
76 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
77 return;
78
79 dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
80#else
81 if (mxcs->gpio > 0)
82 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
83#endif
Stefano Babicd205ddc2010-04-04 22:43:38 +020084}
85
Peng Fan994266b2017-08-09 13:09:33 +080086static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
Stefano Babicd205ddc2010-04-04 22:43:38 +020087{
Lukasz Majewski56c40462020-06-04 23:11:53 +080088#if CONFIG_IS_ENABLED(DM_SPI)
Heiko Schocher7a3faf32019-05-26 12:15:47 +020089 struct udevice *dev = mxcs->dev;
90 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
91
92 u32 cs = slave_plat->cs;
93
94 if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
95 return;
96
97 dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
98#else
99 if (mxcs->gpio > 0)
100 gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
101#endif
Stefano Babicd205ddc2010-04-04 22:43:38 +0200102}
103
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000104u32 get_cspi_div(u32 div)
105{
106 int i;
107
108 for (i = 0; i < 8; i++) {
109 if (div <= (4 << i))
110 return i;
111 }
112 return i;
113}
114
Eric Nelson08c61a52012-01-31 07:52:03 +0000115#ifdef MXC_CSPI
Markus Niebel027a9a02014-10-23 16:09:39 +0200116static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
Stefano Babicc9d59c72011-01-19 22:46:30 +0000117{
118 unsigned int ctrl_reg;
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000119 u32 clk_src;
120 u32 div;
Markus Niebel027a9a02014-10-23 16:09:39 +0200121 unsigned int max_hz = mxcs->max_hz;
122 unsigned int mode = mxcs->mode;
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000123
124 clk_src = mxc_get_clock(MXC_CSPI_CLK);
125
Benoît Thébaudeaucd200402012-08-10 08:51:50 +0000126 div = DIV_ROUND_UP(clk_src, max_hz);
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000127 div = get_cspi_div(div);
128
129 debug("clk %d Hz, div %d, real clk %d Hz\n",
130 max_hz, div, clk_src / (4 << div));
Stefano Babicc9d59c72011-01-19 22:46:30 +0000131
132 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
133 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000134 MXC_CSPICTRL_DATARATE(div) |
Stefano Babicc9d59c72011-01-19 22:46:30 +0000135 MXC_CSPICTRL_EN |
136#ifdef CONFIG_MX35
137 MXC_CSPICTRL_SSCTL |
138#endif
139 MXC_CSPICTRL_MODE;
140
141 if (mode & SPI_CPHA)
142 ctrl_reg |= MXC_CSPICTRL_PHA;
143 if (mode & SPI_CPOL)
144 ctrl_reg |= MXC_CSPICTRL_POL;
145 if (mode & SPI_CS_HIGH)
146 ctrl_reg |= MXC_CSPICTRL_SSPOL;
147 mxcs->ctrl_reg = ctrl_reg;
148
149 return 0;
150}
151#endif
152
Eric Nelson08c61a52012-01-31 07:52:03 +0000153#ifdef MXC_ECSPI
Markus Niebel027a9a02014-10-23 16:09:39 +0200154static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
Stefano Babicd205ddc2010-04-04 22:43:38 +0200155{
156 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
Dirk Behme9a309032013-05-11 07:25:54 +0200157 s32 reg_ctrl, reg_config;
Markus Niebel5d584cc2014-02-17 17:33:17 +0100158 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
159 u32 pre_div = 0, post_div = 0;
Stefano Babicac87c172011-01-19 22:46:33 +0000160 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Markus Niebel027a9a02014-10-23 16:09:39 +0200161 unsigned int max_hz = mxcs->max_hz;
162 unsigned int mode = mxcs->mode;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200163
Fabio Estevam0f1411b2013-04-09 13:06:25 +0000164 /*
165 * Reset SPI and set all CSs to master mode, if toggling
166 * between slave and master mode we might see a glitch
167 * on the clock line
168 */
169 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
170 reg_write(&regs->ctrl, reg_ctrl);
171 reg_ctrl |= MXC_CSPICTRL_EN;
172 reg_write(&regs->ctrl, reg_ctrl);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200173
Stefano Babicd205ddc2010-04-04 22:43:38 +0200174 if (clk_src > max_hz) {
Dirk Behme9a309032013-05-11 07:25:54 +0200175 pre_div = (clk_src - 1) / max_hz;
176 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
177 post_div = fls(pre_div);
178 if (post_div > 4) {
179 post_div -= 4;
180 if (post_div >= 16) {
Stefano Babicd205ddc2010-04-04 22:43:38 +0200181 printf("Error: no divider for the freq: %d\n",
182 max_hz);
183 return -1;
184 }
Dirk Behme9a309032013-05-11 07:25:54 +0200185 pre_div >>= post_div;
186 } else {
187 post_div = 0;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200188 }
189 }
190
191 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
192 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
193 MXC_CSPICTRL_SELCHAN(cs);
194 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
195 MXC_CSPICTRL_PREDIV(pre_div);
196 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
197 MXC_CSPICTRL_POSTDIV(post_div);
198
Stefano Babicd205ddc2010-04-04 22:43:38 +0200199 if (mode & SPI_CS_HIGH)
200 ss_pol = 1;
201
Markus Niebel5d584cc2014-02-17 17:33:17 +0100202 if (mode & SPI_CPOL) {
Stefano Babicd205ddc2010-04-04 22:43:38 +0200203 sclkpol = 1;
Markus Niebel5d584cc2014-02-17 17:33:17 +0100204 sclkctl = 1;
205 }
Stefano Babicd205ddc2010-04-04 22:43:38 +0200206
207 if (mode & SPI_CPHA)
208 sclkpha = 1;
209
Stefano Babicac87c172011-01-19 22:46:33 +0000210 reg_config = reg_read(&regs->cfg);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200211
212 /*
213 * Configuration register setup
Stefano Babicc9d59c72011-01-19 22:46:30 +0000214 * The MX51 supports different setup for each SS
Stefano Babicd205ddc2010-04-04 22:43:38 +0200215 */
216 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
217 (ss_pol << (cs + MXC_CSPICON_SSPOL));
218 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
219 (sclkpol << (cs + MXC_CSPICON_POL));
Markus Niebel5d584cc2014-02-17 17:33:17 +0100220 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
221 (sclkctl << (cs + MXC_CSPICON_CTL));
Stefano Babicd205ddc2010-04-04 22:43:38 +0200222 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
223 (sclkpha << (cs + MXC_CSPICON_PHA));
224
225 debug("reg_ctrl = 0x%x\n", reg_ctrl);
Stefano Babicac87c172011-01-19 22:46:33 +0000226 reg_write(&regs->ctrl, reg_ctrl);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200227 debug("reg_config = 0x%x\n", reg_config);
Stefano Babicac87c172011-01-19 22:46:33 +0000228 reg_write(&regs->cfg, reg_config);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200229
230 /* save config register and control register */
231 mxcs->ctrl_reg = reg_ctrl;
232 mxcs->cfg_reg = reg_config;
233
234 /* clear interrupt reg */
Stefano Babicac87c172011-01-19 22:46:33 +0000235 reg_write(&regs->intr, 0);
236 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200237
238 return 0;
239}
240#endif
241
Peng Fan994266b2017-08-09 13:09:33 +0800242int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
Stefano Babic2f721d12010-08-20 12:05:03 +0200243 const u8 *dout, u8 *din, unsigned long flags)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200244{
Axel Lin9675fed2013-06-14 21:13:32 +0800245 int nbytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200246 u32 data, cnt, i;
Stefano Babicac87c172011-01-19 22:46:33 +0000247 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Heiko Schocherf659b572014-07-14 10:22:11 +0200248 u32 ts;
249 int status;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200250
Ye Li65a106e2019-01-04 09:26:00 +0000251 debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
252 __func__, bitlen, (ulong)dout, (ulong)din);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200253
254 mxcs->ctrl_reg = (mxcs->ctrl_reg &
255 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100256 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
257
Stefano Babicac87c172011-01-19 22:46:33 +0000258 reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
Eric Nelson08c61a52012-01-31 07:52:03 +0000259#ifdef MXC_ECSPI
Stefano Babicac87c172011-01-19 22:46:33 +0000260 reg_write(&regs->cfg, mxcs->cfg_reg);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200261#endif
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200262
Stefano Babicd205ddc2010-04-04 22:43:38 +0200263 /* Clear interrupt register */
Stefano Babicac87c172011-01-19 22:46:33 +0000264 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100265
Stefano Babic2f721d12010-08-20 12:05:03 +0200266 /*
267 * The SPI controller works only with words,
268 * check if less than a word is sent.
269 * Access to the FIFO is only 32 bit
270 */
271 if (bitlen % 32) {
272 data = 0;
273 cnt = (bitlen % 32) / 8;
274 if (dout) {
275 for (i = 0; i < cnt; i++) {
276 data = (data << 8) | (*dout++ & 0xFF);
277 }
278 }
279 debug("Sending SPI 0x%x\n", data);
280
Stefano Babicac87c172011-01-19 22:46:33 +0000281 reg_write(&regs->txdata, data);
Stefano Babic2f721d12010-08-20 12:05:03 +0200282 nbytes -= cnt;
283 }
284
285 data = 0;
286
287 while (nbytes > 0) {
288 data = 0;
289 if (dout) {
290 /* Buffer is not 32-bit aligned */
291 if ((unsigned long)dout & 0x03) {
292 data = 0;
Anatolij Gustschindff01092011-01-20 07:53:06 +0000293 for (i = 0; i < 4; i++)
Stefano Babic2f721d12010-08-20 12:05:03 +0200294 data = (data << 8) | (*dout++ & 0xFF);
Stefano Babic2f721d12010-08-20 12:05:03 +0200295 } else {
296 data = *(u32 *)dout;
297 data = cpu_to_be32(data);
Timo Herbrecher6d5ce1b2013-10-16 00:05:09 +0530298 dout += 4;
Stefano Babic2f721d12010-08-20 12:05:03 +0200299 }
Stefano Babic2f721d12010-08-20 12:05:03 +0200300 }
301 debug("Sending SPI 0x%x\n", data);
Stefano Babicac87c172011-01-19 22:46:33 +0000302 reg_write(&regs->txdata, data);
Stefano Babic2f721d12010-08-20 12:05:03 +0200303 nbytes -= 4;
304 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200305
Stefano Babicd205ddc2010-04-04 22:43:38 +0200306 /* FIFO is written, now starts the transfer setting the XCH bit */
Stefano Babicac87c172011-01-19 22:46:33 +0000307 reg_write(&regs->ctrl, mxcs->ctrl_reg |
Stefano Babicd205ddc2010-04-04 22:43:38 +0200308 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200309
Heiko Schocherf659b572014-07-14 10:22:11 +0200310 ts = get_timer(0);
311 status = reg_read(&regs->stat);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200312 /* Wait until the TC (Transfer completed) bit is set */
Heiko Schocherf659b572014-07-14 10:22:11 +0200313 while ((status & MXC_CSPICTRL_TC) == 0) {
314 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
315 printf("spi_xchg_single: Timeout!\n");
316 return -1;
317 }
318 status = reg_read(&regs->stat);
319 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200320
Stefano Babicd205ddc2010-04-04 22:43:38 +0200321 /* Transfer completed, clear any pending request */
Stefano Babicac87c172011-01-19 22:46:33 +0000322 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100323
Axel Lin9675fed2013-06-14 21:13:32 +0800324 nbytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200325
Stefano Babic2f721d12010-08-20 12:05:03 +0200326 cnt = nbytes % 32;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200327
Stefano Babic2f721d12010-08-20 12:05:03 +0200328 if (bitlen % 32) {
Stefano Babicac87c172011-01-19 22:46:33 +0000329 data = reg_read(&regs->rxdata);
Stefano Babic2f721d12010-08-20 12:05:03 +0200330 cnt = (bitlen % 32) / 8;
Anatolij Gustschindff01092011-01-20 07:53:06 +0000331 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200332 debug("SPI Rx unaligned: 0x%x\n", data);
333 if (din) {
Anatolij Gustschindff01092011-01-20 07:53:06 +0000334 memcpy(din, &data, cnt);
335 din += cnt;
Stefano Babic2f721d12010-08-20 12:05:03 +0200336 }
337 nbytes -= cnt;
338 }
339
340 while (nbytes > 0) {
341 u32 tmp;
Stefano Babicac87c172011-01-19 22:46:33 +0000342 tmp = reg_read(&regs->rxdata);
Stefano Babic2f721d12010-08-20 12:05:03 +0200343 data = cpu_to_be32(tmp);
344 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
Masahiro Yamadab4141192014-11-07 03:03:31 +0900345 cnt = min_t(u32, nbytes, sizeof(data));
Stefano Babic2f721d12010-08-20 12:05:03 +0200346 if (din) {
347 memcpy(din, &data, cnt);
348 din += cnt;
349 }
350 nbytes -= cnt;
351 }
352
353 return 0;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200354
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200355}
356
Peng Fan994266b2017-08-09 13:09:33 +0800357static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
358 unsigned int bitlen, const void *dout,
359 void *din, unsigned long flags)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200360{
Axel Lin9675fed2013-06-14 21:13:32 +0800361 int n_bytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200362 int n_bits;
363 int ret;
364 u32 blk_size;
365 u8 *p_outbuf = (u8 *)dout;
366 u8 *p_inbuf = (u8 *)din;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200367
Peng Fan994266b2017-08-09 13:09:33 +0800368 if (!mxcs)
369 return -EINVAL;
Stefano Babic2f721d12010-08-20 12:05:03 +0200370
371 if (flags & SPI_XFER_BEGIN)
Peng Fan994266b2017-08-09 13:09:33 +0800372 mxc_spi_cs_activate(mxcs);
Stefano Babic2f721d12010-08-20 12:05:03 +0200373
374 while (n_bytes > 0) {
Stefano Babic2f721d12010-08-20 12:05:03 +0200375 if (n_bytes < MAX_SPI_BYTES)
376 blk_size = n_bytes;
377 else
378 blk_size = MAX_SPI_BYTES;
379
380 n_bits = blk_size * 8;
381
Peng Fan994266b2017-08-09 13:09:33 +0800382 ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
Stefano Babic2f721d12010-08-20 12:05:03 +0200383
384 if (ret)
385 return ret;
386 if (dout)
387 p_outbuf += blk_size;
388 if (din)
389 p_inbuf += blk_size;
390 n_bytes -= blk_size;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200391 }
392
Stefano Babic2f721d12010-08-20 12:05:03 +0200393 if (flags & SPI_XFER_END) {
Peng Fan994266b2017-08-09 13:09:33 +0800394 mxc_spi_cs_deactivate(mxcs);
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100395 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200396
397 return 0;
398}
399
Peng Fan994266b2017-08-09 13:09:33 +0800400static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
401{
402 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
403 int ret;
404
405 reg_write(&regs->rxdata, 1);
406 udelay(1);
407 ret = spi_cfg_mxc(mxcs, cs);
408 if (ret) {
409 printf("mxc_spi: cannot setup SPI controller\n");
410 return ret;
411 }
412 reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
413 reg_write(&regs->intr, 0);
414
415 return 0;
416}
417
Lukasz Majewski56c40462020-06-04 23:11:53 +0800418#if !CONFIG_IS_ENABLED(DM_SPI)
Peng Fan994266b2017-08-09 13:09:33 +0800419int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
420 void *din, unsigned long flags)
421{
422 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
423
424 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
425}
426
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300427/*
428 * Some SPI devices require active chip-select over multiple
429 * transactions, we achieve this using a GPIO. Still, the SPI
430 * controller has to be configured to use one of its own chipselects.
431 * To use this feature you have to implement board_spi_cs_gpio() to assign
432 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
433 * You must use some unused on this SPI controller cs between 0 and 3.
434 */
435static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
436 unsigned int bus, unsigned int cs)
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100437{
438 int ret;
439
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300440 mxcs->gpio = board_spi_cs_gpio(bus, cs);
441 if (mxcs->gpio == -1)
442 return 0;
443
Peng Fan994266b2017-08-09 13:09:33 +0800444 gpio_request(mxcs->gpio, "spi-cs");
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300445 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
446 if (ret) {
447 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
448 return -EINVAL;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100449 }
450
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300451 return 0;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100452}
453
Peng Fan994266b2017-08-09 13:09:33 +0800454static unsigned long spi_bases[] = {
455 MXC_SPI_BASE_ADDRESSES
456};
457
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200458struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
459 unsigned int max_hz, unsigned int mode)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200460{
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200461 struct mxc_spi_slave *mxcs;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100462 int ret;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200463
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100464 if (bus >= ARRAY_SIZE(spi_bases))
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200465 return NULL;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200466
Markus Niebel027a9a02014-10-23 16:09:39 +0200467 if (max_hz == 0) {
468 printf("Error: desired clock is 0\n");
469 return NULL;
470 }
471
Simon Glassd3504fe2013-03-18 19:23:40 +0000472 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
Stefano Babic2f721d12010-08-20 12:05:03 +0200473 if (!mxcs) {
474 puts("mxc_spi: SPI Slave not allocated !\n");
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100475 return NULL;
Stefano Babic2f721d12010-08-20 12:05:03 +0200476 }
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100477
Fabio Estevamde5bf022012-11-15 11:23:23 +0000478 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
479
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300480 ret = setup_cs_gpio(mxcs, bus, cs);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100481 if (ret < 0) {
482 free(mxcs);
483 return NULL;
484 }
485
Stefano Babicd205ddc2010-04-04 22:43:38 +0200486 mxcs->base = spi_bases[bus];
Markus Niebel027a9a02014-10-23 16:09:39 +0200487 mxcs->max_hz = max_hz;
488 mxcs->mode = mode;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200489
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200490 return &mxcs->slave;
491}
492
493void spi_free_slave(struct spi_slave *slave)
494{
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100495 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
496
497 free(mxcs);
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200498}
499
500int spi_claim_bus(struct spi_slave *slave)
501{
502 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
503
Peng Fan994266b2017-08-09 13:09:33 +0800504 return mxc_spi_claim_bus_internal(mxcs, slave->cs);
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200505}
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200506
507void spi_release_bus(struct spi_slave *slave)
508{
509 /* TODO: Shut the controller down */
510}
Peng Fan994266b2017-08-09 13:09:33 +0800511#else
512
513static int mxc_spi_probe(struct udevice *bus)
514{
Peng Fan994266b2017-08-09 13:09:33 +0800515 struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
516 int node = dev_of_offset(bus);
517 const void *blob = gd->fdt_blob;
518 int ret;
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200519 int i;
Peng Fan994266b2017-08-09 13:09:33 +0800520
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200521 ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
522 ARRAY_SIZE(mxcs->cs_gpios), 0);
523 if (ret < 0) {
524 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
525 return ret;
526 }
527
528 for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
529 if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
530 continue;
531
532 ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
533 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
534 if (ret) {
535 dev_err(bus, "Setting cs %d error\n", i);
536 return ret;
537 }
Peng Fan994266b2017-08-09 13:09:33 +0800538 }
539
Masahiro Yamada25484932020-07-17 14:36:48 +0900540 mxcs->base = dev_read_addr(bus);
Heiko Schocher2b849e12019-05-26 12:15:46 +0200541 if (mxcs->base == FDT_ADDR_T_NONE)
Peng Fan994266b2017-08-09 13:09:33 +0800542 return -ENODEV;
543
Peng Fan994266b2017-08-09 13:09:33 +0800544 mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
545 20000000);
546
547 return 0;
548}
549
550static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
551 const void *dout, void *din, unsigned long flags)
552{
553 struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
554
555
556 return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
557}
558
559static int mxc_spi_claim_bus(struct udevice *dev)
560{
561 struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
562 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
563
Heiko Schocher7a3faf32019-05-26 12:15:47 +0200564 mxcs->dev = dev;
565
Peng Fan994266b2017-08-09 13:09:33 +0800566 return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
567}
568
569static int mxc_spi_release_bus(struct udevice *dev)
570{
571 return 0;
572}
573
574static int mxc_spi_set_speed(struct udevice *bus, uint speed)
575{
576 /* Nothing to do */
577 return 0;
578}
579
580static int mxc_spi_set_mode(struct udevice *bus, uint mode)
581{
582 struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
583
584 mxcs->mode = mode;
585 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
586
587 return 0;
588}
589
590static const struct dm_spi_ops mxc_spi_ops = {
591 .claim_bus = mxc_spi_claim_bus,
592 .release_bus = mxc_spi_release_bus,
593 .xfer = mxc_spi_xfer,
594 .set_speed = mxc_spi_set_speed,
595 .set_mode = mxc_spi_set_mode,
596};
597
598static const struct udevice_id mxc_spi_ids[] = {
599 { .compatible = "fsl,imx51-ecspi" },
600 { }
601};
602
603U_BOOT_DRIVER(mxc_spi) = {
604 .name = "mxc_spi",
605 .id = UCLASS_SPI,
606 .of_match = mxc_spi_ids,
607 .ops = &mxc_spi_ops,
608 .platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
609 .probe = mxc_spi_probe,
610};
611#endif