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Daniel Gorsulowski44d80252010-01-25 10:50:41 +01001/*
Daniel Gorsulowskia950c812011-04-18 04:15:02 +00002 * (C) Copyright 2010-2011
Daniel Gorsulowski44d80252010-01-25 10:50:41 +01003 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
4 * esd electronic system design gmbh <www.esd.eu>
5 *
6 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01007 * Stelian Pop <stelian@popies.net>
Daniel Gorsulowski44d80252010-01-25 10:50:41 +01008 * Lead Tech Design <www.leadtechdesign.com>
9 *
10 * Configuation settings for the esd OTC570 board.
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000018/*
19 * SoC must be defined first, before hardware.h is included.
20 * In this case SoC is defined in boards.cfg.
21 */
22#include <asm/hardware.h>
23
24/*
25 * Warning: changing CONFIG_SYS_TEXT_BASE requires
26 * adapting the initial boot program.
27 * Since the linker has to swallow that define, we must use a pure
28 * hex number here!
29 */
30#define CONFIG_SYS_TEXT_BASE 0x20002000
31
Daniel Gorsulowskib2f26482011-10-30 22:52:29 +000032/*
33 * since a number of boards are not being listed in linux
34 * arch/arm/tools/mach-types any more, the mach-types have to be
35 * defined here
36 */
37#define MACH_TYPE_OTC570 2166
38
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000039/* ARM asynchronous clock */
40#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
Daniel Gorsulowski9f07ded2010-08-09 11:17:13 +020041#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010042
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000043/* Misc CPU related */
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010044#define CONFIG_SKIP_LOWLEVEL_INIT
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010045#define CONFIG_ARCH_CPU_INIT
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000046#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
47#define CONFIG_SETUP_MEMORY_TAGS
48#define CONFIG_INITRD_TAG
49#define CONFIG_SERIAL_TAG
50#define CONFIG_REVISION_TAG
51#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
52#define CONFIG_MISC_INIT_R /* Call misc_init_r */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000053
54#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */
55#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */
56#define CONFIG_PREBOOT /* enable preboot variable */
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010057
58/*
59 * Hardware drivers
60 */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000061
62/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */
63#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
64
65/* general purpose I/O */
66#define CONFIG_AT91_GPIO
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010067
68/* Console output */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000069#define CONFIG_ATMEL_USART
70#define CONFIG_USART_BASE ATMEL_BASE_DBGU
71#define CONFIG_USART_ID ATMEL_ID_SYS
72#define CONFIG_BAUDRATE 115200
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010073
74#define CONFIG_BOOTDELAY 3
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000075#define CONFIG_ZERO_BOOTDELAY_CHECK
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010076
77/* LCD */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000078#define CONFIG_LCD
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010079#undef CONFIG_SPLASH_SCREEN
80
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000081#ifdef CONFIG_LCD
82# define LCD_BPP LCD_COLOR8
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010083
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000084# ifndef CONFIG_SPLASH_SCREEN
85# define CONFIG_LCD_LOGO
86# define CONFIG_LCD_INFO
87# undef CONFIG_LCD_INFO_BELOW_LOGO
88# endif /* CONFIG_SPLASH_SCREEN */
89
90# undef LCD_TEST_PATTERN
91# define CONFIG_SYS_WHITE_ON_BLACK
92# define CONFIG_ATMEL_LCD
93# define CONFIG_SYS_CONSOLE_IS_IN_ENV
94# define CONFIG_OTC570_LCD_BASE (CONFIG_SYS_SDRAM_BASE + 0x03fa5000)
95# define CONFIG_CMD_BMP
96#endif /* CONFIG_LCD */
Daniel Gorsulowski44d80252010-01-25 10:50:41 +010097
98/* RTC and I2C stuff */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +000099#define CONFIG_RTC_DS1338
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100100#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100101
Heiko Schocherea818db2013-01-29 08:53:15 +0100102#define CONFIG_SYS_I2C
103#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
104#ifdef CONFIG_SYS_I2C_SOFT
105#define CONFIG_SYS_I2C_SOFT_SPEED 100000
106#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
107
Daniel Gorsulowski6258b042010-02-11 14:57:04 +0100108/* Configure data and clock pins for pio */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000109# define I2C_INIT { \
Daniel Gorsulowski6258b042010-02-11 14:57:04 +0100110 at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
111 at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100112}
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000113# define I2C_SOFT_DECLARATIONS
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100114/* Configure data pin as output */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000115# define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100116/* Configure data pin as input */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000117# define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0)
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100118/* Read data pin */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000119# define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4)
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100120/* Set data pin */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000121# define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit)
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100122/* Set clock pin */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000123# define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit)
124# define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
Heiko Schocherea818db2013-01-29 08:53:15 +0100125#endif /* CONFIG_SYS_I2C_SOFT */
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100126
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100127/*
128 * BOOTP options
129 */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000130#define CONFIG_BOOTP_BOOTFILESIZE
131#define CONFIG_BOOTP_BOOTPATH
132#define CONFIG_BOOTP_GATEWAY
133#define CONFIG_BOOTP_HOSTNAME
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100134
135/*
136 * Command line configuration.
137 */
138#include <config_cmd_default.h>
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100139#undef CONFIG_CMD_FPGA
140#undef CONFIG_CMD_LOADS
141#undef CONFIG_CMD_IMLS
142
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000143#define CONFIG_CMD_PING
144#define CONFIG_CMD_DHCP
145#define CONFIG_CMD_NAND
146#define CONFIG_CMD_USB
147#define CONFIG_CMD_I2C
148#define CONFIG_CMD_DATE
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100149
150/* LED */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000151#define CONFIG_AT91_LED
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100152
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000153/*
154 * SDRAM: 1 bank, min 32, max 128 MB
155 * Initialized before u-boot gets started.
156 */
157#define CONFIG_NR_DRAM_BANKS 1
158#define CONFIG_SYS_SDRAM_BASE 0x20000000 /* ATMEL_BASE_CS1 */
159#define CONFIG_SYS_SDRAM_SIZE 0x04000000
160
161#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
162#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
163#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
164
165/*
166 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
167 * leaving the correct space for initial global data structure above
168 * that address while providing maximum stack area below.
169 */
170#define CONFIG_SYS_INIT_SP_ADDR \
171 (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE)
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100172
173/* DataFlash */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000174#ifdef CONFIG_SYS_USE_DATAFLASH
175# define CONFIG_ATMEL_DATAFLASH_SPI
176# define CONFIG_HAS_DATAFLASH
177# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
178# define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
179# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
180# define AT91_SPI_CLK 15000000
181# define DATAFLASH_TCSS (0x1a << 16)
182# define DATAFLASH_TCHS (0x1 << 24)
183#endif
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100184
185/* NOR flash is not populated, disable it */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000186#define CONFIG_SYS_NO_FLASH
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100187
188/* NAND flash */
189#ifdef CONFIG_CMD_NAND
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000190# define CONFIG_NAND_ATMEL
191# define CONFIG_SYS_MAX_NAND_DEVICE 1
192# define CONFIG_SYS_NAND_BASE 0x40000000 /* ATMEL_BASE_CS3 */
193# define CONFIG_SYS_NAND_DBW_8
194# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
195# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100196# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
197# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100198#endif
199
200/* Ethernet */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000201#define CONFIG_MACB
202#define CONFIG_RMII
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000203#define CONFIG_FIT
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100204#define CONFIG_NET_RETRY_COUNT 20
205#undef CONFIG_RESET_PHY_R
206
207/* USB */
208#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800209#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000210#define CONFIG_USB_OHCI_NEW
211#define CONFIG_DOS_PARTITION
212#define CONFIG_SYS_USB_OHCI_CPU_INIT
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100213#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000
214#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
215#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000216#define CONFIG_USB_STORAGE
217#define CONFIG_CMD_FAT
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100218
219/* CAN */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000220#define CONFIG_AT91_CAN
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100221
222/* hw-controller addresses */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000223#define CONFIG_ET1100_BASE 0x70000000 /* ATMEL_BASE_CS6 */
224
225#ifdef CONFIG_SYS_USE_DATAFLASH
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100226
227/* bootstrap + u-boot + env in dataflash on CS0 */
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000228# define CONFIG_ENV_IS_IN_DATAFLASH
229# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100230 0x8400)
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000231# define CONFIG_ENV_OFFSET 0x4200
232# define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100233 CONFIG_ENV_OFFSET)
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000234# define CONFIG_ENV_SIZE 0x4200
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100235
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000236#elif CONFIG_SYS_USE_NANDFLASH
237
238/* bootstrap + u-boot + env + linux in nandflash */
239# define CONFIG_ENV_IS_IN_NAND 1
240# define CONFIG_ENV_OFFSET 0xC0000
241# define CONFIG_ENV_SIZE 0x20000
242
243#endif
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100244
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000245#define CONFIG_SYS_CBSIZE 512
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100246#define CONFIG_SYS_MAXARGS 16
247#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
248 sizeof(CONFIG_SYS_PROMPT) + 16)
Daniel Gorsulowskia950c812011-04-18 04:15:02 +0000249#define CONFIG_SYS_LONGHELP
250#define CONFIG_CMDLINE_EDITING
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100251
252/*
253 * Size of malloc() pool
254 */
255#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
256 128*1024, 0x1000)
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100257
Daniel Gorsulowski44d80252010-01-25 10:50:41 +0100258#endif