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wdenk5b1d7132002-11-03 00:07:02 +00001 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia io remapping
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
17 * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
18 * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
19*/
20
21#define CFG_PCMCIA_IO_ADDR 0xff020000
22#define CFG_PCMCIA_IO_SIZE 0x10000
23#define CFG_PCMCIA_MEM_ADDR 0xe0000000
24#define CFG_PCMCIA_MEM_SIZE 0x10000
25#define CFG_IMMR 0xFF000000
wdenk2535d602003-07-17 23:16:40 +000026#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
wdenk5b1d7132002-11-03 00:07:02 +000027#define CFG_SDRAM_BASE 0x00000000
28#define CFG_FLASH_BASE 0x02800000
29#define BCSR_ADDR ((uint) 0xff010000)
30#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
31
32/* ------------------------------------------------------------------------- */
33
34/*
35 * board/config.h - configuration options, board specific
36 */
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
41#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
42#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
43
44#define CONFIG_VIDEO 1 /* To enable video controller support */
45#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
46#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
47#define CFG_I2C_SLAVE 0x7F
48
49/*Now included by CFG_CMD_PCMCIA */
50/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
51
52/* Video related */
53
54#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
55#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
56#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
57#define CONFIG_VIDEO_SIZE (2*1024*1024)
58/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
59
60/* Wireless 56Khz 4PPM keyboard on SMCx */
61
wdenk682011f2003-06-03 23:54:09 +000062/*#define CONFIG_KEYBOARD 1 */
wdenk5b1d7132002-11-03 00:07:02 +000063#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
64
65/*
66 * High Level Configuration Options
67 * (easy to change)
68 */
wdenk5b1d7132002-11-03 00:07:02 +000069#define CONFIG_MPC823 1
70#define CONFIG_MPC823FADS 1
71#define CONFIG_FADS 1
72
73#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
74#undef CONFIG_8xx_CONS_SMC2
75#undef CONFIG_8xx_CONS_NONE
76#define CONFIG_BAUDRATE 115200
77
78/* Set the CPU speed to 50Mhz on the FADS */
79
80#if 0
81#define MPC8XX_FACT 10 /* Multiply by 10 */
82#define MPC8XX_XIN 5000000 /* 5 MHz in */
83#else
84#define MPC8XX_FACT 10 /* Multiply by 10 */
85#define MPC8XX_XIN 5000000 /* 5 MHz in */
86#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
87#endif
88#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
89
90#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
91
92#if 1
93#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
94#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
95#define CONFIG_BOOTARGS ""
96#define CONFIG_BOOTCOMMAND \
97"bootp ;" \
98"setenv bootargs console=tty0 console=ttyS0 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010099"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
100"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
wdenk5b1d7132002-11-03 00:07:02 +0000101"bootm"
102#else
103#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
104#endif
105
106#undef CONFIG_WATCHDOG /* watchdog disabled */
107
108#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
109
110/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
111#include <cmd_confdefs.h>
112
113/*
114 * Miscellaneous configurable options
115 */
116#define CFG_LONGHELP /* undef to save memory */
117#define CFG_PROMPT ":>" /* Monitor Command Prompt */
118#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
119#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
120#else
121#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
122#endif
123#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
124#define CFG_MAXARGS 16 /* max number of command args */
125#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
126
127#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
128#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
129
130#define CFG_LOAD_ADDR 0x00100000 /* default load address */
131
132#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
133
134#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
135
136/*
137 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here.
140 */
141/*-----------------------------------------------------------------------
142 * Internal Memory Mapped Register
143 */
144#define CFG_IMMR_SIZE ((uint)(64 * 1024))
145
146/*-----------------------------------------------------------------------
147 * Definitions for initial stack pointer and data area (in DPRAM)
148 */
149#define CFG_INIT_RAM_ADDR CFG_IMMR
150#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
151#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
152#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
153#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
154
155/*-----------------------------------------------------------------------
156 * Start addresses for the final memory configuration
157 * (Set up by the startup code)
158 * Please note that CFG_SDRAM_BASE _must_ start at 0
159 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
160 */
161#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
162#if 0
163#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
164#else
165#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
166#endif
167#define CFG_MONITOR_BASE CFG_FLASH_BASE
168#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
169
170/*
171 * For booting Linux, the board info and command line data
172 * have to be in the first 8 MB of memory, since this is
173 * the maximum mapped by the Linux kernel during initialization.
174 */
175#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
176/*-----------------------------------------------------------------------
177 * FLASH organization
178 */
179#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
180#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
181
182#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
183#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
184
185#define CFG_ENV_IS_IN_FLASH 1
186#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
187#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
188
189/*-----------------------------------------------------------------------
190 * Cache Configuration
191 */
192#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
193#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
194#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
195#endif
196
197/*-----------------------------------------------------------------------
198 * SYPCR - System Protection Control 11-9
199 * SYPCR can only be written once after reset!
200 *-----------------------------------------------------------------------
201 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
202 */
203#if defined(CONFIG_WATCHDOG)
204#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
205 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
206#else
207#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
208#endif
209
210/*-----------------------------------------------------------------------
211 * SIUMCR - SIU Module Configuration 11-6
212 *-----------------------------------------------------------------------
213 * PCMCIA config., multi-function pin tri-state
214 */
215#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
216
217/*-----------------------------------------------------------------------
218 * TBSCR - Time Base Status and Control 11-26
219 *-----------------------------------------------------------------------
220 * Clear Reference Interrupt Status, Timebase freezing enabled
221 */
222#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
223
224/*-----------------------------------------------------------------------
225 * PISCR - Periodic Interrupt Status and Control 11-31
226 *-----------------------------------------------------------------------
227 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
228 */
229#define CFG_PISCR (PISCR_PS | PISCR_PITF)
230
231/*-----------------------------------------------------------------------
232 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
233 *-----------------------------------------------------------------------
234 * Reset PLL lock status sticky bit, timer expired status bit and timer *
235 * interrupt status bit - leave PLL multiplication factor unchanged !
236 */
237#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
238
239/*-----------------------------------------------------------------------
240 * SCCR - System Clock and reset Control Register 15-27
241 *-----------------------------------------------------------------------
242 * Set clock output, timebase and RTC source and divider,
243 * power management and some other internal clocks
244 */
245#define SCCR_MASK SCCR_EBDF11
246#define CFG_SCCR (SCCR_TBS | \
247 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
248 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
249 SCCR_DFALCD00)
250
251 /*-----------------------------------------------------------------------
252 *
253 *-----------------------------------------------------------------------
254 *
255 */
256#define CFG_DER 0
257
258/* Because of the way the 860 starts up and assigns CS0 the
259* entire address space, we have to set the memory controller
260* differently. Normally, you write the option register
261* first, and then enable the chip select by writing the
262* base register. For CS0, you must write the base register
263* first, followed by the option register.
264*/
265
266/*
267 * Init Memory Controller:
268 *
269 * BR0/1 and OR0/1 (FLASH)
270 */
271/* the other CS:s are determined by looking at parameters in BCSRx */
272
273#define BCSR_SIZE ((uint)(64 * 1024))
274
275#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
276
277#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
278#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
279
280/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
281#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
282
283#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
284#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
285#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
286
287/* BCSRx - Board Control and Status Registers */
288#define CFG_OR1_REMAP CFG_OR0_REMAP
289#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
290#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
291
292
293/*
294 * Memory Periodic Timer Prescaler
295 */
296
297/* periodic timer for refresh */
298#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
299
300/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
301#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
302#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
303
304/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
305#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
306#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
307
308/*
309 * MAMR settings for SDRAM
310 */
311
312/* 8 column SDRAM */
313#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
314 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
315 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
316/* 9 column SDRAM */
317#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
318 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
319 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
320
321#define CFG_MAMR 0x13a01114
322/*
323 * Internal Definitions
324 *
325 * Boot Flags
326 */
327#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
328#define BOOTFLAG_WARM 0x02 /* Software reboot */
329
330/* values according to the manual */
331
332#define BCSR0 ((uint) (BCSR_ADDR + 00))
333#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
334#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
335#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
336#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
337
338/* FADS bitvalues by Helmut Buchsbaum
339 * see MPC8xxADS User's Manual for a proper description
340 * of the following structures
341 */
342
343#define BCSR0_ERB ((uint)0x80000000)
344#define BCSR0_IP ((uint)0x40000000)
345#define BCSR0_BDIS ((uint)0x10000000)
346#define BCSR0_BPS_MASK ((uint)0x0C000000)
347#define BCSR0_ISB_MASK ((uint)0x01800000)
348#define BCSR0_DBGC_MASK ((uint)0x00600000)
349#define BCSR0_DBPC_MASK ((uint)0x00180000)
350#define BCSR0_EBDF_MASK ((uint)0x00060000)
351
352#define BCSR1_FLASH_EN ((uint)0x80000000)
353#define BCSR1_DRAM_EN ((uint)0x40000000)
354#define BCSR1_ETHEN ((uint)0x20000000)
355#define BCSR1_IRDEN ((uint)0x10000000)
356#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
357#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
358#define BCSR1_BCSR_EN ((uint)0x02000000)
359#define BCSR1_RS232EN_1 ((uint)0x01000000)
360#define BCSR1_PCCEN ((uint)0x00800000)
361#define BCSR1_PCCVCC0 ((uint)0x00400000)
362#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
363#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
364#define BCSR1_RS232EN_2 ((uint)0x00040000)
365#define BCSR1_SDRAM_EN ((uint)0x00020000)
366#define BCSR1_PCCVCC1 ((uint)0x00010000)
367
368#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenkb54d32b2004-06-10 21:34:36 +0000369#define BCSR2_FLASH_PD_SHIFT 28
wdenk5b1d7132002-11-03 00:07:02 +0000370#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
wdenkb54d32b2004-06-10 21:34:36 +0000371#define BCSR2_DRAM_PD_SHIFT 23
wdenk5b1d7132002-11-03 00:07:02 +0000372#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
373#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
374
375#define BCSR3_DBID_MASK ((ushort)0x3800)
376#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
377#define BCSR3_BREVNR0 ((ushort)0x0080)
378#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
379#define BCSR3_BREVN1 ((ushort)0x0008)
380#define BCSR3_BREVN2_MASK ((ushort)0x0003)
381
382#define BCSR4_ETHLOOP ((uint)0x80000000)
383#define BCSR4_TFPLDL ((uint)0x40000000)
384#define BCSR4_TPSQEL ((uint)0x20000000)
385#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
386#ifdef CONFIG_MPC823
387#define BCSR4_USB_EN ((uint)0x08000000)
388#endif /* CONFIG_MPC823 */
389#ifdef CONFIG_MPC860SAR
390#define BCSR4_UTOPIA_EN ((uint)0x08000000)
391#endif /* CONFIG_MPC860SAR */
392#ifdef CONFIG_MPC860T
393#define BCSR4_FETH_EN ((uint)0x08000000)
394#endif /* CONFIG_MPC860T */
395#ifdef CONFIG_MPC823
396#define BCSR4_USB_SPEED ((uint)0x04000000)
397#endif /* CONFIG_MPC823 */
398#ifdef CONFIG_MPC860T
399#define BCSR4_FETHCFG0 ((uint)0x04000000)
400#endif /* CONFIG_MPC860T */
401#ifdef CONFIG_MPC823
402#define BCSR4_VCCO ((uint)0x02000000)
403#endif /* CONFIG_MPC823 */
404#ifdef CONFIG_MPC860T
405#define BCSR4_FETHFDE ((uint)0x02000000)
406#endif /* CONFIG_MPC860T */
407#ifdef CONFIG_MPC823
408#define BCSR4_VIDEO_ON ((uint)0x00800000)
409#endif /* CONFIG_MPC823 */
410#ifdef CONFIG_MPC823
411#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
412#endif /* CONFIG_MPC823 */
413#ifdef CONFIG_MPC860T
414#define BCSR4_FETHCFG1 ((uint)0x00400000)
415#endif /* CONFIG_MPC860T */
416#ifdef CONFIG_MPC823
417#define BCSR4_VIDEO_RST ((uint)0x00200000)
418#endif /* CONFIG_MPC823 */
419#ifdef CONFIG_MPC860T
420#define BCSR4_FETHRST ((uint)0x00200000)
421#endif /* CONFIG_MPC860T */
422#ifdef CONFIG_MPC823
423#define BCSR4_MODEM_EN ((uint)0x00100000)
424#endif /* CONFIG_MPC823 */
425#ifdef CONFIG_MPC823
426#define BCSR4_DATA_VOICE ((uint)0x00080000)
427#endif /* CONFIG_MPC823 */
428#ifdef CONFIG_MPC850
429#define BCSR4_DATA_VOICE ((uint)0x00080000)
430#endif /* CONFIG_MPC850 */
431
432#define CONFIG_DRAM_50MHZ 1
433#define CONFIG_SDRAM_50MHZ
434
wdenk5b1d7132002-11-03 00:07:02 +0000435/* We don't use the 8259.
436*/
437#define NR_8259_INTS 0
438
439/* Machine type
440*/
441#define _MACH_8xx (_MACH_fads)
442
443/*
444 * MPC8xx CPM Options
445 */
446#define CONFIG_SCC_ENET 1
447#define CONFIG_SCC2_ENET 1
448#undef CONFIG_FEC_ENET
449#undef CONFIG_CPM_IIC
450#undef CONFIG_UCODE_PATCH
451
452#define CONFIG_DISK_SPINUP_TIME 1000000
453
454/* PCMCIA configuration */
455
456#define PCMCIA_MAX_SLOTS 1
457
458#ifdef CONFIG_MPC860
459#define PCMCIA_SLOT_A 1
460#endif
461
wdenk180d3f72004-01-04 16:28:35 +0000462#define CFG_DAUGHTERBOARD
463
wdenk5b1d7132002-11-03 00:07:02 +0000464#endif /* __CONFIG_H */