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Wolfgang Denkb87dfd22006-07-19 13:50:38 +02001/*
2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2006
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
39
40#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
41
42#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
43#define BOOTFLAG_WARM 0x02 /* Software reboot */
44
45#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
46#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
47# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
48#endif
49
50/*
51 * Serial console configuration
52 */
53#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
54#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
55#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
56#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
57#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
58
59/*
60 * Video console
61 */
62#if 1
63#define CONFIG_VIDEO
64#define CONFIG_VIDEO_SM501
65#define CONFIG_VIDEO_SM501_32BPP
66#define CONFIG_CFB_CONSOLE
67#define CONFIG_VIDEO_LOGO
68#define CONFIG_VGA_AS_SINGLE_DEVICE
69#define CONFIG_CONSOLE_EXTRA_INFO
70#define CONFIG_VIDEO_SW_CURSOR
71#define CONFIG_SPLASH_SCREEN
72#define CFG_CONSOLE_IS_IN_ENV
73#endif
74
75#ifdef CONFIG_VIDEO
76#define ADD_BMP_CMD CFG_CMD_BMP
77#else
78#define ADD_BMP_CMD 0
79#endif
80
81/* Partitions */
82#define CONFIG_MAC_PARTITION
83#define CONFIG_DOS_PARTITION
84#define CONFIG_ISO_PARTITION
85
86/* USB */
87#define CONFIG_USB_OHCI
88#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
89#define CONFIG_USB_STORAGE
90
91/* POST support */
92#define CONFIG_POST (CFG_POST_MEMORY | \
93 CFG_POST_CPU | \
94 CFG_POST_I2C)
95
96#ifdef CONFIG_POST
97#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
98/* preserve space for the post_word at end of on-chip SRAM */
99#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
100#else
101#define CFG_CMD_POST_DIAG 0
102#endif
103
104/* IDE */
105#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
106
107/*
108 * Supported commands
109 */
110#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
111 ADD_BMP_CMD | \
112 ADD_IDE_CMD | \
113 ADD_PCI_CMD | \
114 ADD_USB_CMD | \
115 CFG_CMD_ASKENV | \
116 CFG_CMD_DATE | \
117 CFG_CMD_DHCP | \
118 CFG_CMD_ECHO | \
119 CFG_CMD_EEPROM | \
120 CFG_CMD_I2C | \
121 CFG_CMD_JFFS2 | \
122 CFG_CMD_MII | \
123 CFG_CMD_NFS | \
124 CFG_CMD_PING | \
125 CFG_CMD_POST_DIAG | \
126 CFG_CMD_REGINFO | \
127 CFG_CMD_SNTP | \
128 CFG_CMD_BSP)
129
130/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
131#include <cmd_confdefs.h>
132
133#define CONFIG_TIMESTAMP /* display image timestamps */
134
135#if (TEXT_BASE == 0xFC000000) /* Boot low */
136# define CFG_LOWBOOT 1
137#endif
138
139/*
140 * Autobooting
141 */
142#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
143
144#define CONFIG_PREBOOT "echo;" \
145 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
146 "echo"
147
148#undef CONFIG_BOOTARGS
149
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200150#if defined(CONFIG_TQM5200_B)
151#define CONFIG_EXTRA_ENV_SETTINGS \
152 "netdev=eth0\0" \
153 "rootpath=/opt/eldk/ppc_6xx\0" \
154 "ramargs=setenv bootargs root=/dev/ram rw\0" \
155 "nfsargs=setenv bootargs root=/dev/nfs rw " \
156 "nfsroot=${serverip}:${rootpath}\0" \
157 "addip=setenv bootargs ${bootargs} " \
158 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
159 ":${hostname}:${netdev}:off panic=1\0" \
160 "flash_self=run ramargs addip;" \
161 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
162 "flash_nfs=run nfsargs addip;" \
163 "bootm ${kernel_addr}\0" \
164 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
165 "bootfile=/tftpboot/tqm5200/uImage\0" \
166 "load=tftp 200000 ${u-boot}\0" \
167 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
168 "update=protect off FC000000 FC07FFFF;" \
169 "erase FC000000 FC07FFFF;" \
170 "cp.b 200000 FC000000 ${filesize};" \
171 "protect on FC000000 FC07FFFF\0" \
172 ""
173#else
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200174#define CONFIG_EXTRA_ENV_SETTINGS \
175 "netdev=eth0\0" \
176 "rootpath=/opt/eldk/ppc_6xx\0" \
177 "ramargs=setenv bootargs root=/dev/ram rw\0" \
178 "nfsargs=setenv bootargs root=/dev/nfs rw " \
179 "nfsroot=${serverip}:${rootpath}\0" \
180 "addip=setenv bootargs ${bootargs} " \
181 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
182 ":${hostname}:${netdev}:off panic=1\0" \
183 "flash_self=run ramargs addip;" \
184 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
185 "flash_nfs=run nfsargs addip;" \
186 "bootm ${kernel_addr}\0" \
187 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
188 "bootfile=/tftpboot/tqm5200/uImage\0" \
189 "load=tftp 200000 $(u-boot)\0" \
190 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
191 "update=protect off FC000000 FC05FFFF;" \
192 "erase FC000000 FC05FFFF;" \
193 "cp.b 200000 FC000000 ${filesize};" \
194 "protect on FC000000 FC05FFFF\0" \
195 ""
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200196#endif /* CONFIG_TQM5200_B */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200197
198#define CONFIG_BOOTCOMMAND "run net_nfs"
199
200/*
201 * IPB Bus clocking configuration.
202 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200203#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200204
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200205#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200206/*
207 * PCI Bus clocking configuration
208 *
209 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Wolfgang Denk725671c2007-06-06 16:26:56 +0200210 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200211 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200212 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200213#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200214#endif
215
216/*
217 * I2C configuration
218 */
219#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
220#define CFG_I2C_MODULE 2 /* Select I2C module #2 */
221
222/*
223 * I2C clock frequency
224 *
225 * Please notice, that the resulting clock frequency could differ from the
226 * configured value. This is because the I2C clock is derived from system
227 * clock over a frequency divider with only a few divider values. U-boot
228 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
229 * approximation allways lies below the configured value, never above.
230 */
231#define CFG_I2C_SPEED 100000 /* 100 kHz */
232#define CFG_I2C_SLAVE 0x7F
233
234/*
235 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
236 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
237 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
238 * same configuration could be used.
239 */
240#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
241#define CFG_I2C_EEPROM_ADDR_LEN 2
242#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
243#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
244
245/* List of I2C addresses to be verified by POST */
246#undef I2C_ADDR_LIST
247#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
248 CFG_I2C_RTC_ADDR, \
249 CFG_I2C_SLAVE }
250
251/*
252 * Flash configuration
253 */
254#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
255
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200256/* use CFI flash driver */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200257#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
258#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
259#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
260#define CFG_FLASH_EMPTY_INFO
261#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
262#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
Wolfgang Denk89366012006-07-19 14:16:38 +0200263#define CFG_FLASH_USE_BUFFER_WRITE 1
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200264
265#if !defined(CFG_LOWBOOT)
266#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
267#else /* CFG_LOWBOOT */
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200268#if defined(CONFIG_TQM5200_B)
269#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
270#else
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200271#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200272#endif /* CONFIG_TQM5200_B */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200273#endif /* CFG_LOWBOOT */
274#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
275 (= chip selects) */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200276
277/* Dynamic MTD partition support */
278#define CONFIG_JFFS2_CMDLINE
279#define MTDIDS_DEFAULT "nor0=TQM5200-0"
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200280#if defined(CONFIG_TQM5200_B)
281#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
282 "1280k(kernel)," \
283 "2m(initrd)," \
284 "4m(small-fs)," \
285 "16m(big-fs)," \
286 "8m(misc)"
287#else
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200288#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
289 "1408k(kernel)," \
290 "2m(initrd)," \
291 "4m(small-fs)," \
292 "16m(big-fs)," \
293 "8m(misc)"
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200294#endif /* CONFIG_TQM5200_B */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200295
296/*
297 * Environment settings
298 */
299#define CFG_ENV_IS_IN_FLASH 1
300#define CFG_ENV_SIZE 0x10000
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200301#if defined(CONFIG_TQM5200_B)
302#define CFG_ENV_SECT_SIZE 0x40000
303#else
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200304#define CFG_ENV_SECT_SIZE 0x20000
305#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200306#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
307#endif /* CONFIG_TQM5200_B */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200308
309/*
310 * Memory map
311 */
312#define CFG_MBAR 0xF0000000
313#define CFG_SDRAM_BASE 0x00000000
314#define CFG_DEFAULT_MBAR 0x80000000
315
316/* Use ON-Chip SRAM until RAM will be available */
317#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
318#ifdef CONFIG_POST
319/* preserve space for the post_word at end of on-chip SRAM */
320#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
321#else
322#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
323#endif
324
325
326#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
327#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
328#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
329
330#define CFG_MONITOR_BASE TEXT_BASE
331#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
332# define CFG_RAMBOOT 1
333#endif
334
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200335#if defined(CONFIG_TQM5200_B)
336#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
337#else
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200338#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200339#endif /* CONFIG_TQM5200_B */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200340#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
341#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
342
343/*
344 * Ethernet configuration
345 */
346#define CONFIG_MPC5xxx_FEC 1
347/*
348 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
349 */
350/* #define CONFIG_FEC_10MBIT 1 */
351#define CONFIG_PHY_ADDR 0x00
352
353/*
354 * GPIO configuration
355 *
356 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
357 * Bit 0 (mask: 0x80000000): 1
358 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
359 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
360 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
361 * Use for REV200 STK52XX boards. Do not use with REV100 modules
362 * (because, there I2C1 is used as I2C bus)
363 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
364 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
365 * 000 -> All PSC2 pins are GIOPs
366 * 001 -> CAN1/2 on PSC2 pins
367 * Use for REV100 STK52xx boards
368 * use PSC3: Bits 20:23 (mask: 0x00000300):
369 * 0001 -> USB2
370 * 0000 -> GPIO
371 * use PSC6:
372 * on STK52xx:
373 * use as UART. Pins PSC6_0 to PSC6_3 are used.
374 * Bits 9:11 (mask: 0x00700000):
375 * 101 -> PSC6 : Extended POST test is not available
376 * on MINI-FAP and TQM5200_IB:
377 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
378 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
379 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
380 * tests.
381 */
382#define CFG_GPS_PORT_CONFIG 0x81500114
383
384/*
385 * RTC configuration
386 */
387#define CONFIG_RTC_M41T11 1
388#define CFG_I2C_RTC_ADDR 0x68
389#define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
390 year */
391
392/*
393 * Miscellaneous configurable options
394 */
395#define CFG_LONGHELP /* undef to save memory */
396#define CFG_PROMPT "=> " /* Monitor Command Prompt */
397#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
398#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
399#else
400#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
401#endif
402#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
403#define CFG_MAXARGS 16 /* max number of command args */
404#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
405
406/* Enable an alternate, more extensive memory test */
407#define CFG_ALT_MEMTEST
408
409#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
410#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
411
412#define CFG_LOAD_ADDR 0x100000 /* default load address */
413
414#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
415
416/*
417 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
418 * which is normally part of the default commands (CFV_CMD_DFL)
419 */
420#define CONFIG_LOOPW
421
422/*
423 * Various low-level settings
424 */
425#if defined(CONFIG_MPC5200)
426#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
427#define CFG_HID0_FINAL HID0_ICE
428#else
429#define CFG_HID0_INIT 0
430#define CFG_HID0_FINAL 0
431#endif
432
433#define CFG_BOOTCS_START CFG_FLASH_BASE
434#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200435#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200436#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
437#else
438#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
439#endif
440#define CFG_CS0_START CFG_FLASH_BASE
441#define CFG_CS0_SIZE CFG_FLASH_SIZE
442
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200443#define CONFIG_LAST_STAGE_INIT
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200444
445/*
446 * SRAM - Do not map below 2 GB in address space, because this area is used
447 * for SDRAM autosizing.
448 */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200449#define CFG_CS2_START 0xE5000000
450#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
451#define CFG_CS2_CFG 0x0004D930
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200452
453/*
454 * Grafic controller - Do not map below 2 GB in address space, because this
455 * area is used for SDRAM autosizing.
456 */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200457#define SM501_FB_BASE 0xE0000000
458#define CFG_CS1_START (SM501_FB_BASE)
459#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
460#define CFG_CS1_CFG 0x8F48FF70
461#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200462
463#define CFG_CS_BURST 0x00000000
464#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
465
466#define CFG_RESET_ADDRESS 0xff000000
467
468/*-----------------------------------------------------------------------
469 * USB stuff
470 *-----------------------------------------------------------------------
471 */
472#define CONFIG_USB_CLOCK 0x0001BBBB
473#define CONFIG_USB_CONFIG 0x00001000
474
475/*-----------------------------------------------------------------------
476 * IDE/ATA stuff Supports IDE harddisk
477 *-----------------------------------------------------------------------
478 */
479
480#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
481
482#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
483#undef CONFIG_IDE_LED /* LED for ide not supported */
484
485#define CONFIG_IDE_RESET /* reset for ide supported */
486#define CONFIG_IDE_PREINIT
487
488#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
489#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
490
491#define CFG_ATA_IDE0_OFFSET 0x0000
492
493#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
494
495/* Offset for data I/O */
496#define CFG_ATA_DATA_OFFSET (0x0060)
497
498/* Offset for normal register accesses */
499#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
500
501/* Offset for alternate registers */
502#define CFG_ATA_ALT_OFFSET (0x005C)
503
504/* Interval between registers */
505#define CFG_ATA_STRIDE 4
506
507#endif /* __CONFIG_H */