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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 70922342369e5e39b286fe21e768a239ca07a514 / . / cpu / mcf52x2 / start.S
blob: 260a09abf76ffdcdd1c1a8ff4451993f9b9556bc [file] [log] [blame]
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31
32#define _START _start
33#define _FAULT _fault
34
35
36#define SAVE_ALL \
37 move.w #0x2700,%sr; /* disable intrs */ \
38 subl #60,%sp; /* space for 15 regs */ \
39 moveml %d0-%d7/%a0-%a6,%sp@; \
40
41#define RESTORE_ALL \
42 moveml %sp@,%d0-%d7/%a0-%a6; \
43 addl #60,%sp; /* space for 15 regs */ \
44 rte
45
46/* If we come from a pre-loader we don't need an initial exception
47 * table.
48 */
49#if !defined(CONFIG_MONITOR_IS_IN_RAM)
50
51.text
52/*
53 * Vector table. This is used for initial platform startup.
54 * These vectors are to catch any un-intended traps.
55 */
56_vectors:
57
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]58.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
59#if defined(CONFIG_R5200)
60.long 0x400
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]61#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]62.long _start - TEXT_BASE
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]63#else
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]64.long _START
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]65#endif
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]66
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102
103#endif
104
105 .text
106
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]107
108#if defined(CFG_INT_FLASH_BASE) && \
109 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
110 #if (TEXT_BASE == CFG_INT_FLASH_BASE)
111 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
112 .long 0xFFFFFFFF /* all sectors protected */
113 .long 0x00000000 /* supervisor/User restriction */
114 .long 0x00000000 /* programm/data space restriction */
115 .long 0x00000000 /* Flash security */
116 #endif
117#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]118 .globl _start
119_start:
120 nop
121 nop
122 move.w #0x2700,%sr
123
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]124#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]125 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
126 move.c %d0, %MBAR
127
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]128 /*** The 5249 has MBAR2 as well ***/
129#ifdef CFG_MBAR2
130 move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
131 movec %d0, #0xc0e /* Set MBAR2 */
132#endif
133
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]134 move.l #(CFG_INIT_RAM_ADDR + 1), %d0
135 movec %d0, %RAMBAR0
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]136#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]137
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]138#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]139 /* Initialize IPSBAR */
140 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
141 move.l %d0, 0x40000000
142
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]143 /* Initialize RAMBAR1: locate SRAM and validate it */
144 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
145 movec %d0, %RAMBAR1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]146
Bartlomiej Siekadaa6e412006-12-20 00:27:32 +0100[diff] [blame]147#if defined(CONFIG_M5282)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]148#if (TEXT_BASE == CFG_INT_FLASH_BASE)
149 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
150
151 move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
152 move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
153 move.l #(CFG_INIT_RAM_ADDR), %a2
154_copy_flash:
155 move.l (%a0)+, (%a2)+
156 cmp.l %a0, %a1
157 bgt.s _copy_flash
158 jmp CFG_INIT_RAM_ADDR
159
160_flashbar_setup:
161 /* Initialize FLASHBAR: locate internal Flash and validate it */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]162 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]163 movec %d0, %RAMBAR0
164 jmp _after_flashbar_copy.L /* Force jump to absolute address */
165_flashbar_setup_end:
166 nop
167_after_flashbar_copy:
168#else
169 /* Setup code to initialize FLASHBAR, if start from external Memory */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]170 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]171 movec %d0, %RAMBAR0
172#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
173
174#endif
Wolfgang Denk6741ae92006-09-04 01:03:57 +0200[diff] [blame]175#endif
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]176 /* if we come from a pre-loader we have no exception table and
177 * therefore no VBR to set
178 */
179#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]180#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
181 move.l #CFG_INT_FLASH_BASE, %d0
182#else
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]183 move.l #CFG_FLASH_BASE, %d0
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]184#endif
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]185 movec %d0, %VBR
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]186#endif
187
188#ifdef CONFIG_R5200
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]189 move.l #(_flash_setup-CFG_FLASH_BASE), %a0
190 move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
191 move.l #(CFG_INIT_RAM_ADDR), %a2
192_copy_flash:
193 move.l (%a0)+, (%a2)+
194 cmp.l %a0, %a1
195 bgt.s _copy_flash
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]196 jmp CFG_INIT_RAM_ADDR
197_after_flash_copy:
198#endif
199
200#if 0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]201 /* invalidate and disable cache */
202 move.l #0x01000000, %d0 /* Invalidate cache cmd */
203 movec %d0, %CACR /* Invalidate cache */
204 move.l #0, %d0
205 movec %d0, %ACR0
206 movec %d0, %ACR1
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]207#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]208
209 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
210 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
211 clr.l %sp@-
212
213 move.l #__got_start, %a5 /* put relocation table address to a5 */
214
215 bsr cpu_init_f /* run low-level CPU init code (from flash) */
216 bsr board_init_f /* run low-level board init code (from flash) */
217
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]218 /* board_init_f() does not return */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]219
220/*------------------------------------------------------------------------------*/
221
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]222#ifdef CONFIG_R5200
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]223_flash_setup:
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]224 /* CSAR0 */
225 move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]226 move.w %d0, 0x40000080
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]227
228 /* CSCR0 */
229 move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]230 move.w %d0, 0x4000008A
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]231
232 /* CSMR0 */
233 move.l #0x001f0001, %d0 /* 2 MB, valid */
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]234 move.l %d0, 0x40000084
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]235
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]236 jmp _after_flash_copy.L
237_flash_setup_end:
238#endif
239
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]240/*
241 * void relocate_code (addr_sp, gd, addr_moni)
242 *
243 * This "function" does not return, instead it continues in RAM
244 * after relocating the monitor code.
245 *
246 * r3 = dest
247 * r4 = src
248 * r5 = length in bytes
249 * r6 = cachelinesize
250 */
251 .globl relocate_code
252relocate_code:
253 link.w %a6,#0
254 move.l 8(%a6), %sp /* set new stack pointer */
255
256 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
257 move.l 16(%a6), %a0 /* Save copy of Destination Address */
258
259 move.l #CFG_MONITOR_BASE, %a1
260 move.l #__init_end, %a2
261 move.l %a0, %a3
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]262 /* copy the code to RAM */
2631:
264 move.l (%a1)+, (%a3)+
265 cmp.l %a1,%a2
266 bgt.s 1b
267
268/*
269 * We are done. Do not return, instead branch to second part of board
270 * initialization, now running from RAM.
271 */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]272 move.l %a0, %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]273 add.l #(in_ram - CFG_MONITOR_BASE), %a1
274 jmp (%a1)
275
276in_ram:
277
278clear_bss:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]279 /*
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]280 * Now clear BSS segment
281 */
282 move.l %a0, %a1
283 add.l #(_sbss - CFG_MONITOR_BASE),%a1
284 move.l %a0, %d1
285 add.l #(_ebss - CFG_MONITOR_BASE),%d1
2866:
287 clr.l (%a1)+
288 cmp.l %a1,%d1
289 bgt.s 6b
290
291 /*
292 * fix got table in RAM
293 */
294 move.l %a0, %a1
295 add.l #(__got_start - CFG_MONITOR_BASE),%a1
296 move.l %a1,%a5 /* * fix got pointer register a5 */
297
298 move.l %a0, %a2
299 add.l #(__got_end - CFG_MONITOR_BASE),%a2
300
3017:
302 move.l (%a1),%d1
303 sub.l #_start,%d1
304 add.l %a0,%d1
305 move.l %d1,(%a1)+
306 cmp.l %a2, %a1
307 bne 7b
308
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]309#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
310 /* patch the 3 accesspoints to 3 ichache_state */
311 /* quick and dirty */
312
313 move.l %a0,%d1
314 add.l #(icache_state - CFG_MONITOR_BASE),%d1
315 move.l %a0,%a1
316 add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
317 move.l %d1,(%a1)
318 move.l %a0,%a1
319 add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
320 move.l %d1,(%a1)
321 move.l %a0,%a1
322 add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
323 move.l %d1,(%a1)
324#endif
325
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]326 /* calculate relative jump to board_init_r in ram */
327 move.l %a0, %a1
328 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
329
330 /* set parameters for board_init_r */
331 move.l %a0,-(%sp) /* dest_addr */
332 move.l %d0,-(%sp) /* gd */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]333#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
334 defined(CFG_HALT_BEFOR_RAM_JUMP)
335 halt
336#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]337 jsr (%a1)
338
339/*------------------------------------------------------------------------------*/
340/* exception code */
341 .globl _fault
342_fault:
343 jmp _fault
344
345 .globl _exc_handler
346_exc_handler:
347 SAVE_ALL
348 movel %sp,%sp@-
349 bsr exc_handler
350 addql #4,%sp
351 RESTORE_ALL
352
353 .globl _int_handler
354_int_handler:
355 SAVE_ALL
356 movel %sp,%sp@-
357 bsr int_handler
358 addql #4,%sp
359 RESTORE_ALL
360
361/*------------------------------------------------------------------------------*/
362/* cache functions */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]363#ifdef CONFIG_M5271
364 .globl icache_enable
365icache_enable:
366 move.l #0x01000000, %d0 /* Invalidate cache cmd */
367 movec %d0, %CACR /* Invalidate cache */
368 move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
369 movec %d0, %ACR0 /* Enable cache */
370
371 move.l #0x80000200, %d0 /* Setup cache mask */
372 movec %d0, %CACR /* Enable cache */
373 nop
374
375 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
376 moveq #1, %d0
377 move.l %d0, (%a1)
378 rts
379#endif
380
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]381#ifdef CONFIG_M5272
382 .globl icache_enable
383icache_enable:
384 move.l #0x01000000, %d0 /* Invalidate cache cmd */
385 movec %d0, %CACR /* Invalidate cache */
386 move.l #0x0000c000, %d0 /* Setup cache mask */
387 movec %d0, %ACR0 /* Enable cache */
388 move.l #0xff00c000, %d0 /* Setup cache mask */
389 movec %d0, %ACR1 /* Enable cache */
390 move.l #0x80000100, %d0 /* Setup cache mask */
391 movec %d0, %CACR /* Enable cache */
392 moveq #1, %d0
393 move.l %d0, icache_state
394 rts
395#endif
396
397#ifdef CONFIG_M5282
398 .globl icache_enable
399icache_enable:
400 move.l #0x01000000, %d0 /* Invalidate cache cmd */
401 movec %d0, %CACR /* Invalidate cache */
402 move.l #0x0000c000, %d0 /* Setup cache mask */
403 movec %d0, %ACR0 /* Enable cache */
404 move.l #0xff00c000, %d0 /* Setup cache mask */
405 movec %d0, %ACR1 /* Enable cache */
406 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
407 movec %d0, %CACR /* Enable cache */
408 moveq #1, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]409icache_state_access_1:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]410 move.l %d0, icache_state
411 rts
412#endif
413
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]414#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]415 .globl icache_enable
416icache_enable:
417 /*
418 * Note: The 5249 Documentation doesn't give a bit position for CINV!
419 * From the 5272 and the 5307 documentation, I have deduced that it is
420 * probably CACR[24]. Should someone say something to Motorola?
421 * ~Jeremy
422 */
423 move.l #0x01000000, %d0 /* Invalidate whole cache */
424 move.c %d0,%CACR
425 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
426 move.c %d0, %ACR0
427 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
428 move.c %d0, %ACR1
429 move.l #0x90000200, %d0 /* Set cache enable cmd */
430 move.c %d0,%CACR
431 moveq #1, %d0
432 move.l %d0, icache_state
433 rts
434#endif
435
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]436 .globl icache_disable
437icache_disable:
438 move.l #0x00000100, %d0 /* Setup cache mask */
439 movec %d0, %CACR /* Enable cache */
440 clr.l %d0 /* Setup cache mask */
441 movec %d0, %ACR0 /* Enable cache */
442 movec %d0, %ACR1 /* Enable cache */
443 moveq #0, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]444icache_state_access_2:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]445 move.l %d0, icache_state
446 rts
447
448 .globl icache_status
449icache_status:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]450icache_state_access_3:
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]451 move.l #(icache_state), %a0
452 move.l (%a0), %d0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]453 rts
454
455 .data
456icache_state:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]457 .long 0 /* cache is diabled on inirialization */
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]458
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]459 .globl dcache_enable
460dcache_enable:
461 /* dummy function */
462 rts
463
464 .globl dcache_disable
465dcache_disable:
466 /* dummy function */
467 rts
468
469 .globl dcache_status
470dcache_status:
471 /* dummy function */
472 rts
473
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]474/*------------------------------------------------------------------------------*/
475
476 .globl version_string
477version_string:
478 .ascii U_BOOT_VERSION
479 .ascii " (", __DATE__, " - ", __TIME__, ")"
480 .ascii CONFIG_IDENT_STRING, "\0"