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wdenk041b1de2002-09-07 21:30:09 +00001/* originally from linux source.
2 * removed the dependencies on CONFIG_ values
3 * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
4 * Modified By Rob Taylor, Flying Pig Systems, 2000
5 */
6
7#ifndef _PPC_IO_H
8#define _PPC_IO_H
9
10#include <linux/config.h>
11#include <asm/byteorder.h>
12
Kumar Gala77c81152008-12-16 14:59:21 -060013#ifdef CONFIG_ADDR_MAP
14#include <addr_map.h>
15#endif
16
wdenk041b1de2002-09-07 21:30:09 +000017#define SIO_CONFIG_RA 0x398
18#define SIO_CONFIG_RD 0x399
19
Heiko Schocherf98984c2007-08-28 17:39:14 +020020#ifndef _IO_BASE
21#define _IO_BASE 0
22#endif
wdenk041b1de2002-09-07 21:30:09 +000023
24#define readb(addr) in_8((volatile u8 *)(addr))
25#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
26#if !defined(__BIG_ENDIAN)
27#define readw(addr) (*(volatile u16 *) (addr))
28#define readl(addr) (*(volatile u32 *) (addr))
29#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
30#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
31#else
32#define readw(addr) in_le16((volatile u16 *)(addr))
33#define readl(addr) in_le32((volatile u32 *)(addr))
34#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
35#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
36#endif
37
38/*
39 * The insw/outsw/insl/outsl macros don't do byte-swapping.
40 * They are only used in practice for transferring buffers which
41 * are arrays of bytes, and byte-swapping is not appropriate in
42 * that case. - paulus
43 */
44#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
45#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
46#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
47#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
48#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
49#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
50
51#define inb(port) in_8((u8 *)((port)+_IO_BASE))
52#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
53#if !defined(__BIG_ENDIAN)
54#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
55#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
56#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
57#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
58#else
59#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
60#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
61#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
62#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
63#endif
64
65#define inb_p(port) in_8((u8 *)((port)+_IO_BASE))
66#define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
67#define inw_p(port) in_le16((u16 *)((port)+_IO_BASE))
68#define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
69#define inl_p(port) in_le32((u32 *)((port)+_IO_BASE))
70#define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
71
72extern void _insb(volatile u8 *port, void *buf, int ns);
73extern void _outsb(volatile u8 *port, const void *buf, int ns);
74extern void _insw(volatile u16 *port, void *buf, int ns);
75extern void _outsw(volatile u16 *port, const void *buf, int ns);
76extern void _insl(volatile u32 *port, void *buf, int nl);
77extern void _outsl(volatile u32 *port, const void *buf, int nl);
78extern void _insw_ns(volatile u16 *port, void *buf, int ns);
79extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
80extern void _insl_ns(volatile u32 *port, void *buf, int nl);
81extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
82
83/*
84 * The *_ns versions below don't do byte-swapping.
85 * Neither do the standard versions now, these are just here
86 * for older code.
87 */
88#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
89#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
90#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
91#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
92
93
94#define IO_SPACE_LIMIT ~0
95
96#define memset_io(a,b,c) memset((void *)(a),(b),(c))
97#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
98#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
99
100/*
101 * Enforce In-order Execution of I/O:
102 * Acts as a barrier to ensure all previous I/O accesses have
103 * completed before any further ones are issued.
104 */
Haiying Wang3a197b22007-02-21 16:52:31 +0100105static inline void eieio(void)
106{
107 __asm__ __volatile__ ("eieio" : : : "memory");
108}
109
110static inline void sync(void)
111{
112 __asm__ __volatile__ ("sync" : : : "memory");
113}
wdenk041b1de2002-09-07 21:30:09 +0000114
Stefan Roese53ad0212007-06-01 15:16:58 +0200115static inline void isync(void)
116{
117 __asm__ __volatile__ ("isync" : : : "memory");
118}
119
wdenk041b1de2002-09-07 21:30:09 +0000120/* Enforce in-order execution of data I/O.
121 * No distinction between read/write on PPC; use eieio for all three.
122 */
123#define iobarrier_rw() eieio()
124#define iobarrier_r() eieio()
125#define iobarrier_w() eieio()
126
127/*
Haavard Skinnemoen812711c2007-12-13 12:56:31 +0100128 * Non ordered and non-swapping "raw" accessors
129 */
130#define __iomem
131#define PCI_FIX_ADDR(addr) (addr)
132
133static inline unsigned char __raw_readb(const volatile void __iomem *addr)
134{
135 return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
136}
137static inline unsigned short __raw_readw(const volatile void __iomem *addr)
138{
139 return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
140}
141static inline unsigned int __raw_readl(const volatile void __iomem *addr)
142{
143 return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
144}
145static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
146{
147 *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
148}
149static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
150{
151 *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
152}
153static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
154{
155 *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
156}
157
158/*
wdenk041b1de2002-09-07 21:30:09 +0000159 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
Stefan Roese53ad0212007-06-01 15:16:58 +0200160 *
161 * Read operations have additional twi & isync to make sure the read
162 * is actually performed (i.e. the data has come back) before we start
163 * executing any following instructions.
wdenk041b1de2002-09-07 21:30:09 +0000164 */
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000165static inline u8 in_8(const volatile unsigned char __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000166{
Prabhakar Kushwahaa16a5cc2012-04-10 22:48:59 +0000167 u8 ret;
wdenk041b1de2002-09-07 21:30:09 +0000168
Stefan Roese53ad0212007-06-01 15:16:58 +0200169 __asm__ __volatile__(
170 "sync; lbz%U1%X1 %0,%1;\n"
171 "twi 0,%0,0;\n"
172 "isync" : "=r" (ret) : "m" (*addr));
173 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000174}
175
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000176static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
wdenk041b1de2002-09-07 21:30:09 +0000177{
Timur Tabi1fade702010-12-03 09:03:46 +0000178 __asm__ __volatile__("sync;\n"
179 "stb%U0%X0 %1,%0;\n"
180 : "=m" (*addr)
181 : "r" (val));
wdenk041b1de2002-09-07 21:30:09 +0000182}
183
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000184static inline u16 in_le16(const volatile unsigned short __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000185{
Prabhakar Kushwahaa16a5cc2012-04-10 22:48:59 +0000186 u16 ret;
wdenk041b1de2002-09-07 21:30:09 +0000187
Stefan Roese53ad0212007-06-01 15:16:58 +0200188 __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
189 "twi 0,%0,0;\n"
190 "isync" : "=r" (ret) :
191 "r" (addr), "m" (*addr));
192 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000193}
194
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000195static inline u16 in_be16(const volatile unsigned short __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000196{
Prabhakar Kushwahaa16a5cc2012-04-10 22:48:59 +0000197 u16 ret;
wdenk041b1de2002-09-07 21:30:09 +0000198
Stefan Roese53ad0212007-06-01 15:16:58 +0200199 __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
200 "twi 0,%0,0;\n"
201 "isync" : "=r" (ret) : "m" (*addr));
202 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000203}
204
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000205static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
wdenk041b1de2002-09-07 21:30:09 +0000206{
Stefan Roese53ad0212007-06-01 15:16:58 +0200207 __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
208 "r" (val), "r" (addr));
wdenk041b1de2002-09-07 21:30:09 +0000209}
210
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000211static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
wdenk041b1de2002-09-07 21:30:09 +0000212{
Stefan Roese53ad0212007-06-01 15:16:58 +0200213 __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
wdenk041b1de2002-09-07 21:30:09 +0000214}
215
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000216static inline u32 in_le32(const volatile unsigned __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000217{
Prabhakar Kushwahaa16a5cc2012-04-10 22:48:59 +0000218 u32 ret;
wdenk041b1de2002-09-07 21:30:09 +0000219
Stefan Roese53ad0212007-06-01 15:16:58 +0200220 __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
221 "twi 0,%0,0;\n"
222 "isync" : "=r" (ret) :
223 "r" (addr), "m" (*addr));
224 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000225}
226
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000227static inline u32 in_be32(const volatile unsigned __iomem *addr)
wdenk041b1de2002-09-07 21:30:09 +0000228{
Prabhakar Kushwahaa16a5cc2012-04-10 22:48:59 +0000229 u32 ret;
wdenk041b1de2002-09-07 21:30:09 +0000230
Stefan Roese53ad0212007-06-01 15:16:58 +0200231 __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
232 "twi 0,%0,0;\n"
233 "isync" : "=r" (ret) : "m" (*addr));
234 return ret;
wdenk041b1de2002-09-07 21:30:09 +0000235}
236
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000237static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
wdenk041b1de2002-09-07 21:30:09 +0000238{
Stefan Roese53ad0212007-06-01 15:16:58 +0200239 __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
240 "r" (val), "r" (addr));
wdenk041b1de2002-09-07 21:30:09 +0000241}
242
Prabhakar Kushwaha20959472012-04-10 22:49:12 +0000243static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
wdenk041b1de2002-09-07 21:30:09 +0000244{
Stefan Roese53ad0212007-06-01 15:16:58 +0200245 __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
wdenk041b1de2002-09-07 21:30:09 +0000246}
247
Wolfgang Grandegger39841512008-06-04 12:45:22 +0200248/* Clear and set bits in one shot. These macros can be used to clear and
249 * set multiple bits in a register using a single call. These macros can
250 * also be used to set a multiple-bit bit pattern using a mask, by
251 * specifying the mask in the 'clear' parameter and the new bit pattern
252 * in the 'set' parameter.
253 */
254
255#define clrbits(type, addr, clear) \
256 out_##type((addr), in_##type(addr) & ~(clear))
257
258#define setbits(type, addr, set) \
259 out_##type((addr), in_##type(addr) | (set))
260
261#define clrsetbits(type, addr, clear, set) \
262 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
263
264#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
265#define setbits_be32(addr, set) setbits(be32, addr, set)
266#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
267
268#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
269#define setbits_le32(addr, set) setbits(le32, addr, set)
270#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
271
272#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
273#define setbits_be16(addr, set) setbits(be16, addr, set)
274#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
275
276#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
277#define setbits_le16(addr, set) setbits(le16, addr, set)
278#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
279
280#define clrbits_8(addr, clear) clrbits(8, addr, clear)
281#define setbits_8(addr, set) setbits(8, addr, set)
282#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
283
Haavard Skinnemoen4d7d6932007-12-13 12:56:33 +0100284/*
285 * Given a physical address and a length, return a virtual address
286 * that can be used to access the memory range with the caching
287 * properties specified by "flags".
288 */
Haavard Skinnemoen4d7d6932007-12-13 12:56:33 +0100289#define MAP_NOCACHE (0)
290#define MAP_WRCOMBINE (0)
291#define MAP_WRBACK (0)
292#define MAP_WRTHROUGH (0)
293
294static inline void *
295map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
296{
Kumar Gala77c81152008-12-16 14:59:21 -0600297#ifdef CONFIG_ADDR_MAP
Timur Tabi7b6e8052012-05-04 12:21:30 +0000298 return addrmap_phys_to_virt(paddr);
Kumar Gala77c81152008-12-16 14:59:21 -0600299#else
Becky Brucef3612a72008-05-07 13:28:16 -0500300 return (void *)((unsigned long)paddr);
Kumar Gala77c81152008-12-16 14:59:21 -0600301#endif
Haavard Skinnemoen4d7d6932007-12-13 12:56:33 +0100302}
303
304/*
305 * Take down a mapping set up by map_physmem().
306 */
307static inline void unmap_physmem(void *vaddr, unsigned long flags)
308{
309
310}
311
Kumar Gala65e43a12008-12-13 17:20:27 -0600312static inline phys_addr_t virt_to_phys(void * vaddr)
313{
Kumar Gala77c81152008-12-16 14:59:21 -0600314#ifdef CONFIG_ADDR_MAP
315 return addrmap_virt_to_phys(vaddr);
316#else
Becky Bruceb1ffece2008-12-03 23:04:37 -0600317 return (phys_addr_t)((unsigned long)vaddr);
Kumar Gala77c81152008-12-16 14:59:21 -0600318#endif
Kumar Gala65e43a12008-12-13 17:20:27 -0600319}
320
wdenk041b1de2002-09-07 21:30:09 +0000321#endif