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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 709b384b6493d9726dce20663ebe31bf7cab2925 / . / cpu / mcf5445x / start.S
blob: c156bab037fa8d8a72738601de2721db50a385d2 [file] [log] [blame]
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]25#include <timestamp.h>
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]26#include "version.h"
27
28#ifndef CONFIG_IDENT_STRING
29#define CONFIG_IDENT_STRING ""
30#endif
31
32/* last three long word reserved for cache status */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]33#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
34#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
35#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]36
37#define _START _start
38#define _FAULT _fault
39
40#define SAVE_ALL \
41 move.w #0x2700,%sr; /* disable intrs */ \
42 subl #60,%sp; /* space for 15 regs */ \
43 moveml %d0-%d7/%a0-%a6,%sp@;
44
45#define RESTORE_ALL \
46 moveml %sp@,%d0-%d7/%a0-%a6; \
47 addl #60,%sp; /* space for 15 regs */ \
48 rte;
49
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]50#if defined(CONFIG_CF_SBF)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]51#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
52#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]53#endif
54
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]55.text
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]56
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]57/*
58 * Vector table. This is used for initial platform startup.
59 * These vectors are to catch any un-intended traps.
60 */
61_vectors:
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]62#if defined(CONFIG_CF_SBF)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]63
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]64INITSP: .long 0 /* Initial SP */
65INITPC: .long ASM_DRAMINIT /* Initial PC */
66
67#else
68
69INITSP: .long 0 /* Initial SP */
70INITPC: .long _START /* Initial PC */
71
72#endif
73
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]74vector02: .long _FAULT /* Access Error */
75vector03: .long _FAULT /* Address Error */
76vector04: .long _FAULT /* Illegal Instruction */
77vector05: .long _FAULT /* Reserved */
78vector06: .long _FAULT /* Reserved */
79vector07: .long _FAULT /* Reserved */
80vector08: .long _FAULT /* Privilege Violation */
81vector09: .long _FAULT /* Trace */
82vector0A: .long _FAULT /* Unimplemented A-Line */
83vector0B: .long _FAULT /* Unimplemented F-Line */
84vector0C: .long _FAULT /* Debug Interrupt */
85vector0D: .long _FAULT /* Reserved */
86vector0E: .long _FAULT /* Format Error */
87vector0F: .long _FAULT /* Unitialized Int. */
88
89/* Reserved */
90vector10_17:
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92
93vector18: .long _FAULT /* Spurious Interrupt */
94vector19: .long _FAULT /* Autovector Level 1 */
95vector1A: .long _FAULT /* Autovector Level 2 */
96vector1B: .long _FAULT /* Autovector Level 3 */
97vector1C: .long _FAULT /* Autovector Level 4 */
98vector1D: .long _FAULT /* Autovector Level 5 */
99vector1E: .long _FAULT /* Autovector Level 6 */
100vector1F: .long _FAULT /* Autovector Level 7 */
101
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]102#if !defined(CONFIG_CF_SBF)
103
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]104/* TRAP #0 - #15 */
105vector20_2F:
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108
109/* Reserved */
110vector30_3F:
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113
114vector64_127:
115.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
122.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
123
124vector128_191:
125.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
126.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
127.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
128.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
129.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
130.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
131.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
132.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
133
134vector192_255:
135.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
136.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
137.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
138.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
139.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
140.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
141.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
142.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]143#endif
144
145#if defined(CONFIG_CF_SBF)
146 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
147asm_sbf_img_hdr:
148 .long 0x00000000 /* checksum, not yet implemented */
149 .long 0x00030000 /* image length */
150 .long TEXT_BASE /* image to be relocated at */
151
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]152
153
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]154asm_dram_init:
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]155 move.w #0x2700,%sr /* Mask off Interrupt */
156
157 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
158 movec %d0, %VBR
159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]160 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]161 movec %d0, %RAMBAR1
162
163 /* initialize general use internal ram */
164 move.l #0, %d0
165 move.l #(CACR_STATUS), %a1 /* CACR */
166 move.l #(ICACHE_STATUS), %a2 /* icache */
167 move.l #(DCACHE_STATUS), %a3 /* dcache */
168 move.l %d0, (%a1)
169 move.l %d0, (%a2)
170 move.l %d0, (%a3)
171
172 /* invalidate and disable cache */
173 move.l #0x01004100, %d0 /* Invalidate cache cmd */
174 movec %d0, %CACR /* Invalidate cache */
175 move.l #0, %d0
176 movec %d0, %ACR0
177 movec %d0, %ACR1
178 movec %d0, %ACR2
179 movec %d0, %ACR3
180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]181 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]182 clr.l %sp@-
183
184 /* Must disable global address */
185 move.l #0xFC008000, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]186 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]187 move.l #0xFC008008, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]188 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]189 move.l #0xFC008004, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]190 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]191
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]192 /* Dram Initialization a1, a2, and d0 */
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]193 /* mscr sdram */
194 move.l #0xFC0A4074, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]195 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]196 nop
197
198 /* SDRAM Chip 0 and 1 */
199 move.l #0xFC0B8110, %a1
200 move.l #0xFC0B8114, %a2
201
202 /* calculate the size */
203 move.l #0x13, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]204 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
205#ifdef CONFIG_SYS_SDRAM_BASE1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]206 lsr.l #1, %d2
207#endif
208
209dramsz_loop:
210 lsr.l #1, %d2
211 add.l #1, %d1
212 cmp.l #1, %d2
213 bne dramsz_loop
214
215 /* SDRAM Chip 0 and 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]216 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]217 or.l %d1, (%a1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]218#ifdef CONFIG_SYS_SDRAM_BASE1
219 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]220 or.l %d1, (%a2)
221#endif
222 nop
223
224 /* dram cfg1 and cfg2 */
225 move.l #0xFC0B8008, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]226 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]227 nop
228 move.l #0xFC0B800C, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]229 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]230 nop
231
232 move.l #0xFC0B8000, %a1 /* Mode */
233 move.l #0xFC0B8004, %a2 /* Ctrl */
234
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]235 /* Issue PALL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]236 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]237 nop
238
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]239#ifdef CONFIG_M54455EVB
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]240 /* Issue LEMR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]241 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]242 nop
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]243 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]244 nop
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]245#endif
246
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]247 move.l #1000, %d1
248 jsr asm_delay
249
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]250 /* Issue PALL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]251 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]252 nop
253
254 /* Perform two refresh cycles */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]255 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]256 nop
257 move.l %d0, (%a2)
258 move.l %d0, (%a2)
259 nop
260
261#ifdef CONFIG_M54455EVB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]262 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]263 nop
264#elif defined(CONFIG_M54451EVB)
265 /* Issue LEMR */
TsiChung Liewc3a9e632009-02-18 11:49:31 +0000[diff] [blame]266 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]267 nop
TsiChung Liewc3a9e632009-02-18 11:49:31 +0000[diff] [blame]268 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]269#endif
270
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]271 move.l #500, %d1
272 jsr asm_delay
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]273
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]274 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
275 and.l #0x7FFFFFFF, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]276#ifdef CONFIG_M54455EVB
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]277 or.l #0x10000C00, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]278#elif defined(CONFIG_M54451EVB)
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]279 or.l #0x10000C00, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]280#endif
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]281 move.l %d1, (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]282 nop
283
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]284 move.l #2000, %d1
285 jsr asm_delay
286
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]287 /*
288 * DSPI Initialization
289 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
290 * a1 - dspi status
291 * a2 - dtfr
292 * a3 - drfr
293 * a4 - Dst addr
294 */
295 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]296asm_dspi_init:
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]297 move.l #0xFC0A4063, %a0
298 move.b #0x7F, (%a0)
299
300 /* Configure DSPI module */
301 move.l #0xFC05C000, %a0
302 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
303
304 move.l #0xFC05C00C, %a0
305 move.l #0x3E000011, (%a0)
306
307 move.l #0xFC05C034, %a2 /* dtfr */
308 move.l #0xFC05C03B, %a3 /* drfr */
309
310 move.l #(ASM_SBF_IMG_HDR + 4), %a1
311 move.l (%a1)+, %d5
312 move.l (%a1), %a4
313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]314 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
315 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]316
317 move.l #0xFC05C02C, %a1 /* dspi status */
318
319 /* Issue commands and address */
320 move.l #0x8002000B, %d2 /* Fast Read Cmd */
321 jsr asm_dspi_wr_status
322 jsr asm_dspi_rd_status
323
324 move.l #0x80020000, %d2 /* Address byte 2 */
325 jsr asm_dspi_wr_status
326 jsr asm_dspi_rd_status
327
328 move.l #0x80020000, %d2 /* Address byte 1 */
329 jsr asm_dspi_wr_status
330 jsr asm_dspi_rd_status
331
332 move.l #0x80020000, %d2 /* Address byte 0 */
333 jsr asm_dspi_wr_status
334 jsr asm_dspi_rd_status
335
336 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
337 jsr asm_dspi_wr_status
338 jsr asm_dspi_rd_status
339
340 /* Transfer serial boot header to sram */
341asm_dspi_rd_loop1:
342 move.l #0x80020000, %d2
343 jsr asm_dspi_wr_status
344 jsr asm_dspi_rd_status
345
346 move.b %d1, (%a0) /* read, copy to dst */
347
348 add.l #1, %a0 /* inc dst by 1 */
349 sub.l #1, %d4 /* dec cnt by 1 */
350 bne asm_dspi_rd_loop1
351
352 /* Transfer u-boot from serial flash to memory */
353asm_dspi_rd_loop2:
354 move.l #0x80020000, %d2
355 jsr asm_dspi_wr_status
356 jsr asm_dspi_rd_status
357
358 move.b %d1, (%a4) /* read, copy to dst */
359
360 add.l #1, %a4 /* inc dst by 1 */
361 sub.l #1, %d5 /* dec cnt by 1 */
362 bne asm_dspi_rd_loop2
363
364 move.l #0x00020000, %d2 /* Terminate */
365 jsr asm_dspi_wr_status
366 jsr asm_dspi_rd_status
367
368 /* jump to memory and execute */
369 move.l #(TEXT_BASE + 0x400), %a0
370 jmp (%a0)
371
372asm_dspi_wr_status:
373 move.l (%a1), %d0 /* status */
374 and.l #0x0000F000, %d0
375 cmp.l #0x00003000, %d0
376 bgt asm_dspi_wr_status
377
378 move.l %d2, (%a2)
379 rts
380
381asm_dspi_rd_status:
382 move.l (%a1), %d0 /* status */
383 and.l #0x000000F0, %d0
384 lsr.l #4, %d0
385 cmp.l #0, %d0
386 beq asm_dspi_rd_status
387
388 move.b (%a3), %d1
389 rts
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]390
391asm_delay:
392 nop
393 subq.l #1, %d1
394 bne asm_delay
395 rts
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]396#endif /* CONFIG_CF_SBF */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]397
398 .text
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]399 . = 0x400
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]400 .globl _start
401_start:
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]402#if !defined(CONFIG_CF_SBF)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]403 nop
404 nop
405 move.w #0x2700,%sr /* Mask off Interrupt */
406
407 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]408 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]409 movec %d0, %VBR
410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]411 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew225a24b2007-11-07 18:00:54 -0600[diff] [blame]412 movec %d0, %RAMBAR1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]413
414 /* initialize general use internal ram */
415 move.l #0, %d0
416 move.l #(CACR_STATUS), %a1 /* CACR */
417 move.l #(ICACHE_STATUS), %a2 /* icache */
418 move.l #(DCACHE_STATUS), %a3 /* dcache */
419 move.l %d0, (%a1)
420 move.l %d0, (%a2)
421 move.l %d0, (%a3)
422
423 /* invalidate and disable cache */
424 move.l #0x01004100, %d0 /* Invalidate cache cmd */
425 movec %d0, %CACR /* Invalidate cache */
426 move.l #0, %d0
427 movec %d0, %ACR0
428 movec %d0, %ACR1
429 movec %d0, %ACR2
430 movec %d0, %ACR3
431
432 /* set stackpointer to end of internal ram to get some stackspace for
433 the first c-code */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]434 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]435 clr.l %sp@-
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]436#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]437
438 move.l #__got_start, %a5 /* put relocation table address to a5 */
439
440 bsr cpu_init_f /* run low-level CPU init code (from flash) */
441 bsr board_init_f /* run low-level board init code (from flash) */
442
443 /* board_init_f() does not return */
444
445/*------------------------------------------------------------------------------*/
446
447/*
448 * void relocate_code (addr_sp, gd, addr_moni)
449 *
450 * This "function" does not return, instead it continues in RAM
451 * after relocating the monitor code.
452 *
453 * r3 = dest
454 * r4 = src
455 * r5 = length in bytes
456 * r6 = cachelinesize
457 */
458 .globl relocate_code
459relocate_code:
460 link.w %a6,#0
461 move.l 8(%a6), %sp /* set new stack pointer */
462
463 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
464 move.l 16(%a6), %a0 /* Save copy of Destination Address */
465
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]466 move.l #CONFIG_SYS_MONITOR_BASE, %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]467 move.l #__init_end, %a2
468 move.l %a0, %a3
469
470 /* copy the code to RAM */
4711:
472 move.l (%a1)+, (%a3)+
473 cmp.l %a1,%a2
474 bgt.s 1b
475
476/*
477 * We are done. Do not return, instead branch to second part of board
478 * initialization, now running from RAM.
479 */
480 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]481 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]482 jmp (%a1)
483
484in_ram:
485
486clear_bss:
487 /*
488 * Now clear BSS segment
489 */
490 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]491 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]492 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]493 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]4946:
495 clr.l (%a1)+
496 cmp.l %a1,%d1
497 bgt.s 6b
498
499 /*
500 * fix got table in RAM
501 */
502 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]503 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]504 move.l %a1,%a5 /* * fix got pointer register a5 */
505
506 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]507 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]508
5097:
510 move.l (%a1),%d1
511 sub.l #_start,%d1
512 add.l %a0,%d1
513 move.l %d1,(%a1)+
514 cmp.l %a2, %a1
515 bne 7b
516
517 /* calculate relative jump to board_init_r in ram */
518 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]519 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]520
521 /* set parameters for board_init_r */
522 move.l %a0,-(%sp) /* dest_addr */
523 move.l %d0,-(%sp) /* gd */
524 jsr (%a1)
525
526/*------------------------------------------------------------------------------*/
527/* exception code */
528 .globl _fault
529_fault:
TsiChung Liew3b1e8ac2008-06-18 19:12:13 -0500[diff] [blame]530 bra _fault
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]531 .globl _exc_handler
532
533_exc_handler:
534 SAVE_ALL
535 movel %sp,%sp@-
536 bsr exc_handler
537 addql #4,%sp
538 RESTORE_ALL
539
540 .globl _int_handler
541_int_handler:
542 SAVE_ALL
543 movel %sp,%sp@-
544 bsr int_handler
545 addql #4,%sp
546 RESTORE_ALL
547
548/*------------------------------------------------------------------------------*/
549/* cache functions */
550 .globl icache_enable
551icache_enable:
552 move.l #(CACR_STATUS), %a1 /* read CACR Status */
553 move.l (%a1), %d1
554
555 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]556 movec %d0, %CACR
557
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame^]558 move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]559 movec %d0, %ACR2
560
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]561 move.l #0x04088020, %d0 /* Enable bcache and icache */
562 movec %d0, %CACR
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]563
564 move.l #(ICACHE_STATUS), %a1
565 moveq #1, %d0
566 move.l %d0, (%a1)
567 rts
568
569 .globl icache_disable
570icache_disable:
571 move.l #(CACR_STATUS), %a1 /* read CACR Status */
572 move.l (%a1), %d0
573
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]574 move.l #0xFFF77BFF, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]575 or.l #0x00040100, %d0 /* Setup cache mask */
576 movec %d0, %CACR /* Invalidate icache */
577 clr.l %d0
578 movec %d0, %ACR2
579 movec %d0, %ACR3
580
581 move.l #(ICACHE_STATUS), %a1
582 moveq #0, %d0
583 move.l %d0, (%a1)
584 rts
585
586 .globl icache_status
587icache_status:
588 move.l #(ICACHE_STATUS), %a1
589 move.l (%a1), %d0
590 rts
591
592 .globl icache_invalid
593icache_invalid:
594 move.l #(CACR_STATUS), %a1 /* read CACR Status */
595 move.l (%a1), %d0
596
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]597 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]598 movec %d0, %CACR /* Enable and invalidate cache */
599 rts
600
601 .globl dcache_enable
602dcache_enable:
603 move.l #(CACR_STATUS), %a1 /* read CACR Status */
604 move.l (%a1), %d1
605
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]606 move.l #0x01040100, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]607 movec %d0, %CACR /* Invalidate dcache */
608
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]609 move.l #0x80088020, %d0 /* Enable bcache and icache */
610 movec %d0, %CACR
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]611
612 move.l #(DCACHE_STATUS), %a1
613 moveq #1, %d0
614 move.l %d0, (%a1)
615 rts
616
617 .globl dcache_disable
618dcache_disable:
619 move.l #(CACR_STATUS), %a1 /* read CACR Status */
620 move.l (%a1), %d0
621
622 and.l #0x7FFFFFFF, %d0
623 or.l #0x01000000, %d0 /* Setup cache mask */
624 movec %d0, %CACR /* Disable dcache */
625 clr.l %d0
626 movec %d0, %ACR0
627 movec %d0, %ACR1
628
629 move.l #(DCACHE_STATUS), %a1
630 moveq #0, %d0
631 move.l %d0, (%a1)
632 rts
633
634 .globl dcache_invalid
635dcache_invalid:
636 move.l #(CACR_STATUS), %a1 /* read CACR Status */
637 move.l (%a1), %d0
638
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]639 move.l #0x81088020, %d0 /* Setup cache mask */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]640 movec %d0, %CACR /* Enable and invalidate cache */
641 rts
642
643 .globl dcache_status
644dcache_status:
645 move.l #(DCACHE_STATUS), %a1
646 move.l (%a1), %d0
647 rts
648
649/*------------------------------------------------------------------------------*/
650
651 .globl version_string
652version_string:
653 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]654 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]655 .ascii CONFIG_IDENT_STRING, "\0"
TsiChung Liew9b464322008-03-28 08:47:45 -0500[diff] [blame]656 .align 4