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Alison Wang186fc4d2012-10-18 19:25:52 +00001/*
2 * Configuation settings for the Freescale MCF54418 TWR board.
3 *
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Alison Wang186fc4d2012-10-18 19:25:52 +00008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M54418TWR_H
15#define _M54418TWR_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
Alison Wang186fc4d2012-10-18 19:25:52 +000021#define CONFIG_M54418TWR /* M54418TWR board */
22
23#define CONFIG_MCFUART
24#define CONFIG_SYS_UART_PORT (0)
25#define CONFIG_BAUDRATE 115200
26#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
27
28#undef CONFIG_WATCHDOG
29
30#define CONFIG_TIMESTAMP /* Print image info with timestamp */
31
32/*
33 * BOOTP options
34 */
35#define CONFIG_BOOTP_BOOTFILESIZE
36#define CONFIG_BOOTP_BOOTPATH
37#define CONFIG_BOOTP_GATEWAY
38#define CONFIG_BOOTP_HOSTNAME
39
40/* Command line configuration */
Alison Wang186fc4d2012-10-18 19:25:52 +000041#undef CONFIG_CMD_DATE
Alison Wang186fc4d2012-10-18 19:25:52 +000042#undef CONFIG_CMD_JFFS2
Alison Wang186fc4d2012-10-18 19:25:52 +000043#undef CONFIG_CMD_NAND
Alison Wang186fc4d2012-10-18 19:25:52 +000044#define CONFIG_CMD_REGINFO
Alison Wang186fc4d2012-10-18 19:25:52 +000045
46/*
47 * NAND FLASH
48 */
49#ifdef CONFIG_CMD_NAND
50#define CONFIG_JFFS2_NAND
51#define CONFIG_NAND_FSL_NFC
52#define CONFIG_SYS_NAND_BASE 0xFC0FC000
53#define CONFIG_SYS_MAX_NAND_DEVICE 1
54#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
55#define CONFIG_SYS_NAND_SELECT_DEVICE
Alison Wang186fc4d2012-10-18 19:25:52 +000056#endif
57
58/* Network configuration */
59#define CONFIG_MCFFEC
60#ifdef CONFIG_MCFFEC
Alison Wang186fc4d2012-10-18 19:25:52 +000061#define CONFIG_MII 1
62#define CONFIG_MII_INIT 1
63#define CONFIG_SYS_DISCOVER_PHY
64#define CONFIG_SYS_RX_ETH_BUFFER 2
65#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
66#define CONFIG_SYS_TX_ETH_BUFFER 2
67#define CONFIG_HAS_ETH1
68
69#define CONFIG_SYS_FEC0_PINMUX 0
70#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
71#define CONFIG_SYS_FEC1_PINMUX 0
72#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
73#define MCFFEC_TOUT_LOOP 50000
74#define CONFIG_SYS_FEC0_PHYADDR 0
75#define CONFIG_SYS_FEC1_PHYADDR 1
76
Alison Wang186fc4d2012-10-18 19:25:52 +000077
78#ifdef CONFIG_SYS_NAND_BOOT
79#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
80 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
81 "-(jffs2) console=ttyS0,115200"
82#else
83#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
84 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
85 __stringify(CONFIG_IPADDR) " ip=" \
86 __stringify(CONFIG_IPADDR) ":" \
87 __stringify(CONFIG_SERVERIP)":" \
88 __stringify(CONFIG_GATEWAYIP)": " \
89 __stringify(CONFIG_NETMASK) \
90 "::eth0:off:rw console=ttyS0,115200"
91#endif
92
Alison Wang186fc4d2012-10-18 19:25:52 +000093#define CONFIG_ETHPRIME "FEC0"
94#define CONFIG_IPADDR 192.168.1.2
95#define CONFIG_NETMASK 255.255.255.0
96#define CONFIG_SERVERIP 192.168.1.1
97#define CONFIG_GATEWAYIP 192.168.1.1
98
Alison Wang186fc4d2012-10-18 19:25:52 +000099#define CONFIG_SYS_FEC_BUF_USE_SRAM
100/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
101#ifndef CONFIG_SYS_DISCOVER_PHY
102#define FECDUPLEX FULL
103#define FECSPEED _100BASET
104#define LINKSTATUS 1
105#else
106#define LINKSTATUS 0
107#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
108#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
109#endif
110#endif /* CONFIG_SYS_DISCOVER_PHY */
111#endif
112
113#define CONFIG_HOSTNAME M54418TWR
114
115#if defined(CONFIG_CF_SBF)
116/* ST Micro serial flash */
117#define CONFIG_SYS_LOAD_ADDR2 0x40010007
118#define CONFIG_EXTRA_ENV_SETTINGS \
119 "netdev=eth0\0" \
120 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
121 "loadaddr=0x40010000\0" \
122 "sbfhdr=sbfhdr.bin\0" \
123 "uboot=u-boot.bin\0" \
124 "load=tftp ${loadaddr} ${sbfhdr};" \
125 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
126 "upd=run load; run prog\0" \
127 "prog=sf probe 0:1 1000000 3;" \
128 "sf erase 0 40000;" \
129 "sf write ${loadaddr} 0 40000;" \
130 "save\0" \
131 ""
132#elif defined(CONFIG_SYS_NAND_BOOT)
133#define CONFIG_EXTRA_ENV_SETTINGS \
134 "netdev=eth0\0" \
135 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
136 "loadaddr=0x40010000\0" \
137 "u-boot=u-boot.bin\0" \
138 "load=tftp ${loadaddr} ${u-boot};\0" \
139 "upd=run load; run prog\0" \
140 "prog=nand device 0;" \
141 "nand erase 0 40000;" \
142 "nb_update ${loadaddr} ${filesize};" \
143 "save\0" \
144 ""
145#else
146#define CONFIG_SYS_UBOOT_END 0x3FFFF
147#define CONFIG_EXTRA_ENV_SETTINGS \
148 "netdev=eth0\0" \
149 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
150 "loadaddr=40010000\0" \
151 "u-boot=u-boot.bin\0" \
152 "load=tftp ${loadaddr) ${u-boot}\0" \
153 "upd=run load; run prog\0" \
154 "prog=prot off mram" " ;" \
155 "cp.b ${loadaddr} 0 ${filesize};" \
156 "save\0" \
157 ""
158#endif
159
160/* Realtime clock */
161#undef CONFIG_MCFRTC
162#define CONFIG_RTC_MCFRRTC
163#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
164
165/* Timer */
166#define CONFIG_MCFTMR
167#undef CONFIG_MCFPIT
168
169/* I2c */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200170#undef CONFIG_SYS_FSL_I2C
Alison Wang186fc4d2012-10-18 19:25:52 +0000171#undef CONFIG_HARD_I2C /* I2C with hardware support */
Heiko Schocherea818db2013-01-29 08:53:15 +0100172#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
Alison Wang186fc4d2012-10-18 19:25:52 +0000173/* I2C speed and slave address */
174#define CONFIG_SYS_I2C_SPEED 80000
175#define CONFIG_SYS_I2C_SLAVE 0x7F
176#define CONFIG_SYS_I2C_OFFSET 0x58000
177#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
178
179/* DSPI and Serial Flash */
180#define CONFIG_CF_SPI
181#define CONFIG_CF_DSPI
182#define CONFIG_SERIAL_FLASH
183#define CONFIG_HARD_SPI
184#define CONFIG_SYS_SBFHDR_SIZE 0x7
185#ifdef CONFIG_CMD_SPI
Alison Wang186fc4d2012-10-18 19:25:52 +0000186
187# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
188 DSPI_CTAR_PCSSCK_1CLK | \
189 DSPI_CTAR_PASC(0) | \
190 DSPI_CTAR_PDT(0) | \
191 DSPI_CTAR_CSSCK(0) | \
192 DSPI_CTAR_ASC(0) | \
193 DSPI_CTAR_DT(1))
194# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
195# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
196#endif
197
198/* Input, PCI, Flexbus, and VCO */
199#define CONFIG_EXTRA_CLOCK
200
201#define CONFIG_PRAM 2048 /* 2048 KB */
202
Alison Wang186fc4d2012-10-18 19:25:52 +0000203#define CONFIG_SYS_LONGHELP /* undef to save memory */
204
205#if defined(CONFIG_CMD_KGDB)
206#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
207#else
208#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
209#endif
210/* Print Buffer Size */
211#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
212 sizeof(CONFIG_SYS_PROMPT) + 16)
213#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
214/* Boot Argument Buffer Size */
215#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
216
217#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
218
Alison Wang186fc4d2012-10-18 19:25:52 +0000219#define CONFIG_SYS_MBAR 0xFC000000
220
221/*
222 * Low Level Configuration Settings
223 * (address mappings, register initial values, etc.)
224 * You should know what you are doing if you make changes here.
225 */
226
227/*-----------------------------------------------------------------------
228 * Definitions for initial stack pointer and data area (in DPRAM)
229 */
230#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
231/* End of used area in internal SRAM */
232#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
233#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Alison Wang186fc4d2012-10-18 19:25:52 +0000234#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900235 GENERATED_GBL_DATA_SIZE) - 32)
Alison Wang186fc4d2012-10-18 19:25:52 +0000236#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
237#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
238
239/*-----------------------------------------------------------------------
240 * Start addresses for the final memory configuration
241 * (Set up by the startup code)
242 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
243 */
244#define CONFIG_SYS_SDRAM_BASE 0x40000000
245#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
246
247#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
248#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
249#define CONFIG_SYS_DRAM_TEST
250
251#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
252#define CONFIG_SERIAL_BOOT
253#endif
254
255#if defined(CONFIG_SERIAL_BOOT)
Masahiro Yamada61a43922015-12-11 12:22:25 +0900256#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
Alison Wang186fc4d2012-10-18 19:25:52 +0000257#else
258#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
259#endif
260
261#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
262/* Reserve 256 kB for Monitor */
263#define CONFIG_SYS_MONITOR_LEN (256 << 10)
264/* Reserve 256 kB for malloc() */
265#define CONFIG_SYS_MALLOC_LEN (256 << 10)
266
267/*
268 * For booting Linux, the board info and command line data
269 * have to be in the first 8 MB of memory, since this is
270 * the maximum mapped by the Linux kernel during initialization ??
271 */
272/* Initial Memory map for Linux */
273#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
274 (CONFIG_SYS_SDRAM_SIZE << 20))
275
276/* Configuration for environment
277 * Environment is embedded in u-boot in the second sector of the flash
278 */
279#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
280#define CONFIG_SYS_NO_FLASH
281#define CONFIG_ENV_IS_IN_MRAM 1
282#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
283#define CONFIG_ENV_SIZE 0x1000
284#endif
285
286#if defined(CONFIG_CF_SBF)
287#define CONFIG_SYS_NO_FLASH
288#define CONFIG_ENV_IS_IN_SPI_FLASH 1
289#define CONFIG_ENV_SPI_CS 1
290#define CONFIG_ENV_OFFSET 0x40000
291#define CONFIG_ENV_SIZE 0x2000
292#define CONFIG_ENV_SECT_SIZE 0x10000
293#endif
294#if defined(CONFIG_SYS_NAND_BOOT)
295#define CONFIG_SYS_NO_FLASH
Jason Jinb765fce2012-10-25 15:27:37 +0800296#define CONFIG_ENV_IS_NOWHERE
Alison Wang186fc4d2012-10-18 19:25:52 +0000297#define CONFIG_ENV_OFFSET 0x80000
298#define CONFIG_ENV_SIZE 0x20000
299#define CONFIG_ENV_SECT_SIZE 0x20000
300#endif
301#undef CONFIG_ENV_OVERWRITE
302
303/* FLASH organization */
304#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
305
306#undef CONFIG_SYS_FLASH_CFI
307#ifdef CONFIG_SYS_FLASH_CFI
308
309#define CONFIG_FLASH_CFI_DRIVER 1
310/* Max size that the board might have */
311#define CONFIG_SYS_FLASH_SIZE 0x1000000
312#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
313/* max number of memory banks */
314#define CONFIG_SYS_MAX_FLASH_BANKS 1
315/* max number of sectors on one chip */
316#define CONFIG_SYS_MAX_FLASH_SECT 270
317/* "Real" (hardware) sectors protection */
318#define CONFIG_SYS_FLASH_PROTECTION
319#define CONFIG_SYS_FLASH_CHECKSUM
320#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
321#else
322/* max number of sectors on one chip */
323#define CONFIG_SYS_MAX_FLASH_SECT 270
324/* max number of sectors on one chip */
325#define CONFIG_SYS_MAX_FLASH_BANKS 0
326#endif
327
328/*
329 * This is setting for JFFS2 support in u-boot.
330 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
331 */
332#ifdef CONFIG_CMD_JFFS2
333#define CONFIG_JFFS2_DEV "nand0"
334#define CONFIG_JFFS2_PART_OFFSET (0x800000)
335#define CONFIG_CMD_MTDPARTS
336#define CONFIG_MTD_DEVICE
337#define MTDIDS_DEFAULT "nand0=m54418twr.nand"
338
339#define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
340 "7m(kernel)," \
341 "-(rootfs)"
342
343#endif
344
345#ifdef CONFIG_CMD_UBI
346#define CONFIG_CMD_MTDPARTS
347#define CONFIG_MTD_DEVICE /* needed for mtdparts command */
348#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
349#define CONFIG_RBTREE
350#define MTDIDS_DEFAULT "nand0=NAND"
351#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
352 "-(ubi)"
353#endif
354/* Cache Configuration */
355#define CONFIG_SYS_CACHELINE_SIZE 16
356#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
357 CONFIG_SYS_INIT_RAM_SIZE - 8)
358#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
359 CONFIG_SYS_INIT_RAM_SIZE - 4)
360#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
361#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
362#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
363 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
364 CF_ACR_EN | CF_ACR_SM_ALL)
365#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
366 CF_CACR_ICINVA | CF_CACR_EUSP)
367#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
368 CF_CACR_DEC | CF_CACR_DDCM_P | \
369 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
370
371#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
372 CONFIG_SYS_INIT_RAM_SIZE - 12)
373
374/*-----------------------------------------------------------------------
375 * Memory bank definitions
376 */
377/*
378 * CS0 - NOR Flash 16MB
379 * CS1 - Available
380 * CS2 - Available
381 * CS3 - Available
382 * CS4 - Available
383 * CS5 - Available
384 */
385
386 /* Flash */
387#define CONFIG_SYS_CS0_BASE 0x00000000
388#define CONFIG_SYS_CS0_MASK 0x000F0101
389#define CONFIG_SYS_CS0_CTRL 0x00001D60
390
391#endif /* _M54418TWR_H */