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Wu, Josh9e336902013-04-16 23:42:44 +00001/*
2 * (C) Copyright 2013 Atmel Corporation.
3 * Josh Wu <josh.wu@atmel.com>
4 *
5 * Configuation settings for the AT91SAM9N12-EK boards.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Wu, Josh9e336902013-04-16 23:42:44 +00008 */
9
10#ifndef __AT91SAM9N12_CONFIG_H_
11#define __AT91SAM9N12_CONFIG_H_
12
13/*
14 * SoC must be defined first, before hardware.h is included.
15 * In this case SoC is defined in boards.cfg.
16 */
17#include <asm/hardware.h>
18
19#define CONFIG_SYS_TEXT_BASE 0x26f00000
20
Wu, Josh9e336902013-04-16 23:42:44 +000021/* ARM asynchronous clock */
22#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
23#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
Wu, Josh9e336902013-04-16 23:42:44 +000024
25/* Misc CPU related */
26#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
27#define CONFIG_SETUP_MEMORY_TAGS
28#define CONFIG_INITRD_TAG
29#define CONFIG_SKIP_LOWLEVEL_INIT
Wu, Josh9e336902013-04-16 23:42:44 +000030
Wu, Josh9e336902013-04-16 23:42:44 +000031/* general purpose I/O */
32#define CONFIG_AT91_GPIO
33
34/* serial console */
35#define CONFIG_ATMEL_USART
36#define CONFIG_USART_BASE ATMEL_BASE_DBGU
37#define CONFIG_USART_ID ATMEL_ID_SYS
38#define CONFIG_BAUDRATE 115200
39
40/* LCD */
Wu, Josh9e336902013-04-16 23:42:44 +000041#define LCD_BPP LCD_COLOR16
42#define LCD_OUTPUT_BPP 24
43#define CONFIG_LCD_LOGO
44#define CONFIG_LCD_INFO
45#define CONFIG_LCD_INFO_BELOW_LOGO
46#define CONFIG_SYS_WHITE_ON_BLACK
47#define CONFIG_ATMEL_HLCD
48#define CONFIG_ATMEL_LCD_RGB565
Wu, Josh9e336902013-04-16 23:42:44 +000049
Wu, Josh9e336902013-04-16 23:42:44 +000050
51/*
52 * BOOTP options
53 */
54#define CONFIG_BOOTP_BOOTFILESIZE
55#define CONFIG_BOOTP_BOOTPATH
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58
59/* NOR flash - no real flash on this board */
60#define CONFIG_SYS_NO_FLASH
61
62/*
63 * Command line configuration.
64 */
Wu, Josh9e336902013-04-16 23:42:44 +000065#define CONFIG_CMD_NAND
Wu, Josh9e336902013-04-16 23:42:44 +000066
67#define CONFIG_NR_DRAM_BANKS 1
68#define CONFIG_SYS_SDRAM_BASE 0x20000000
69#define CONFIG_SYS_SDRAM_SIZE 0x08000000
70
71/*
72 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
73 * leaving the correct space for initial global data structure above
74 * that address while providing maximum stack area below.
75 */
76# define CONFIG_SYS_INIT_SP_ADDR \
77 (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
78
79/* DataFlash */
80#ifdef CONFIG_CMD_SF
81#define CONFIG_ATMEL_SPI
Wu, Josh9e336902013-04-16 23:42:44 +000082#define CONFIG_SF_DEFAULT_SPEED 30000000
83#define CONFIG_ENV_SPI_MODE SPI_MODE_3
84#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
85#endif
86
87/* NAND flash */
88#ifdef CONFIG_CMD_NAND
89#define CONFIG_NAND_ATMEL
90#define CONFIG_SYS_MAX_NAND_DEVICE 1
91#define CONFIG_SYS_NAND_BASE 0x40000000
92#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
93#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +010094#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
95#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
Wu, Josh9e336902013-04-16 23:42:44 +000096
97/* PMECC & PMERRLOC */
98#define CONFIG_ATMEL_NAND_HWECC
99#define CONFIG_ATMEL_NAND_HW_PMECC
100#define CONFIG_PMECC_CAP 2
101#define CONFIG_PMECC_SECTOR_SIZE 512
102#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000
Bo Shence76f0a2013-06-26 10:48:53 +0800103
104#define CONFIG_CMD_NAND_TRIMFFS
105
Wu, Josh9e336902013-04-16 23:42:44 +0000106#endif
107
108#define CONFIG_MTD_PARTITIONS
109#define CONFIG_MTD_DEVICE
110#define CONFIG_CMD_MTDPARTS
111#define MTDIDS_DEFAULT "nand0=atmel_nand"
112#define MTDPARTS_DEFAULT \
113 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
114 "256k(env),256k(env_redundant),256k(spare)," \
115 "512k(dtb),6M(kernel)ro,-(rootfs)"
116
117#define CONFIG_EXTRA_ENV_SETTINGS \
118 "console=console=ttyS0,115200\0" \
119 "mtdparts="MTDPARTS_DEFAULT"\0" \
120 "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
121 "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
122
123/* MMC */
124#ifdef CONFIG_CMD_MMC
Wu, Josh9e336902013-04-16 23:42:44 +0000125#define CONFIG_GENERIC_MMC
126#define CONFIG_GENERIC_ATMEL_MCI
127#endif
128
129/* FAT */
130#ifdef CONFIG_CMD_FAT
131#define CONFIG_DOS_PARTITION
132#endif
133
Bo Shen16276222013-04-24 10:46:18 +0800134/* Ethernet */
135#define CONFIG_KS8851_MLL
136#define CONFIG_KS8851_MLL_BASEADDR 0x30000000 /* use NCS2 */
137
Wu, Josh9e336902013-04-16 23:42:44 +0000138#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
139
140#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
141#define CONFIG_SYS_MEMTEST_END 0x26e00000
142
Bo Shend9bef0a2013-10-21 16:13:59 +0800143/* USB host */
144#ifdef CONFIG_CMD_USB
145#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800146#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Bo Shend9bef0a2013-10-21 16:13:59 +0800147#define CONFIG_USB_OHCI_NEW
148#define CONFIG_SYS_USB_OHCI_CPU_INIT
149#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
150#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12"
151#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
Bo Shend9bef0a2013-10-21 16:13:59 +0800152#endif
153
Wu, Josh9e336902013-04-16 23:42:44 +0000154#ifdef CONFIG_SYS_USE_SPIFLASH
155
156/* bootstrap + u-boot + env + linux in dataflash on CS0 */
157#define CONFIG_ENV_IS_IN_SPI_FLASH
158#define CONFIG_ENV_OFFSET 0x5000
159#define CONFIG_ENV_SIZE 0x3000
160#define CONFIG_ENV_SECT_SIZE 0x1000
161#define CONFIG_BOOTCOMMAND \
162 "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \
163 "sf probe 0; sf read 0x22000000 0x100000 0x300000; " \
164 "bootm 0x22000000"
165
166#elif defined(CONFIG_SYS_USE_NANDFLASH)
167
168/* bootstrap + u-boot + env + linux in nandflash */
169#define CONFIG_ENV_IS_IN_NAND
170#define CONFIG_ENV_OFFSET 0xc0000
171#define CONFIG_ENV_OFFSET_REDUND 0x100000
172#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
173#define CONFIG_BOOTCOMMAND \
174 "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \
175 "nand read 0x21000000 0x180000 0x080000;" \
176 "nand read 0x22000000 0x200000 0x400000;" \
177 "bootm 0x22000000 - 0x21000000"
178
179#else /* CONFIG_SYS_USE_MMC */
180
181/* bootstrap + u-boot + env + linux in mmc */
Wu, Josh23ac62d2015-03-24 17:07:22 +0800182
183#ifdef CONFIG_ENV_IS_IN_MMC
184/* Use raw reserved sectors to save environment */
Wu, Josh9e336902013-04-16 23:42:44 +0000185#define CONFIG_ENV_OFFSET 0x2000
186#define CONFIG_ENV_SIZE 0x1000
187#define CONFIG_SYS_MMC_ENV_DEV 0
Wu, Josh23ac62d2015-03-24 17:07:22 +0800188#else
189/* Use file in FAT file to save environment */
190#define CONFIG_ENV_IS_IN_FAT
191#define CONFIG_FAT_WRITE
192#define FAT_ENV_INTERFACE "mmc"
193#define FAT_ENV_FILE "uboot.env"
194#define FAT_ENV_DEVICE_AND_PART "0"
195#define CONFIG_ENV_SIZE 0x4000
196#endif
197
Wu, Josh9e336902013-04-16 23:42:44 +0000198#define CONFIG_BOOTCOMMAND \
199 "setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};" \
200 "fatload mmc 0:1 0x21000000 dtb;" \
201 "fatload mmc 0:1 0x22000000 uImage;" \
202 "bootm 0x22000000 - 0x21000000"
203
204#endif
205
Wu, Josh9e336902013-04-16 23:42:44 +0000206#define CONFIG_SYS_CBSIZE 256
207#define CONFIG_SYS_MAXARGS 16
Wu, Josh9e336902013-04-16 23:42:44 +0000208#define CONFIG_SYS_LONGHELP
209#define CONFIG_CMDLINE_EDITING
210#define CONFIG_AUTO_COMPLETE
Wu, Josh9e336902013-04-16 23:42:44 +0000211
212/*
213 * Size of malloc() pool
214 */
215#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
Bo Shenff255e82015-03-27 14:23:36 +0800216
217/* SPL */
218#define CONFIG_SPL_FRAMEWORK
219#define CONFIG_SPL_TEXT_BASE 0x300000
220#define CONFIG_SPL_MAX_SIZE 0x6000
221#define CONFIG_SPL_STACK 0x308000
222
223#define CONFIG_SPL_BSS_START_ADDR 0x20000000
224#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
225#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
226#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
227
Bo Shenff255e82015-03-27 14:23:36 +0800228#define CONFIG_SPL_BOARD_INIT
229#define CONFIG_SYS_MONITOR_LEN (512 << 10)
230
231#define CONFIG_SYS_MASTER_CLOCK 132096000
232#define CONFIG_SYS_AT91_PLLA 0x20953f03
233#define CONFIG_SYS_MCKR 0x1301
234#define CONFIG_SYS_MCKR_CSS 0x1302
235
Bo Shenff255e82015-03-27 14:23:36 +0800236#ifdef CONFIG_SYS_USE_MMC
237#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
Bo Shenff255e82015-03-27 14:23:36 +0800238#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
239#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shenff255e82015-03-27 14:23:36 +0800240
241#elif CONFIG_SYS_USE_NANDFLASH
Bo Shenff255e82015-03-27 14:23:36 +0800242#define CONFIG_SPL_NAND_DRIVERS
243#define CONFIG_SPL_NAND_BASE
244#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
245#define CONFIG_SYS_NAND_5_ADDR_CYCLE
246#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
247#define CONFIG_SYS_NAND_PAGE_COUNT 64
248#define CONFIG_SYS_NAND_OOBSIZE 64
249#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
250#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
251#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
252
253#elif CONFIG_SYS_USE_SPIFLASH
Bo Shenff255e82015-03-27 14:23:36 +0800254#define CONFIG_SPL_SPI_LOAD
255#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
256
257#endif
Wu, Josh9e336902013-04-16 23:42:44 +0000258
259#endif