blob: 658e359b20fa99f206843ed3bbba24e9298ac42f [file] [log] [blame]
Stefan Roese04386f62015-10-02 08:20:35 +02001/*
2 * (C) Copyright 2007-2013
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/*
9 * lwmon5.h - configuration for lwmon5 board
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
Stefan Roese04386f62015-10-02 08:20:35 +020015 * High Level Configuration Options
16 */
17#define CONFIG_LWMON5 1 /* Board is lwmon5 */
18#define CONFIG_440EPX 1 /* Specific PPC440EPx */
19#define CONFIG_440 1 /* ... PPC440 family */
20
Stefan Roese04386f62015-10-02 08:20:35 +020021#define CONFIG_SYS_TEXT_BASE 0xFFF80000
22#define CONFIG_HOSTNAME lwmon5
Stefan Roese04386f62015-10-02 08:20:35 +020023
24#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
25
26#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
27
Stefan Roese04386f62015-10-02 08:20:35 +020028#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
29#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
30#define CONFIG_MISC_INIT_R /* Call misc_init_r */
31#define CONFIG_BOARD_RESET /* Call board_reset */
32
33/*
34 * Base addresses -- Note these are effective addresses where the
35 * actual resources get mapped (not physical addresses)
36 */
37#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
38#define CONFIG_SYS_MONITOR_LEN 0x80000
39#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
40
41#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
42#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
43#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
44#define CONFIG_SYS_LIME_BASE_0 0xc0000000
45#define CONFIG_SYS_LIME_BASE_1 0xc1000000
46#define CONFIG_SYS_LIME_BASE_2 0xc2000000
47#define CONFIG_SYS_LIME_BASE_3 0xc3000000
48#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
49#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
50#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
51#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
52#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
53#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
54#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
55#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
56
Stefan Roese04386f62015-10-02 08:20:35 +020057#define CONFIG_SYS_USB2D0_BASE 0xe0000100
58#define CONFIG_SYS_USB_DEVICE 0xe0000000
59#define CONFIG_SYS_USB_HOST 0xe0000400
Stefan Roese04386f62015-10-02 08:20:35 +020060
61/*
62 * Initial RAM & stack pointer
63 *
64 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
65 * the POST_WORD from OCM to a 440EPx register that preserves it's
66 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
67 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
68 */
Stefan Roese04386f62015-10-02 08:20:35 +020069#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
70#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
71#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
72#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
73 GENERATED_GBL_DATA_SIZE)
74#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roeseb6b5e392015-10-02 08:20:37 +020075
Stefan Roese04386f62015-10-02 08:20:35 +020076/* unused GPT0 COMP reg */
77#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
78#define CONFIG_SYS_OCM_SIZE (16 << 10)
79/* 440EPx errata CHIP 11: don't use last 4kbytes */
80#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
81
82/* Additional registers for watchdog timer post test */
83#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
84#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
85#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
86#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
87#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
88#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
89#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
90#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
91#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
92#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
93
94/*
95 * Serial Port
96 */
97#define CONFIG_CONS_INDEX 2 /* Use UART1 */
Stefan Roese04386f62015-10-02 08:20:35 +020098#define CONFIG_SYS_NS16550_SERIAL
99#define CONFIG_SYS_NS16550_REG_SIZE 1
100#define CONFIG_SYS_NS16550_CLK get_serial_clock()
101#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
102#define CONFIG_BAUDRATE 115200
103
104#define CONFIG_SYS_BAUDRATE_TABLE \
105 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
106
107/*
108 * Environment
109 */
110#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
111
112/*
113 * FLASH related
114 */
115#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
116#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
117
118#define CONFIG_SYS_FLASH0 0xFC000000
119#define CONFIG_SYS_FLASH1 0xF8000000
120#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
121
122#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
123#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
124
125#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
126#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
127
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
129#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
130
131#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
132#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
133
134#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
135#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
136#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
137
138/* Address and size of Redundant Environment Sector */
139#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
140#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
141
142/*
143 * DDR SDRAM
144 */
145#define CONFIG_SYS_MBYTES_SDRAM 256
146#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
147#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Stefan Roese04386f62015-10-02 08:20:35 +0200148#define CONFIG_DDR_ECC /* enable ECC */
Stefan Roese04386f62015-10-02 08:20:35 +0200149
Stefan Roese04386f62015-10-02 08:20:35 +0200150/* POST support */
151#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
152 CONFIG_SYS_POST_CPU | \
153 CONFIG_SYS_POST_ECC | \
154 CONFIG_SYS_POST_ETHER | \
155 CONFIG_SYS_POST_FPU | \
156 CONFIG_SYS_POST_I2C | \
157 CONFIG_SYS_POST_MEMORY | \
158 CONFIG_SYS_POST_OCM | \
159 CONFIG_SYS_POST_RTC | \
160 CONFIG_SYS_POST_SPR | \
161 CONFIG_SYS_POST_UART | \
162 CONFIG_SYS_POST_SYSMON | \
163 CONFIG_SYS_POST_WATCHDOG | \
164 CONFIG_SYS_POST_DSP | \
165 CONFIG_SYS_POST_BSPEC1 | \
166 CONFIG_SYS_POST_BSPEC2 | \
167 CONFIG_SYS_POST_BSPEC3 | \
168 CONFIG_SYS_POST_BSPEC4 | \
169 CONFIG_SYS_POST_BSPEC5)
170
171/* Define here the base-addresses of the UARTs to test in POST */
172#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
173 CONFIG_SYS_NS16550_COM2 }
174
175#define CONFIG_POST_UART { \
176 "UART test", \
177 "uart", \
178 "This test verifies the UART operation.", \
179 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
180 &uart_post_test, \
181 NULL, \
182 NULL, \
183 CONFIG_SYS_POST_UART \
184 }
185
186#define CONFIG_POST_WATCHDOG { \
187 "Watchdog timer test", \
188 "watchdog", \
189 "This test checks the watchdog timer.", \
190 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
191 &lwmon5_watchdog_post_test, \
192 NULL, \
193 NULL, \
194 CONFIG_SYS_POST_WATCHDOG \
195 }
196
197#define CONFIG_POST_BSPEC1 { \
198 "dsPIC init test", \
199 "dspic_init", \
200 "This test returns result of dsPIC READY test run earlier.", \
201 POST_RAM | POST_ALWAYS, \
202 &dspic_init_post_test, \
203 NULL, \
204 NULL, \
205 CONFIG_SYS_POST_BSPEC1 \
206 }
207
208#define CONFIG_POST_BSPEC2 { \
209 "dsPIC test", \
210 "dspic", \
211 "This test gets result of dsPIC POST and dsPIC version.", \
212 POST_RAM | POST_ALWAYS, \
213 &dspic_post_test, \
214 NULL, \
215 NULL, \
216 CONFIG_SYS_POST_BSPEC2 \
217 }
218
219#define CONFIG_POST_BSPEC3 { \
220 "FPGA test", \
221 "fpga", \
222 "This test checks FPGA registers and memory.", \
223 POST_RAM | POST_ALWAYS | POST_MANUAL, \
224 &fpga_post_test, \
225 NULL, \
226 NULL, \
227 CONFIG_SYS_POST_BSPEC3 \
228 }
229
230#define CONFIG_POST_BSPEC4 { \
231 "GDC test", \
232 "gdc", \
233 "This test checks GDC registers and memory.", \
234 POST_RAM | POST_ALWAYS | POST_MANUAL,\
235 &gdc_post_test, \
236 NULL, \
237 NULL, \
238 CONFIG_SYS_POST_BSPEC4 \
239 }
240
241#define CONFIG_POST_BSPEC5 { \
242 "SYSMON1 test", \
243 "sysmon1", \
244 "This test checks GPIO_62_EPX pin indicating power failure.", \
245 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
246 &sysmon1_post_test, \
247 NULL, \
248 NULL, \
249 CONFIG_SYS_POST_BSPEC5 \
250 }
251
252#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
253#define CONFIG_LOGBUFFER
254/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
255#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
256#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
Stefan Roese04386f62015-10-02 08:20:35 +0200257
258/*
259 * I2C
260 */
261#define CONFIG_SYS_I2C
262#define CONFIG_SYS_I2C_PPC4XX
263#define CONFIG_SYS_I2C_PPC4XX_CH0
264#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
265#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
266
267#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
268#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
269#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
270#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
271#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
272#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
273#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
274
275#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
276#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
277 /* 64 byte page write mode using*/
278 /* last 6 bits of the address */
279#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
280#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
281
282#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
283#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
284#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
285#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
286
287#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
288 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
289 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
290 CONFIG_SYS_I2C_DSPIC_ADDR, \
291 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
292 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
293 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
294
Stefan Roese04386f62015-10-02 08:20:35 +0200295/* Update size in "reg" property of NOR FLASH device tree nodes */
296#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
297
Stefan Roese04386f62015-10-02 08:20:35 +0200298#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
299
300#define CONFIG_PREBOOT "setenv bootdelay 15"
301
302#undef CONFIG_BOOTARGS
303
304#define CONFIG_EXTRA_ENV_SETTINGS \
305 "hostname=lwmon5\0" \
306 "netdev=eth0\0" \
307 "unlock=yes\0" \
308 "logversion=2\0" \
309 "nfsargs=setenv bootargs root=/dev/nfs rw " \
310 "nfsroot=${serverip}:${rootpath}\0" \
311 "ramargs=setenv bootargs root=/dev/ram rw\0" \
312 "addip=setenv bootargs ${bootargs} " \
313 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
314 ":${hostname}:${netdev}:off panic=1\0" \
315 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
316 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
317 "flash_nfs=run nfsargs addip addtty addmisc;" \
318 "bootm ${kernel_addr}\0" \
319 "flash_self=run ramargs addip addtty addmisc;" \
320 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
321 "net_nfs=tftp 200000 ${bootfile};" \
322 "run nfsargs addip addtty addmisc;bootm\0" \
323 "rootpath=/opt/eldk/ppc_4xxFP\0" \
324 "bootfile=/tftpboot/lwmon5/uImage\0" \
325 "kernel_addr=FC000000\0" \
326 "ramdisk_addr=FC180000\0" \
327 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
328 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
329 "cp.b 200000 FFF80000 80000\0" \
330 "upd=run load update\0" \
331 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
332 "autoscr 200000\0" \
333 ""
334#define CONFIG_BOOTCOMMAND "run flash_self"
335
Stefan Roese04386f62015-10-02 08:20:35 +0200336
337#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
338#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
339
340#define CONFIG_PPC4xx_EMAC
341#define CONFIG_IBM_EMAC4_V4 1
342#define CONFIG_MII 1 /* MII PHY management */
343#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
344
345#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
346#define CONFIG_PHY_RESET_DELAY 300
347
348#define CONFIG_HAS_ETH0
349#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
350
351#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
352#define CONFIG_PHY1_ADDR 1
353
354/* Video console */
Stefan Roese04386f62015-10-02 08:20:35 +0200355#define CONFIG_VIDEO_MB862xx
356#define CONFIG_VIDEO_MB862xx_ACCEL
Stefan Roese04386f62015-10-02 08:20:35 +0200357#define CONFIG_VIDEO_LOGO
Stefan Roese04386f62015-10-02 08:20:35 +0200358#define VIDEO_FB_16BPP_PIXEL_SWAP
359#define VIDEO_FB_16BPP_WORD_SWAP
360
Stefan Roese04386f62015-10-02 08:20:35 +0200361#define CONFIG_SPLASH_SCREEN
362
Stefan Roese04386f62015-10-02 08:20:35 +0200363/*
364 * USB/EHCI
365 */
366#define CONFIG_USB_EHCI /* Enable EHCI USB support */
367#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
368#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
369#define CONFIG_EHCI_MMIO_BIG_ENDIAN
370#define CONFIG_EHCI_DESC_BIG_ENDIAN
371#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
Stefan Roese04386f62015-10-02 08:20:35 +0200372
373/* Partitions */
374#define CONFIG_MAC_PARTITION
375#define CONFIG_DOS_PARTITION
376#define CONFIG_ISO_PARTITION
Stefan Roese04386f62015-10-02 08:20:35 +0200377
378/*
379 * BOOTP options
380 */
381#define CONFIG_BOOTP_BOOTFILESIZE
382#define CONFIG_BOOTP_BOOTPATH
383#define CONFIG_BOOTP_GATEWAY
384#define CONFIG_BOOTP_HOSTNAME
385
386/*
387 * Command line configuration.
388 */
Stefan Roese04386f62015-10-02 08:20:35 +0200389#define CONFIG_CMD_DATE
Stefan Roese04386f62015-10-02 08:20:35 +0200390#define CONFIG_CMD_DIAG
391#define CONFIG_CMD_EEPROM
Stefan Roese04386f62015-10-02 08:20:35 +0200392#define CONFIG_CMD_IRQ
Stefan Roese04386f62015-10-02 08:20:35 +0200393#define CONFIG_CMD_REGINFO
394#define CONFIG_CMD_SDRAM
395
396#ifdef CONFIG_VIDEO
397#define CONFIG_CMD_BMP
398#endif
399
Stefan Roese04386f62015-10-02 08:20:35 +0200400#ifdef CONFIG_440EPX
Stefan Roese04386f62015-10-02 08:20:35 +0200401#endif
Stefan Roese04386f62015-10-02 08:20:35 +0200402
403/*
404 * Miscellaneous configurable options
405 */
406#define CONFIG_SUPPORT_VFAT
407
408#define CONFIG_SYS_LONGHELP /* undef to save memory */
409
Stefan Roese04386f62015-10-02 08:20:35 +0200410#if defined(CONFIG_CMD_KGDB)
411#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
412#else
413#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
414#endif
415#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
416#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
417#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
418
419#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
420#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
421
422#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
423#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
424
425#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Stefan Roese04386f62015-10-02 08:20:35 +0200426#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese04386f62015-10-02 08:20:35 +0200427
Stefan Roese04386f62015-10-02 08:20:35 +0200428#ifndef DEBUG
429#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
430#endif
431#define CONFIG_WD_PERIOD 40000 /* in usec */
432#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
Stefan Roese04386f62015-10-02 08:20:35 +0200433
434/*
435 * For booting Linux, the board info and command line data
436 * have to be in the first 16 MB of memory, since this is
437 * the maximum mapped by the 40x Linux kernel during initialization.
438 */
439#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
440#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
441
442/*
443 * External Bus Controller (EBC) Setup
444 */
445#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
446
447/* Memory Bank 0 (NOR-FLASH) initialization */
448#define CONFIG_SYS_EBC_PB0AP 0x03000280
449#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
450
451/* Memory Bank 1 (Lime) initialization */
452#define CONFIG_SYS_EBC_PB1AP 0x01004380
453#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
454
455/* Memory Bank 2 (FPGA) initialization */
456#define CONFIG_SYS_EBC_PB2AP 0x01004400
457#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
458
459/* Memory Bank 3 (FPGA2) initialization */
460#define CONFIG_SYS_EBC_PB3AP 0x01004400
461#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
462
463#define CONFIG_SYS_EBC_CFG 0xb8400000
464
465/*
466 * Graphics (Fujitsu Lime)
467 */
468/* SDRAM Clock frequency adjustment register */
469#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
470#if 1 /* 133MHz is not tested enough, use 100MHz for now */
471/* Lime Clock frequency is to set 100MHz */
472#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
473#else
474/* Lime Clock frequency for 133MHz */
475#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
476#endif
477
478/* SDRAM Parameter register */
479#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
480/*
481 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
482 * and pixel flare on display when 133MHz was configured. According to
483 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
484 * Grade
485 */
486#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
487#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
488#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
489#else
490#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
491#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
492#endif
493
494/*
495 * GPIO Setup
496 */
497#define CONFIG_SYS_GPIO_PHY1_RST 12
498#define CONFIG_SYS_GPIO_FLASH_WP 14
499#define CONFIG_SYS_GPIO_PHY0_RST 22
500#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
501#define CONFIG_SYS_GPIO_DSPIC_READY 51
502#define CONFIG_SYS_GPIO_CAN_ENABLE 53
503#define CONFIG_SYS_GPIO_LSB_ENABLE 54
504#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
505#define CONFIG_SYS_GPIO_HIGHSIDE 56
506#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
507#define CONFIG_SYS_GPIO_BOARD_RESET 58
508#define CONFIG_SYS_GPIO_LIME_S 59
509#define CONFIG_SYS_GPIO_LIME_RST 60
510#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
511#define CONFIG_SYS_GPIO_WATCHDOG 63
512
Stefan Roese04386f62015-10-02 08:20:35 +0200513#define GPIO49_VAL 1
Stefan Roese04386f62015-10-02 08:20:35 +0200514
515/*
516 * PPC440 GPIO Configuration
517 */
518#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
519{ \
520/* GPIO Core 0 */ \
521{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
522{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
523{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
524{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
525{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
526{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
527{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
528{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
529{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
530{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
531{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
532{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
533{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
534{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
535{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
536{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
537{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
538{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
539{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
540{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
541{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
542{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
543{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
544{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
545{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
546{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
547{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
548{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
549{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
550{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
551{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
552{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
553}, \
554{ \
555/* GPIO Core 1 */ \
556{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
557{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
558{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
559{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
560{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
561{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
562{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
563{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
564{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
565{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
566{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
567{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
568{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
569{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
570{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
571{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
572{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
573{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
574{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
575{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
576{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
577{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
578{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
579{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
580{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
581{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
582{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
583{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
584{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
585{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
586{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
587{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
588} \
589}
590
591#if defined(CONFIG_CMD_KGDB)
592#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
593#endif
594
Stefan Roese04386f62015-10-02 08:20:35 +0200595#endif /* __CONFIG_H */