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Stefan Roesefeaedfc2005-11-15 10:35:59 +01001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * CMS700.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_VOM405 1 /* ...on a VOM405 board */
39
40#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
42
43#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
49#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT /* enable preboot variable */
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roesefeaedfc2005-11-15 10:35:59 +010054
Ben Warren96e21f82008-10-27 23:50:15 -070055#define CONFIG_PPC4xx_EMAC
Stefan Roesefeaedfc2005-11-15 10:35:59 +010056#define CONFIG_NET_MULTI 1
57#undef CONFIG_HAS_ETH1
58
59#define CONFIG_MII 1 /* MII PHY management */
60#define CONFIG_PHY_ADDR 0 /* PHY address */
61#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
62#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
63
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050064/*
65 * BOOTP options
66 */
67#define CONFIG_BOOTP_SUBNETMASK
68#define CONFIG_BOOTP_GATEWAY
69#define CONFIG_BOOTP_HOSTNAME
70#define CONFIG_BOOTP_BOOTPATH
71#define CONFIG_BOOTP_DNS
72#define CONFIG_BOOTP_DNS2
73#define CONFIG_BOOTP_SEND_HOSTNAME
Stefan Roesefeaedfc2005-11-15 10:35:59 +010074
Stefan Roesefeaedfc2005-11-15 10:35:59 +010075
Jon Loeliger49cf7e82007-07-05 19:52:35 -050076/*
77 * Command line configuration.
78 */
79#include <config_cmd_default.h>
Stefan Roesefeaedfc2005-11-15 10:35:59 +010080
Jon Loeliger49cf7e82007-07-05 19:52:35 -050081#define CONFIG_CMD_DHCP
82#define CONFIG_CMD_BSP
Jon Loeliger49cf7e82007-07-05 19:52:35 -050083#define CONFIG_CMD_ELF
84#define CONFIG_CMD_NAND
85#define CONFIG_CMD_I2C
86#define CONFIG_CMD_DATE
87#define CONFIG_CMD_MII
88#define CONFIG_CMD_PING
89#define CONFIG_CMD_EEPROM
90
Stefan Roesefeaedfc2005-11-15 10:35:59 +010091
Stefan Roesefeaedfc2005-11-15 10:35:59 +010092#undef CONFIG_WATCHDOG /* watchdog disabled */
93
94#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
95
96#undef CONFIG_PRAM /* no "protected RAM" */
97
98/*
99 * Miscellaneous configurable options
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_LONGHELP /* undef to save memory */
102#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
105#ifdef CONFIG_SYS_HUSH_PARSER
106#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100107#endif
108
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500109#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100111#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100113#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
123#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100124
Stefan Roese550650d2010-09-20 16:05:31 +0200125#define CONFIG_CONS_INDEX 2 /* Use UART1 */
126#define CONFIG_SYS_NS16550
127#define CONFIG_SYS_NS16550_SERIAL
128#define CONFIG_SYS_NS16550_REG_SIZE 1
129#define CONFIG_SYS_NS16550_CLK get_serial_clock()
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100133
134/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100136 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
137 57600, 115200, 230400, 460800, 921600 }
138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
140#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100143
144#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
145
146#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100149
150/*-----------------------------------------------------------------------
151 * RTC stuff
152 *-----------------------------------------------------------------------
153 */
154#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100156
157/*-----------------------------------------------------------------------
158 * NAND-FLASH stuff
159 *-----------------------------------------------------------------------
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200163#define NAND_BIG_DELAY_US 25
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
166#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
167#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
168#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
171#define CONFIG_SYS_NAND_QUIET 1
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100172
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100173/*
174 * For booting Linux, the board info and command line data
175 * have to be in the first 8 MB of memory, since this is
176 * the maximum mapped by the Linux kernel during initialization.
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100179/*-----------------------------------------------------------------------
180 * FLASH organization
181 */
182#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
185#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
188#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
191#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
192#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100193/*
194 * The following defines are added for buggy IOP480 byte interface.
195 * All other boards should use the standard values (CPCI405 etc.)
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
198#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
199#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100202
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100203/*-----------------------------------------------------------------------
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchs7cc635f2009-04-29 09:50:57 +0200209#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
210#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
211#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
212#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
215# define CONFIG_SYS_RAMBOOT 1
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100216#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217# undef CONFIG_SYS_RAMBOOT
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100218#endif
219
220/*-----------------------------------------------------------------------
221 * Environment Variable setup
222 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200223#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200224#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
225#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100226 /* total size of a CAT24WC16 is 2048 bytes */
227
228/*-----------------------------------------------------------------------
229 * I2C EEPROM (CAT24WC16) for environment
230 */
231#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200232#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
234#define CONFIG_SYS_I2C_SLAVE 0x7F
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
237#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100238/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
240#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100241 /* 16 byte page write mode using*/
242 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_EEPROM_WREN 1
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100246
247/*-----------------------------------------------------------------------
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100248 * External Bus Controller (EBC) Setup
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PLD_BASE 0xf0000000
251#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100252
253/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_EBC_PB0AP 0x92015480
255#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100256
257/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_EBC_PB1AP 0x92015480
259#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100260
261/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
263#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100264
265/*-----------------------------------------------------------------------
266 * FPGA stuff
267 */
Matthias Fuchs7cc635f2009-04-29 09:50:57 +0200268#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100269
270/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
272#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
273#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
274#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
275#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100276
277/*-----------------------------------------------------------------------
278 * Definitions for initial stack pointer and data area (in data cache)
279 */
280/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_TEMP_STACK_OCM 1
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100282
283/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
285#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
286#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
287#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
290#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
291#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100292
293/*-----------------------------------------------------------------------
294 * Definitions for GPIO setup (PPC405EP specific)
295 *
296 * GPIO0[0] - External Bus Controller BLAST output
297 * GPIO0[1-9] - Instruction trace outputs -> GPIO
298 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
299 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
300 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
301 * GPIO0[24-27] - UART0 control signal inputs/outputs
302 * GPIO0[28-29] - UART1 data signal input/output
303 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
304 */
305/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
306/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
307/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
308/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200309#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */
310#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
311#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
312#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
313#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
314#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
318#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100319
320/*
321 * Internal Definitions
322 *
323 * Boot Flags
324 */
325#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
326#define BOOTFLAG_WARM 0x02 /* Software reboot */
327
328/*
329 * Default speed selection (cpu_plb_opb_ebc) in mhz.
330 * This value will be set if iic boot eprom is disabled.
331 */
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100332#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
333#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100334
335#endif /* __CONFIG_H */