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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
wdenkc6097192002-11-03 00:24:07 +000031#ifndef __ASSEMBLY__
32#include <galileo/core.h>
33#endif
34
35#include "../board/evb64260/local.h"
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
wdenkc6097192002-11-03 00:24:07 +000044
Wolfgang Denk53677ef2008-05-20 16:00:29 +020045#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
wdenkc6097192002-11-03 00:24:07 +000046
47#undef CONFIG_ECC /* enable ECC support */
48/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
49
50/* which initialization functions to call for this board */
51#define CONFIG_MISC_INIT_R 1
wdenkc837dcb2004-01-20 23:12:12 +000052#define CONFIG_BOARD_EARLY_INIT_F 1
wdenkc6097192002-11-03 00:24:07 +000053
54#ifndef CONFIG_EVB64260_750CX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_BOARD_NAME "EVB64260"
wdenkc6097192002-11-03 00:24:07 +000056#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_BOARD_NAME "EVB64260-750CX"
wdenkc6097192002-11-03 00:24:07 +000058#endif
59
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_HUSH_PARSER
61#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +000062
63/*
64 * The following defines let you select what serial you want to use
65 * for your console driver.
66 *
67 * what to do:
68 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
wdenkc6097192002-11-03 00:24:07 +000070 * to 0 below.
71 *
72 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
73 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
74 */
75#define CONFIG_MPSC
76#define CONFIG_MPSC_PORT 0
77
78#define CONFIG_NET_MULTI /* attempt all available adapters */
79
80/* define this if you want to enable GT MAC filtering */
81#define CONFIG_GT_USE_MAC_HASH_TABLE
82
83#undef CONFIG_ETHER_PORT_MII /* use RMII */
84
85#if 1
86#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
87#else
88#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
89#endif
90#define CONFIG_ZERO_BOOTDELAY_CHECK
91
92#undef CONFIG_BOOTARGS
93#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020094 "bootp && " \
wdenkc6097192002-11-03 00:24:07 +000095 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
96 "ip=$ipaddr:$serverip:$gatewayip:" \
97 "$netmask:$hostname:eth0:none; && " \
98 "bootm"
99
100#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
wdenkc6097192002-11-03 00:24:07 +0000102
103#undef CONFIG_WATCHDOG /* watchdog disabled */
104#undef CONFIG_ALTIVEC /* undef to disable */
105
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500106/*
107 * BOOTP options
108 */
109#define CONFIG_BOOTP_SUBNETMASK
110#define CONFIG_BOOTP_GATEWAY
111#define CONFIG_BOOTP_HOSTNAME
112#define CONFIG_BOOTP_BOOTPATH
113#define CONFIG_BOOTP_BOOTFILESIZE
wdenkc6097192002-11-03 00:24:07 +0000114
115
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500116/*
117 * Command line configuration.
118 */
119#include <config_cmd_default.h>
wdenkc6097192002-11-03 00:24:07 +0000120
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500121#define CONFIG_CMD_ASKENV
122
wdenkc6097192002-11-03 00:24:07 +0000123
124/*
125 * Miscellaneous configurable options
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LONGHELP /* undef to save memory */
128#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500129#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000131#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000133#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
135#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
139#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
wdenkc6097192002-11-03 00:24:07 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200144#define CONFIG_SYS_BUS_CLK 100000000 /* 100 MHz */
wdenkc6097192002-11-03 00:24:07 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkc6097192002-11-03 00:24:07 +0000147
148#ifdef CONFIG_EVB64260_750CX
149#define CONFIG_750CX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BROKEN_CL2
wdenkc6097192002-11-03 00:24:07 +0000151#endif
152
153/*
154 * Low Level Configuration Settings
155 * (address mappings, register initial values, etc.)
156 * You should know what you are doing if you make changes here.
157 */
158
159/*-----------------------------------------------------------------------
160 * Definitions for initial stack pointer and data area
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
163#define CONFIG_SYS_INIT_RAM_END 0x1000
164#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
165#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
166#define CONFIG_SYS_INIT_RAM_LOCK
wdenkc6097192002-11-03 00:24:07 +0000167
168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_SDRAM_BASE 0x00000000
175#define CONFIG_SYS_FLASH_BASE 0xfff00000
176#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
177#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
178#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
179#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
wdenkc6097192002-11-03 00:24:07 +0000180
181/* areas to map different things with the GT in physical space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_DRAM_BANKS 4
183#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
wdenkc6097192002-11-03 00:24:07 +0000184
185/* What to put in the bats. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
wdenkc6097192002-11-03 00:24:07 +0000187
188/* Peripheral Device section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_GT_REGS 0xf8000000
190#define CONFIG_SYS_DEV_BASE 0xfc000000
wdenkc6097192002-11-03 00:24:07 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
193#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
194#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
195#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */
198#define CONFIG_SYS_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */
199#define CONFIG_SYS_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */
200#define CONFIG_SYS_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */
wdenkc6097192002-11-03 00:24:07 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_DEV0_PAR 0x20205093
203#define CONFIG_SYS_DEV1_PAR 0xcfcfffff
204#define CONFIG_SYS_DEV2_PAR 0xc0059bd4
205#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c
206#define CONFIG_SYS_32BIT_BOOT_PAR 0xc4a8241c
wdenk8bde7f72003-06-27 21:31:46 +0000207 /* c 4 a 8 2 4 1 c */
208 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
209 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
210 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
211 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
wdenkc6097192002-11-03 00:24:07 +0000212
213#if 0 /* Wrong?? NTL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
wdenkc6097192002-11-03 00:24:07 +0000215 /* DMAAck[1:0] GNT0[1:0] */
216#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
wdenkc6097192002-11-03 00:24:07 +0000218 /* REQ0[1:0] GNT0[1:0] */
219#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
wdenkc6097192002-11-03 00:24:07 +0000221 /* DMAReq[4] DMAAck[4] WDNMI WDE */
222#if 0 /* Wrong?? NTL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
wdenkc6097192002-11-03 00:24:07 +0000224 /* DMAAck[1:0] GNT1[1:0] */
225#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
wdenkc6097192002-11-03 00:24:07 +0000227 /* GPP[22] (RS232IntB or PCI1Int) */
228 /* GPP[21] (RS323IntA) */
229 /* BClkIn */
230 /* REQ1[1:0] GNT1[1:0] */
231#endif
232
233#if 0 /* Wrong?? NTL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
wdenkc6097192002-11-03 00:24:07 +0000235 /* GPP[27:26] Int[1:0] */
236#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
wdenk8bde7f72003-06-27 21:31:46 +0000238 /* GPP[29] (PCI1Int) */
239 /* BClkOut0 */
240 /* GPP[27] (PCI0Int) */
241 /* GPP[26] (RtcInt or PCI1Int) */
242 /* CPUInt[25:24] */
wdenkc6097192002-11-03 00:24:07 +0000243#endif
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
wdenkc6097192002-11-03 00:24:07 +0000246
247#if 0 /* Wrong?? - NTL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
wdenkc6097192002-11-03 00:24:07 +0000249#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
wdenk8bde7f72003-06-27 21:31:46 +0000251 /* gpp[29] */
wdenkc6097192002-11-03 00:24:07 +0000252 /* gpp[27:26] */
wdenk8bde7f72003-06-27 21:31:46 +0000253 /* gpp[22:21] */
wdenkc6097192002-11-03 00:24:07 +0000254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
wdenkc6097192002-11-03 00:24:07 +0000256 /* idmas use buffer 1,1
257 comm use buffer 0
258 pci use buffer 1,1
259 cpu use buffer 0
260 normal load (see also ifdef HVL)
261 standard SDRAM (see also ifdef REG)
262 non staggered refresh */
263 /* 31:26 25 23 20 19 18 16 */
264 /* 110110 00 111 0 0 00 1 */
265 /* refresh_count=0x200
266 phisical interleaving disable
267 virtual interleaving enable */
268 /* 15 14 13:0 */
269 /* 1 0 0x200 */
270#endif
271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
273#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
274#define CONFIG_SYS_INIT_CHAN1
275#define CONFIG_SYS_INIT_CHAN2
wdenkc6097192002-11-03 00:24:07 +0000276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
wdenkc6097192002-11-03 00:24:07 +0000278#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
279
280
281/*-----------------------------------------------------------------------
282 * PCI stuff
283 *-----------------------------------------------------------------------
284 */
285
286#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
287#define PCI_HOST_FORCE 1 /* configure as pci host */
288#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
289
290#define CONFIG_PCI /* include pci support */
291#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
292#define CONFIG_PCI_PNP /* do pci plug-and-play */
293
294/* PCI MEMORY MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
296#define CONFIG_SYS_PCI0_MEM_SIZE _128M
297#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
298#define CONFIG_SYS_PCI1_MEM_SIZE _128M
wdenkc6097192002-11-03 00:24:07 +0000299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
301#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
wdenkc6097192002-11-03 00:24:07 +0000302
303
wdenkc6097192002-11-03 00:24:07 +0000304/* PCI I/O MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
306#define CONFIG_SYS_PCI0_IO_SIZE _16M
307#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
308#define CONFIG_SYS_PCI1_IO_SIZE _16M
wdenkc6097192002-11-03 00:24:07 +0000309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
311#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
312#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
313#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
wdenkc6097192002-11-03 00:24:07 +0000314
315/*
316 * NS16550 Configuration
317 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_NS16550
wdenkc6097192002-11-03 00:24:07 +0000319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_NS16550_REG_SIZE -4
wdenkc6097192002-11-03 00:24:07 +0000321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_NS16550_CLK 3686400
wdenkc6097192002-11-03 00:24:07 +0000323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_DUART_IO + 0)
325#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_DUART_IO + 0x20)
wdenkc6097192002-11-03 00:24:07 +0000326
327/*----------------------------------------------------------------------
328 * Initial BAT mappings
329 */
330
331/* NOTES:
332 * 1) GUARDED and WRITE_THRU not allowed in IBATS
333 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
334 */
335
336/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
338#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
339#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
340#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
wdenkc6097192002-11-03 00:24:07 +0000341
342/* init ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
344#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
345#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
346#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenkc6097192002-11-03 00:24:07 +0000347
348/* PCI0, PCI1 in one BAT */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
350#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
351#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
352#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000353
354/* GT regs, bootrom, all the devices, PCI I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
356#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
357#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
358#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000359
360/* I2C speed and slave address (for compatability) defaults */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_I2C_SPEED 400000
362#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000363
364/* I2C addresses for the two DIMM SPD chips */
365#ifndef CONFIG_EVB64260_750CX
366#define DIMM0_I2C_ADDR 0x56
367#define DIMM1_I2C_ADDR 0x54
368#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
369#define DIMM0_I2C_ADDR 0x54
370#define DIMM1_I2C_ADDR 0x54
371#endif
372
373/*
374 * For booting Linux, the board info and command line data
375 * have to be in the first 8 MB of memory, since this is
376 * the maximum mapped by the Linux kernel during initialization.
377 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000379
380/*-----------------------------------------------------------------------
381 * FLASH organization
382 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
384#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
387#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */
wdenkc6097192002-11-03 00:24:07 +0000388
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
390#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
391#define CONFIG_SYS_FLASH_CFI 1
wdenkc6097192002-11-03 00:24:07 +0000392
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200393#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200394#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
395#define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000397
398/*-----------------------------------------------------------------------
399 * Cache Configuration
400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500402#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000404#endif
405
406/*-----------------------------------------------------------------------
407 * L2CR setup -- make sure this is right for your board!
wdenk1d0350e2002-11-11 21:14:20 +0000408 * look in include/74xx_7xx.h for the defines used here
wdenkc6097192002-11-03 00:24:07 +0000409 */
410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_L2
wdenkc6097192002-11-03 00:24:07 +0000412
413#ifdef CONFIG_750CX
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200414#define L2_INIT 0
wdenkc6097192002-11-03 00:24:07 +0000415#else
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200416#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
417 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
wdenkc6097192002-11-03 00:24:07 +0000418#endif
419
420#define L2_ENABLE (L2_INIT | L2CR_L2E)
421
422/*
423 * Internal Definitions
424 *
425 * Boot Flags
426 */
427#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
428#define BOOTFLAG_WARM 0x02 /* Software reboot */
429
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_BOARD_ASM_INIT 1
wdenkc6097192002-11-03 00:24:07 +0000431
432
433#endif /* __CONFIG_H */