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Hoan Hoang0f52b562009-01-18 22:44:17 -05001/*
2 * U-boot - Configuration file for IBF-DSP561 board
3 */
4
5#ifndef __CONFIG_IBF_DSP561__H__
6#define __CONFIG_IBF_DSP561__H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Hoan Hoang0f52b562009-01-18 22:44:17 -05009
10
11/*
12 * Processor Settings
13 */
14#define CONFIG_BFIN_CPU bf561-0.5
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 24
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 9
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x377
49#define CONFIG_EBIU_SDGCTL_VAL 0x91998d
50#define CONFIG_EBIU_SDBCTL_VAL 0x15
51
52#define CONFIG_EBIU_AMGCTL_VAL 0x3F
53#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
54#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
55
56#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
57#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
58
59
60/*
Hoan Hoang5cbbabc2010-05-10 15:38:55 -040061 * Network Settings
62 */
63#define ADI_CMDS_NETWORK 1
64#define CONFIG_NET_MULTI
65#define CONFIG_DRIVER_AX88180 1
66#define AX88180_BASE 0x2c000000
67#define CONFIG_HOSTNAME ibf-dsp561
68/* Uncomment next line to use fixed MAC address */
69/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
70
71
72/*
Hoan Hoang0f52b562009-01-18 22:44:17 -050073 * Flash Settings
74 */
75#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
76#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
77#define CONFIG_SYS_FLASH_CFI_AMD_RESET
78#define CONFIG_SYS_FLASH_BASE 0x20000000
79#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
80#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
81/* The BF561-EZKIT uses a top boot flash */
82#define CONFIG_ENV_IS_IN_FLASH 1
83#define CONFIG_ENV_ADDR 0x20004000
84#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
85#define CONFIG_ENV_SIZE 0x2000
86#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
87#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
88#define ENV_IS_EMBEDDED
89#else
Mike Frysinger76d82182009-07-21 22:17:36 -040090#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Hoan Hoang0f52b562009-01-18 22:44:17 -050091#endif
Mike Frysinger9ff67e52009-06-14 06:29:07 -040092#ifdef ENV_IS_EMBEDDED
93/* WARNING - the following is hand-optimized to fit within
94 * the sector before the environment sector. If it throws
95 * an error during compilation remove an object here to get
96 * it linked after the configuration sector.
97 */
98# define LDS_BOARD_TEXT \
Peter Tyserc6fb83d2010-04-12 22:28:13 -050099 arch/blackfin/cpu/traps.o (.text .text.*); \
100 arch/blackfin/cpu/interrupt.o (.text .text.*); \
101 arch/blackfin/cpu/serial.o (.text .text.*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400102 common/dlmalloc.o (.text .text.*); \
Peter Tyser78acc472010-04-12 22:28:05 -0500103 lib/crc32.o (.text .text.*); \
104 lib/zlib.o (.text .text.*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400105 board/ibf-dsp561/ibf-dsp561.o (.text .text.*); \
106 . = DEFINED(env_offset) ? env_offset : .; \
107 common/env_embedded.o (.text .text.*);
108#endif
Hoan Hoang0f52b562009-01-18 22:44:17 -0500109
110
111/*
112 * I2C Settings
113 */
114#define CONFIG_SOFT_I2C 1
Mike Frysingerbeb60e72010-06-08 16:22:44 -0400115#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
116#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
Hoan Hoang0f52b562009-01-18 22:44:17 -0500117
118
119/*
120 * Misc Settings
121 */
122#define CONFIG_UART_CONSOLE 0
123
124
125/*
126 * Pull in common ADI header for remaining command/environment setup
127 */
128#include <configs/bfin_adi_common.h>
129
Mike Frysingerf348ab82009-04-24 17:22:40 -0400130#endif