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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 711e2b2af820d21d9931d4cf8057d3894600fd54 / . / include / ppc440.h
blob: 4d2157a8f2eaf0511e4c168b71a56e360f15e509 [file] [log] [blame]
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1/*----------------------------------------------------------------------------+
2|
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]9|
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]13|
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]17|
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]20+----------------------------------------------------------------------------*/
21
Larry Johnsonc46f5332007-12-22 15:15:13 -0500[diff] [blame]22/*
23 * (C) Copyright 2006
24 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
25 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
26 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
27 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
28 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
29 *
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License as
32 * published by the Free Software Foundation; either version 2 of
33 * the License, or (at your option) any later version.
34 *
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
39 *
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43 * MA 02111-1307 USA
44 */
45
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]46#ifndef __PPC440_H__
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]47#define __PPC440_H__
48
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]49#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
Stefan Roese9b94ac62007-10-31 17:55:58 +0100[diff] [blame]50
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]51/*--------------------------------------------------------------------- */
52/* Special Purpose Registers */
53/*--------------------------------------------------------------------- */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]54#define xer_reg 0x001
55#define lr_reg 0x008
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]56#define dec 0x016 /* decrementer */
57#define srr0 0x01a /* save/restore register 0 */
58#define srr1 0x01b /* save/restore register 1 */
59#define pid 0x030 /* process id */
60#define decar 0x036 /* decrementer auto-reload */
61#define csrr0 0x03a /* critical save/restore register 0 */
62#define csrr1 0x03b /* critical save/restore register 1 */
63#define dear 0x03d /* data exception address register */
64#define esr 0x03e /* exception syndrome register */
65#define ivpr 0x03f /* interrupt prefix register */
66#define usprg0 0x100 /* user special purpose register general 0 */
67#define usprg1 0x110 /* user special purpose register general 1 */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]68#define tblr 0x10c /* time base lower, read only */
69#define tbur 0x10d /* time base upper, read only */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]70#define sprg1 0x111 /* special purpose register general 1 */
71#define sprg2 0x112 /* special purpose register general 2 */
72#define sprg3 0x113 /* special purpose register general 3 */
73#define sprg4 0x114 /* special purpose register general 4 */
74#define sprg5 0x115 /* special purpose register general 5 */
75#define sprg6 0x116 /* special purpose register general 6 */
76#define sprg7 0x117 /* special purpose register general 7 */
77#define tbl 0x11c /* time base lower (supervisor)*/
78#define tbu 0x11d /* time base upper (supervisor)*/
79#define pir 0x11e /* processor id register */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]80#define dbsr 0x130 /* debug status register */
81#define dbcr0 0x134 /* debug control register 0 */
82#define dbcr1 0x135 /* debug control register 1 */
83#define dbcr2 0x136 /* debug control register 2 */
84#define iac1 0x138 /* instruction address compare 1 */
85#define iac2 0x139 /* instruction address compare 2 */
86#define iac3 0x13a /* instruction address compare 3 */
87#define iac4 0x13b /* instruction address compare 4 */
88#define dac1 0x13c /* data address compare 1 */
89#define dac2 0x13d /* data address compare 2 */
90#define dvc1 0x13e /* data value compare 1 */
91#define dvc2 0x13f /* data value compare 2 */
92#define tsr 0x150 /* timer status register */
93#define tcr 0x154 /* timer control register */
94#define ivor0 0x190 /* interrupt vector offset register 0 */
95#define ivor1 0x191 /* interrupt vector offset register 1 */
96#define ivor2 0x192 /* interrupt vector offset register 2 */
97#define ivor3 0x193 /* interrupt vector offset register 3 */
98#define ivor4 0x194 /* interrupt vector offset register 4 */
99#define ivor5 0x195 /* interrupt vector offset register 5 */
100#define ivor6 0x196 /* interrupt vector offset register 6 */
101#define ivor7 0x197 /* interrupt vector offset register 7 */
102#define ivor8 0x198 /* interrupt vector offset register 8 */
103#define ivor9 0x199 /* interrupt vector offset register 9 */
104#define ivor10 0x19a /* interrupt vector offset register 10 */
105#define ivor11 0x19b /* interrupt vector offset register 11 */
106#define ivor12 0x19c /* interrupt vector offset register 12 */
107#define ivor13 0x19d /* interrupt vector offset register 13 */
108#define ivor14 0x19e /* interrupt vector offset register 14 */
109#define ivor15 0x19f /* interrupt vector offset register 15 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200[diff] [blame]110#if defined(CONFIG_440)
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]111#define mcsrr0 0x23a /* machine check save/restore register 0 */
112#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
113#define mcsr 0x23c /* machine check status register */
114#endif
115#define inv0 0x370 /* instruction cache normal victim 0 */
116#define inv1 0x371 /* instruction cache normal victim 1 */
117#define inv2 0x372 /* instruction cache normal victim 2 */
118#define inv3 0x373 /* instruction cache normal victim 3 */
119#define itv0 0x374 /* instruction cache transient victim 0 */
120#define itv1 0x375 /* instruction cache transient victim 1 */
121#define itv2 0x376 /* instruction cache transient victim 2 */
122#define itv3 0x377 /* instruction cache transient victim 3 */
123#define dnv0 0x390 /* data cache normal victim 0 */
124#define dnv1 0x391 /* data cache normal victim 1 */
125#define dnv2 0x392 /* data cache normal victim 2 */
126#define dnv3 0x393 /* data cache normal victim 3 */
127#define dtv0 0x394 /* data cache transient victim 0 */
128#define dtv1 0x395 /* data cache transient victim 1 */
129#define dtv2 0x396 /* data cache transient victim 2 */
130#define dtv3 0x397 /* data cache transient victim 3 */
131#define dvlim 0x398 /* data cache victim limit */
132#define ivlim 0x399 /* instruction cache victim limit */
133#define rstcfg 0x39b /* reset configuration */
134#define dcdbtrl 0x39c /* data cache debug tag register low */
135#define dcdbtrh 0x39d /* data cache debug tag register high */
136#define icdbtrl 0x39e /* instruction cache debug tag register low */
137#define icdbtrh 0x39f /* instruction cache debug tag register high */
138#define mmucr 0x3b2 /* mmu control register */
139#define ccr0 0x3b3 /* core configuration register 0 */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]140#define ccr1 0x378 /* core configuration for 440x5 only */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]141#define icdbdr 0x3d3 /* instruction cache debug data register */
142#define dbdr 0x3f3 /* debug data register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]143
144/******************************************************************************
145 * DCRs & Related
146 ******************************************************************************/
147
148/*-----------------------------------------------------------------------------
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]149 | Clocking Controller
150 +----------------------------------------------------------------------------*/
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]151/* values for clkcfga register - indirect addressing of these regs */
152#define clk_clkukpd 0x0020
153#define clk_pllc 0x0040
154#define clk_plld 0x0060
155#define clk_primad 0x0080
156#define clk_primbd 0x00a0
157#define clk_opbd 0x00c0
158#define clk_perd 0x00e0
159#define clk_mald 0x0100
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]160#define clk_spcid 0x0120
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]161#define clk_icfg 0x0140
162
163/* 440gx sdr register definations */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]164#define sdr_sdstp0 0x0020 /* */
165#define sdr_sdstp1 0x0021 /* */
Stefan Roese90e6f412007-04-18 12:05:59 +0200[diff] [blame]166#define SDR_PINSTP 0x0040
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]167#define sdr_sdcs 0x0060
168#define sdr_ecid0 0x0080
169#define sdr_ecid1 0x0081
170#define sdr_ecid2 0x0082
171#define sdr_jtag 0x00c0
Steven A. Falco711e2b22008-11-20 14:37:57 -0500[diff] [blame^]172#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
173#define SDR0_DDRCFG 0x00e0
174#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]175#define sdr_ebc 0x0100
176#define sdr_uart0 0x0120 /* UART0 Config */
177#define sdr_uart1 0x0121 /* UART1 Config */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]178#define sdr_uart2 0x0122 /* UART2 Config */
179#define sdr_uart3 0x0123 /* UART3 Config */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]180#define sdr_cp440 0x0180
181#define sdr_xcr 0x01c0
182#define sdr_xpllc 0x01c1
183#define sdr_xplld 0x01c2
184#define sdr_srst 0x0200
185#define sdr_slpipe 0x0220
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]186#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
187#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]188#define sdr_mirq0 0x0260
189#define sdr_mirq1 0x0261
190#define sdr_maltbl 0x0280
191#define sdr_malrbl 0x02a0
192#define sdr_maltbs 0x02c0
193#define sdr_malrbs 0x02e0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]194#define sdr_pci0 0x0300
195#define sdr_usb0 0x0320
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]196#define sdr_cust0 0x4000
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]197#define sdr_cust1 0x4002
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]198#define sdr_pfc0 0x4100 /* Pin Function 0 */
199#define sdr_pfc1 0x4101 /* Pin Function 1 */
200#define sdr_plbtr 0x4200
201#define sdr_mfr 0x4300 /* SDR0_MFR reg */
202
Marian Balakowiczbba68372006-06-30 18:35:04 +0200[diff] [blame]203#ifdef CONFIG_440GX
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]204#define sdr_amp 0x0240
205#define sdr_xpllc 0x01c1
206#define sdr_xplld 0x01c2
207#define sdr_xcr 0x01c0
208#define sdr_sdstp2 0x4001
209#define sdr_sdstp3 0x4003
Marian Balakowiczbba68372006-06-30 18:35:04 +0200[diff] [blame]210#endif /* CONFIG_440GX */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]211
Igor Lisitsina11e0692007-03-28 19:06:19 +0400[diff] [blame]212/*----------------------------------------------------------------------------+
213| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
214+----------------------------------------------------------------------------*/
215#define CCR0_PRE 0x40000000
216#define CCR0_CRPE 0x08000000
217#define CCR0_DSTG 0x00200000
218#define CCR0_DAPUIB 0x00100000
219#define CCR0_DTB 0x00008000
220#define CCR0_GICBT 0x00004000
221#define CCR0_GDCBT 0x00002000
222#define CCR0_FLSTA 0x00000100
223#define CCR0_ICSLC_MASK 0x0000000C
224#define CCR0_ICSLT_MASK 0x00000003
225#define CCR1_TCS_MASK 0x00000080
226#define CCR1_TCS_INTCLK 0x00000000
227#define CCR1_TCS_EXTCLK 0x00000080
228#define MMUCR_SWOA 0x01000000
229#define MMUCR_U1TE 0x00400000
230#define MMUCR_U2SWOAE 0x00200000
231#define MMUCR_DULXE 0x00800000
232#define MMUCR_IULXE 0x00400000
233#define MMUCR_STS 0x00100000
234#define MMUCR_STID_MASK 0x000000FF
Igor Lisitsina11e0692007-03-28 19:06:19 +0400[diff] [blame]235
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]236#ifdef CONFIG_440SPE
237#undef sdr_sdstp2
238#define sdr_sdstp2 0x0022
239#undef sdr_sdstp3
240#define sdr_sdstp3 0x0023
241#define sdr_ddr0 0x00E1
242#define sdr_uart2 0x0122
243#define sdr_xcr0 0x01c0
244/* #define sdr_xcr1 0x01c3 only one PCIX - SG */
245/* #define sdr_xcr2 0x01c6 only one PCIX - SG */
246#define sdr_xpllc0 0x01c1
247#define sdr_xplld0 0x01c2
248#define sdr_xpllc1 0x01c4 /*notRCW - SG */
249#define sdr_xplld1 0x01c5 /*notRCW - SG */
250#define sdr_xpllc2 0x01c7 /*notRCW - SG */
251#define sdr_xplld2 0x01c8 /*notRCW - SG */
252#define sdr_amp0 0x0240
253#define sdr_amp1 0x0241
254#define sdr_cust2 0x4004
255#define sdr_cust3 0x4006
256#define sdr_sdstp4 0x4001
257#define sdr_sdstp5 0x4003
258#define sdr_sdstp6 0x4005
259#define sdr_sdstp7 0x4007
260
Stefan Roesedf294492007-03-08 10:06:09 +0100[diff] [blame]261#endif /* CONFIG_440SPE */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]262
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]263/*-----------------------------------------------------------------------------
Wolfgang Denk6ed6ce62005-09-25 16:01:42 +0200[diff] [blame]264 | External Bus Controller
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]265 +----------------------------------------------------------------------------*/
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]266/* values for ebccfga register - indirect addressing of these regs */
267#define pb0cr 0x00 /* periph bank 0 config reg */
268#define pb1cr 0x01 /* periph bank 1 config reg */
269#define pb2cr 0x02 /* periph bank 2 config reg */
270#define pb3cr 0x03 /* periph bank 3 config reg */
271#define pb4cr 0x04 /* periph bank 4 config reg */
272#define pb5cr 0x05 /* periph bank 5 config reg */
273#define pb6cr 0x06 /* periph bank 6 config reg */
274#define pb7cr 0x07 /* periph bank 7 config reg */
275#define pb0ap 0x10 /* periph bank 0 access parameters */
276#define pb1ap 0x11 /* periph bank 1 access parameters */
277#define pb2ap 0x12 /* periph bank 2 access parameters */
278#define pb3ap 0x13 /* periph bank 3 access parameters */
279#define pb4ap 0x14 /* periph bank 4 access parameters */
280#define pb5ap 0x15 /* periph bank 5 access parameters */
281#define pb6ap 0x16 /* periph bank 6 access parameters */
282#define pb7ap 0x17 /* periph bank 7 access parameters */
283#define pbear 0x20 /* periph bus error addr reg */
284#define pbesr 0x21 /* periph bus error status reg */
285#define xbcfg 0x23 /* external bus configuration reg */
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]286#define EBC0_CFG 0x23 /* external bus configuration reg */
Wolfgang Denk6ed6ce62005-09-25 16:01:42 +0200[diff] [blame]287#define xbcid 0x24 /* external bus core id reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]288
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]289#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
290 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]291
292/* PLB4 to PLB3 Bridge OUT */
293#define P4P3_DCR_BASE 0x020
294#define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
295#define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
296#define p4p3_eadr (P4P3_DCR_BASE+0x2)
297#define p4p3_euadr (P4P3_DCR_BASE+0x3)
298#define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
299#define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
300#define p4p3_confg (P4P3_DCR_BASE+0x6)
301#define p4p3_pic (P4P3_DCR_BASE+0x7)
302#define p4p3_peir (P4P3_DCR_BASE+0x8)
303#define p4p3_rev (P4P3_DCR_BASE+0xA)
304
305/* PLB3 to PLB4 Bridge IN */
306#define P3P4_DCR_BASE 0x030
307#define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
308#define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
309#define p3p4_eadr (P3P4_DCR_BASE+0x2)
310#define p3p4_euadr (P3P4_DCR_BASE+0x3)
311#define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
312#define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
313#define p3p4_confg (P3P4_DCR_BASE+0x6)
314#define p3p4_pic (P3P4_DCR_BASE+0x7)
315#define p3p4_peir (P3P4_DCR_BASE+0x8)
316#define p3p4_rev (P3P4_DCR_BASE+0xA)
317
318/* PLB3 Arbiter */
319#define PLB3_DCR_BASE 0x070
320#define plb3_revid (PLB3_DCR_BASE+0x2)
321#define plb3_besr (PLB3_DCR_BASE+0x3)
322#define plb3_bear (PLB3_DCR_BASE+0x6)
323#define plb3_acr (PLB3_DCR_BASE+0x7)
324
325/* PLB4 Arbiter - PowerPC440EP Pass1 */
326#define PLB4_DCR_BASE 0x080
Stefan Roesea78bc442007-01-05 10:40:36 +0100[diff] [blame]327#define plb4_acr (PLB4_DCR_BASE+0x1)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]328#define plb4_revid (PLB4_DCR_BASE+0x2)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]329#define plb4_besr (PLB4_DCR_BASE+0x4)
330#define plb4_bearl (PLB4_DCR_BASE+0x6)
331#define plb4_bearh (PLB4_DCR_BASE+0x7)
332
Stefan Roesea78bc442007-01-05 10:40:36 +0100[diff] [blame]333#define PLB4_ACR_WRP (0x80000000 >> 7)
334
Stefan Roese17f50f222005-08-04 17:09:16 +0200[diff] [blame]335/* Pin Function Control Register 1 */
336#define SDR0_PFC1 0x4101
337#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
338#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
339#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
340#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
341#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
342#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
343#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
344#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
345#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
346#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
347#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
348#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
349#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
350#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
351#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
352#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
353#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
354#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
355#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
356#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
357#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
358#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
359#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
360#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
361
362#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
363#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
364#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
365#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
366
367/* USB Control Register */
368#define SDR0_USB0 0x0320
369#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
370#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
371#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
372#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
373#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
374#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
375
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]376/* Miscealleneaous Function Reg. */
377#define SDR0_MFR 0x4300
378#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
379#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
380#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
381#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
382#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
383#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
384#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
385#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
386#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
387#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
388#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
389#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
390#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
391
392#define SDR0_MFR_ERRATA3_EN0 0x00800000
393#define SDR0_MFR_ERRATA3_EN1 0x00400000
394#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
395#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
396#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
397#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
398#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
399
Stefan Roese8f24e062008-01-09 10:28:20 +0100[diff] [blame]400#define GPT0_COMP6 0x00000098
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100[diff] [blame]401#define GPT0_COMP5 0x00000094
402#define GPT0_COMP4 0x00000090
403#define GPT0_COMP3 0x0000008C
Yuri Tikhonov3d610182008-02-06 18:48:36 +0100[diff] [blame]404#define GPT0_COMP2 0x00000088
405#define GPT0_COMP1 0x00000084
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]406
Yuri Tikhonoveb0615b2008-04-24 10:30:53 +0200[diff] [blame]407#define GPT0_MASK6 0x000000D8
408#define GPT0_MASK5 0x000000D4
409#define GPT0_MASK4 0x000000D0
410#define GPT0_MASK3 0x000000CC
411#define GPT0_MASK2 0x000000C8
412#define GPT0_MASK1 0x000000C4
413
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]414#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Niklaus Gigerf780b832007-06-27 18:11:38 +0200[diff] [blame]415#define SDR0_USB2D0CR 0x0320
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]416#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
417#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
418#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
419
420#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
421#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
422#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
423
424#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
425#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
426#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
427
428/* USB2 Host Control Register */
429#define SDR0_USB2H0CR 0x0340
430#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
431#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
432#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
433#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
434
435/* Pin Function Control Register 1 */
436#define SDR0_PFC1 0x4101
437#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
438#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
439#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
440
441#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
442#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
443#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
444#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
445#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
446#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
447#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
448#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
449
450#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
451#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
452#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
453#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
454#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
455#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
456#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
457#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
458#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
459#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
460#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
461#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
462#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
463#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
464#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
465#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
466#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
467#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
468#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
469#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
470#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
471
472#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
473#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
474#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
475#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
476
477/* Ethernet PLL Configuration Register */
478#define SDR0_PFC2 0x4102
479#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
480#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
481#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
482#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
483
484#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
485#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
486#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
487#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
488#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
489#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
490#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
491#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
492
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200[diff] [blame]493#define SDR0_PFC4 0x4104
494
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]495/* USB2PHY0 Control Register */
496#define SDR0_USB2PHY0CR 0x4103
497#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
498#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
499#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
500
501#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
502#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
503#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
504
505#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
506#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
507#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
508
509#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
510#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
511#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
512
513#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
514#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
515#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
516
517#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
518#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
519#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
520
521#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
522#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
523#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
524
525#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
526#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
527#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
528
529#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
530#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
531#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
532
533#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
534#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
535#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
536#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
537
538/* Miscealleneaous Function Reg. */
539#define SDR0_MFR 0x4300
540#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
541#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
542#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
543#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
544#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
545#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
546#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
547#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
548#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
549#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
550#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
551
552#define SDR0_MFR_ERRATA3_EN0 0x00800000
553#define SDR0_MFR_ERRATA3_EN1 0x00400000
554#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
555#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
556#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
557#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
558#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
559
560#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
561
Stefan Roese17f50f222005-08-04 17:09:16 +0200[diff] [blame]562/* CUST1 Customer Configuration Register1 */
563#define SDR0_CUST1 0x4002
564#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
565#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
566#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
567
568/* Pin Function Control Register 0 */
569#define SDR0_PFC0 0x4100
570#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
571#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
572#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
573#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
574#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
575
576/* Pin Function Control Register 1 */
577#define SDR0_PFC1 0x4101
578#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
579#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
580#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
581#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
582#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
583#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
584#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
585#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
586#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
587#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
588#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
589#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
590#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
591#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
592#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
593#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
594#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
595#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
596#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
597#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
598#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
599#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
600#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
601#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
602
603#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
604#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
605#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
606#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
607
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]608#endif /* 440EP || 440GR || 440EPX || 440GRX */
609
610/*-----------------------------------------------------------------------------
611 | L2 Cache
612 +----------------------------------------------------------------------------*/
613#if defined (CONFIG_440GX) || \
614 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]615 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
616 defined(CONFIG_460SX)
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]617#define L2_CACHE_BASE 0x030
618#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
619#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
620#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
621#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
622#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
623#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
624#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
625#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
626
627#endif /* CONFIG_440GX */
628
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]629/*-----------------------------------------------------------------------------
630 | Internal SRAM
631 +----------------------------------------------------------------------------*/
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]632#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]633#define ISRAM0_DCR_BASE 0x380
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]634#else
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]635#define ISRAM0_DCR_BASE 0x020
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]636#endif
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]637#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
638#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
639#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
640#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
641#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
642#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
643#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
644#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
645#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
646#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
647#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
648
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]649#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
650 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
651 defined(CONFIG_460EX) || defined(CONFIG_460GT)
652/* CUST0 Customer Configuration Register0 */
653#define SDR0_CUST0 0x4000
654#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
655#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
656#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
657#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]658
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]659#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
660#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
661#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
662
663#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
664#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
665#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
666
667#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
668#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
669#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
670
671#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
672#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
673#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
674
675#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
676#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
677#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
678
679#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
680#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
681#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
682
683#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
684#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
685#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
686
687#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
688#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
689#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
690#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
691#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
692#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
693#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
694#endif
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]695
696/*-----------------------------------------------------------------------------
697 | On-Chip Buses
698 +----------------------------------------------------------------------------*/
699/* TODO: as needed */
700
701/*-----------------------------------------------------------------------------
702 | Clocking, Power Management and Chip Control
703 +----------------------------------------------------------------------------*/
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]704#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
705 defined(CONFIG_460SX)
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]706#define CNTRL_DCR_BASE 0x160
707#else
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]708#define CNTRL_DCR_BASE 0x0b0
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]709#endif
Eugene O'Brien5b2052e2008-04-11 10:00:35 -0400[diff] [blame]710
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]711#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
712#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
713#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]714
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]715#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
716#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
717#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
718#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]719
720#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
721#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
722#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
723#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
724
Stefan Roese5568e612005-11-22 13:20:42 +0100[diff] [blame]725#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
726
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]727#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
728#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]729
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]730/*-----------------------------------------------------------------------------
731 | DMA
732 +----------------------------------------------------------------------------*/
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]733#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
734#define DMA_DCR_BASE 0x200
735#else
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]736#define DMA_DCR_BASE 0x100
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]737#endif
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]738#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
739#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
740#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
741#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
742#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
743#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]744#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
745#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]746#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
747#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
748#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
749#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
750#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
751#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]752#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
753#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]754#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
755#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
756#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
757#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
758#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
759#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]760#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
761#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]762#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
763#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
764#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
765#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
766#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
767#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]768#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
769#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]770#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
771#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
772#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
773#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]774
775/*-----------------------------------------------------------------------------
776 | Memory Access Layer
777 +----------------------------------------------------------------------------*/
778#define MAL_DCR_BASE 0x180
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]779#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
780#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
781#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
782#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
783#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]784#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
785#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]786#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
787#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
788#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
789#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]790#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
791#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]792#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
793#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
794#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]795#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
796#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]797#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
798#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]799#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
800#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]801#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
802#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]803#if defined(CONFIG_440GX) || \
804 defined(CONFIG_460EX) || defined(CONFIG_460GT)
805#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
806#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
807#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100[diff] [blame]808#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
809#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]810#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
811#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]812#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100[diff] [blame]813#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
814#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200[diff] [blame]815#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]816
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]817/*-----------------------------------------------------------------------------+
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]818| SDR0 Bit Settings
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]819+-----------------------------------------------------------------------------*/
Stefan Roesedf294492007-03-08 10:06:09 +0100[diff] [blame]820#if defined(CONFIG_440SP)
821#define SDR0_SRST 0x0200
822
823#define SDR0_DDR0 0x00E1
824#define SDR0_DDR0_DPLLRST 0x80000000
825#define SDR0_DDR0_DDRM_MASK 0x60000000
826#define SDR0_DDR0_DDRM_DDR1 0x20000000
827#define SDR0_DDR0_DDRM_DDR2 0x40000000
828#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
829#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
830#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
831#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
832#endif
833
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]834#if defined(CONFIG_440SPE) || defined(CONFIG_460SX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]835#define SDR0_CP440 0x0180
836#define SDR0_CP440_ERPN_MASK 0x30000000
837#define SDR0_CP440_ERPN_MASK_HI 0x3000
838#define SDR0_CP440_ERPN_MASK_LO 0x0000
839#define SDR0_CP440_ERPN_EBC 0x10000000
840#define SDR0_CP440_ERPN_EBC_HI 0x1000
841#define SDR0_CP440_ERPN_EBC_LO 0x0000
842#define SDR0_CP440_ERPN_PCI 0x20000000
843#define SDR0_CP440_ERPN_PCI_HI 0x2000
844#define SDR0_CP440_ERPN_PCI_LO 0x0000
845#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
846#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
847#define SDR0_CP440_NTO1_MASK 0x00000002
848#define SDR0_CP440_NTO1_NTOP 0x00000000
849#define SDR0_CP440_NTO1_NTO1 0x00000002
850#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
851#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]852
853#define SDR0_SDSTP0 0x0020
854#define SDR0_SDSTP0_ENG_MASK 0x80000000
855#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
856#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
857#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
858#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
859#define SDR0_SDSTP0_SRC_MASK 0x40000000
860#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
861#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
862#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
863#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
864#define SDR0_SDSTP0_SEL_MASK 0x38000000
865#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
866#define SDR0_SDSTP0_SEL_CPU 0x08000000
867#define SDR0_SDSTP0_SEL_EBC 0x28000000
868#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
869#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
870#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
871#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
872#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
873#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
874#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
875#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
876#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
877#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
878#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
879#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
880#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
881#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
882#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
883#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
884#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
885#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
886#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
887#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
888
889
890#define SDR0_SDSTP1 0x0021
891#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
892#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
893#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
894#define SDR0_SDSTP1_PERDV0_MASK 0x03000000
895#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
896#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
897#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
898#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
899#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
900#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
901#define SDR0_SDSTP1_DDR1_MODE 0x00100000
902#define SDR0_SDSTP1_DDR2_MODE 0x00200000
903#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
904#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
905#define SDR0_SDSTP1_ERPN_MASK 0x00080000
906#define SDR0_SDSTP1_ERPN_EBC 0x00000000
907#define SDR0_SDSTP1_ERPN_PCI 0x00080000
908#define SDR0_SDSTP1_PAE_MASK 0x00040000
909#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
910#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
911#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
912#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
913#define SDR0_SDSTP1_PHCE_MASK 0x00020000
914#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
915#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
916#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
917#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
918#define SDR0_SDSTP1_PISE_MASK 0x00010000
919#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
920#define SDR0_SDSTP1_PISE_ENABLE 0x00001000
921#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
922#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
923#define SDR0_SDSTP1_PCWE_MASK 0x00008000
924#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
925#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
926#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
927#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
928#define SDR0_SDSTP1_PPIM_MASK 0x00007800
929#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
930#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
931#define SDR0_SDSTP1_PR64E_MASK 0x00000400
932#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
933#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
934#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
935#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
936#define SDR0_SDSTP1_PXFS_MASK 0x00000300
937#define SDR0_SDSTP1_PXFS_100_133 0x00000000
938#define SDR0_SDSTP1_PXFS_66_100 0x00000100
939#define SDR0_SDSTP1_PXFS_50_66 0x00000200
940#define SDR0_SDSTP1_PXFS_0_50 0x00000300
941#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
942#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
943#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
944#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
945#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
946#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
947#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
948#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
949#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
950#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
951#define SDR0_SDSTP1_ETH_MASK 0x00000004
952#define SDR0_SDSTP1_ETH_10_100 0x00000000
953#define SDR0_SDSTP1_ETH_GIGA 0x00000004
954#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
955#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
956#define SDR0_SDSTP1_NTO1_MASK 0x00000001
957#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
958#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
959#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
960#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
961
962#define SDR0_SDSTP2 0x0022
963#define SDR0_SDSTP2_P1AE_MASK 0x80000000
964#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
965#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
966#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
967#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
968#define SDR0_SDSTP2_P1HCE_MASK 0x40000000
969#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
970#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
971#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
972#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
973#define SDR0_SDSTP2_P1ISE_MASK 0x20000000
974#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
975#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
976#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
977#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
978#define SDR0_SDSTP2_P1CWE_MASK 0x10000000
979#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
980#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
981#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
982#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
983#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
984#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
985#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
986#define SDR0_SDSTP2_P1R64E_MASK 0x00800000
987#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
988#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
989#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
990#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
991#define SDR0_SDSTP2_P1XFS_MASK 0x00600000
992#define SDR0_SDSTP2_P1XFS_100_133 0x00000000
993#define SDR0_SDSTP2_P1XFS_66_100 0x00200000
994#define SDR0_SDSTP2_P1XFS_50_66 0x00400000
995#define SDR0_SDSTP2_P1XFS_0_50 0x00600000
996#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
997#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
998#define SDR0_SDSTP2_P2AE_MASK 0x00040000
999#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
1000#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
1001#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
1002#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
1003#define SDR0_SDSTP2_P2HCE_MASK 0x00020000
1004#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
1005#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
1006#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
1007#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
1008#define SDR0_SDSTP2_P2ISE_MASK 0x00010000
1009#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
1010#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
1011#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
1012#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
1013#define SDR0_SDSTP2_P2CWE_MASK 0x00008000
1014#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
1015#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
1016#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
1017#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
1018#define SDR0_SDSTP2_P2PIM_MASK 0x00007800
1019#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
1020#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
1021#define SDR0_SDSTP2_P2XFS_MASK 0x00000300
1022#define SDR0_SDSTP2_P2XFS_100_133 0x00000000
1023#define SDR0_SDSTP2_P2XFS_66_100 0x00000100
1024#define SDR0_SDSTP2_P2XFS_50_66 0x00000200
1025#define SDR0_SDSTP2_P2XFS_0_50 0x00000100
1026#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
1027#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
1028
1029#define SDR0_SDSTP3 0x0023
1030
1031#define SDR0_PINSTP 0x0040
1032#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
1033#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
1034#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
1035#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
1036#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
1037#define SDR0_SDCS 0x0060
1038#define SDR0_ECID0 0x0080
1039#define SDR0_ECID1 0x0081
1040#define SDR0_ECID2 0x0082
1041#define SDR0_JTAG 0x00C0
1042
1043#define SDR0_DDR0 0x00E1
1044#define SDR0_DDR0_DPLLRST 0x80000000
1045#define SDR0_DDR0_DDRM_MASK 0x60000000
1046#define SDR0_DDR0_DDRM_DDR1 0x20000000
1047#define SDR0_DDR0_DDRM_DDR2 0x40000000
1048#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1049#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1050#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1051#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
1052
1053#define SDR0_UART0 0x0120
1054#define SDR0_UART1 0x0121
1055#define SDR0_UART2 0x0122
1056#define SDR0_UARTX_UXICS_MASK 0xF0000000
1057#define SDR0_UARTX_UXICS_PLB 0x20000000
1058#define SDR0_UARTX_UXEC_MASK 0x00800000
1059#define SDR0_UARTX_UXEC_INT 0x00000000
1060#define SDR0_UARTX_UXEC_EXT 0x00800000
1061#define SDR0_UARTX_UXDIV_MASK 0x000000FF
1062#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1063#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
1064
1065#define SDR0_CP440 0x0180
1066#define SDR0_CP440_ERPN_MASK 0x30000000
1067#define SDR0_CP440_ERPN_MASK_HI 0x3000
1068#define SDR0_CP440_ERPN_MASK_LO 0x0000
1069#define SDR0_CP440_ERPN_EBC 0x10000000
1070#define SDR0_CP440_ERPN_EBC_HI 0x1000
1071#define SDR0_CP440_ERPN_EBC_LO 0x0000
1072#define SDR0_CP440_ERPN_PCI 0x20000000
1073#define SDR0_CP440_ERPN_PCI_HI 0x2000
1074#define SDR0_CP440_ERPN_PCI_LO 0x0000
1075#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1076#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1077#define SDR0_CP440_NTO1_MASK 0x00000002
1078#define SDR0_CP440_NTO1_NTOP 0x00000000
1079#define SDR0_CP440_NTO1_NTO1 0x00000002
1080#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1081#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
1082
1083#define SDR0_XCR0 0x01C0
1084#define SDR0_XCR1 0x01C3
1085#define SDR0_XCR2 0x01C6
1086#define SDR0_XCRn_PAE_MASK 0x80000000
1087#define SDR0_XCRn_PAE_DISABLE 0x00000000
1088#define SDR0_XCRn_PAE_ENABLE 0x80000000
1089#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1090#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1091#define SDR0_XCRn_PHCE_MASK 0x40000000
1092#define SDR0_XCRn_PHCE_DISABLE 0x00000000
1093#define SDR0_XCRn_PHCE_ENABLE 0x40000000
1094#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1095#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1096#define SDR0_XCRn_PISE_MASK 0x20000000
1097#define SDR0_XCRn_PISE_DISABLE 0x00000000
1098#define SDR0_XCRn_PISE_ENABLE 0x20000000
1099#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1100#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1101#define SDR0_XCRn_PCWE_MASK 0x10000000
1102#define SDR0_XCRn_PCWE_DISABLE 0x00000000
1103#define SDR0_XCRn_PCWE_ENABLE 0x10000000
1104#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1105#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1106#define SDR0_XCRn_PPIM_MASK 0x0F000000
1107#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1108#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1109#define SDR0_XCRn_PR64E_MASK 0x00800000
1110#define SDR0_XCRn_PR64E_DISABLE 0x00000000
1111#define SDR0_XCRn_PR64E_ENABLE 0x00800000
1112#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1113#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1114#define SDR0_XCRn_PXFS_MASK 0x00600000
1115#define SDR0_XCRn_PXFS_100_133 0x00000000
1116#define SDR0_XCRn_PXFS_66_100 0x00200000
1117#define SDR0_XCRn_PXFS_50_66 0x00400000
1118#define SDR0_XCRn_PXFS_0_33 0x00600000
1119#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1120#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1121
1122#define SDR0_XPLLC0 0x01C1
1123#define SDR0_XPLLD0 0x01C2
1124#define SDR0_XPLLC1 0x01C4
1125#define SDR0_XPLLD1 0x01C5
1126#define SDR0_XPLLC2 0x01C7
1127#define SDR0_XPLLD2 0x01C8
1128#define SDR0_SRST 0x0200
1129#define SDR0_SLPIPE 0x0220
1130
1131#define SDR0_AMP0 0x0240
1132#define SDR0_AMP0_PRIORITY 0xFFFF0000
1133#define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
1134#define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
1135
1136#define SDR0_AMP1 0x0241
1137#define SDR0_AMP1_PRIORITY 0xFC000000
1138#define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
1139#define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
1140
1141#define SDR0_MIRQ0 0x0260
1142#define SDR0_MIRQ1 0x0261
1143#define SDR0_MALTBL 0x0280
1144#define SDR0_MALRBL 0x02A0
1145#define SDR0_MALTBS 0x02C0
1146#define SDR0_MALRBS 0x02E0
1147
1148/* Reserved for Customer Use */
1149#define SDR0_CUST0 0x4000
1150#define SDR0_CUST0_AUTONEG_MASK 0x8000000
1151#define SDR0_CUST0_NO_AUTONEG 0x0000000
1152#define SDR0_CUST0_AUTONEG 0x8000000
1153#define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
1154#define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
1155#define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
1156#define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
1157#define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
1158#define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
1159#define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
1160
1161#define SDR0_SDSTP4 0x4001
1162#define SDR0_CUST1 0x4002
1163#define SDR0_SDSTP5 0x4003
1164#define SDR0_CUST2 0x4004
1165#define SDR0_SDSTP6 0x4005
1166#define SDR0_CUST3 0x4006
1167#define SDR0_SDSTP7 0x4007
1168
1169#define SDR0_PFC0 0x4100
1170#define SDR0_PFC0_GPIO_0 0x80000000
1171#define SDR0_PFC0_PCIX0REQ2_N 0x00000000
1172#define SDR0_PFC0_GPIO_1 0x40000000
1173#define SDR0_PFC0_PCIX0REQ3_N 0x00000000
1174#define SDR0_PFC0_GPIO_2 0x20000000
1175#define SDR0_PFC0_PCIX0GNT2_N 0x00000000
1176#define SDR0_PFC0_GPIO_3 0x10000000
1177#define SDR0_PFC0_PCIX0GNT3_N 0x00000000
1178#define SDR0_PFC0_GPIO_4 0x08000000
1179#define SDR0_PFC0_PCIX1REQ2_N 0x00000000
1180#define SDR0_PFC0_GPIO_5 0x04000000
1181#define SDR0_PFC0_PCIX1REQ3_N 0x00000000
1182#define SDR0_PFC0_GPIO_6 0x02000000
1183#define SDR0_PFC0_PCIX1GNT2_N 0x00000000
1184#define SDR0_PFC0_GPIO_7 0x01000000
1185#define SDR0_PFC0_PCIX1GNT3_N 0x00000000
1186#define SDR0_PFC0_GPIO_8 0x00800000
1187#define SDR0_PFC0_PERREADY 0x00000000
1188#define SDR0_PFC0_GPIO_9 0x00400000
1189#define SDR0_PFC0_PERCS1_N 0x00000000
1190#define SDR0_PFC0_GPIO_10 0x00200000
1191#define SDR0_PFC0_PERCS2_N 0x00000000
1192#define SDR0_PFC0_GPIO_11 0x00100000
1193#define SDR0_PFC0_IRQ0 0x00000000
1194#define SDR0_PFC0_GPIO_12 0x00080000
1195#define SDR0_PFC0_IRQ1 0x00000000
1196#define SDR0_PFC0_GPIO_13 0x00040000
1197#define SDR0_PFC0_IRQ2 0x00000000
1198#define SDR0_PFC0_GPIO_14 0x00020000
1199#define SDR0_PFC0_IRQ3 0x00000000
1200#define SDR0_PFC0_GPIO_15 0x00010000
1201#define SDR0_PFC0_IRQ4 0x00000000
1202#define SDR0_PFC0_GPIO_16 0x00008000
1203#define SDR0_PFC0_IRQ5 0x00000000
1204#define SDR0_PFC0_GPIO_17 0x00004000
1205#define SDR0_PFC0_PERBE0_N 0x00000000
1206#define SDR0_PFC0_GPIO_18 0x00002000
1207#define SDR0_PFC0_PCI0GNT0_N 0x00000000
1208#define SDR0_PFC0_GPIO_19 0x00001000
1209#define SDR0_PFC0_PCI0GNT1_N 0x00000000
1210#define SDR0_PFC0_GPIO_20 0x00000800
1211#define SDR0_PFC0_PCI0REQ0_N 0x00000000
1212#define SDR0_PFC0_GPIO_21 0x00000400
1213#define SDR0_PFC0_PCI0REQ1_N 0x00000000
1214#define SDR0_PFC0_GPIO_22 0x00000200
1215#define SDR0_PFC0_PCI1GNT0_N 0x00000000
1216#define SDR0_PFC0_GPIO_23 0x00000100
1217#define SDR0_PFC0_PCI1GNT1_N 0x00000000
1218#define SDR0_PFC0_GPIO_24 0x00000080
1219#define SDR0_PFC0_PCI1REQ0_N 0x00000000
1220#define SDR0_PFC0_GPIO_25 0x00000040
1221#define SDR0_PFC0_PCI1REQ1_N 0x00000000
1222#define SDR0_PFC0_GPIO_26 0x00000020
1223#define SDR0_PFC0_PCI2GNT0_N 0x00000000
1224#define SDR0_PFC0_GPIO_27 0x00000010
1225#define SDR0_PFC0_PCI2GNT1_N 0x00000000
1226#define SDR0_PFC0_GPIO_28 0x00000008
1227#define SDR0_PFC0_PCI2REQ0_N 0x00000000
1228#define SDR0_PFC0_GPIO_29 0x00000004
1229#define SDR0_PFC0_PCI2REQ1_N 0x00000000
1230#define SDR0_PFC0_GPIO_30 0x00000002
1231#define SDR0_PFC0_UART1RX 0x00000000
1232#define SDR0_PFC0_GPIO_31 0x00000001
1233#define SDR0_PFC0_UART1TX 0x00000000
1234
1235#define SDR0_PFC1 0x4101
1236#define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
1237#define SDR0_PFC1_UART1_DSR_DTR 0x00000000
1238#define SDR0_PFC1_UART1_CTS_RTS 0x02000000
1239#define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
1240#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
1241#define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
1242#define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
1243#define SDR0_PFC1_ETH_10_100 0x00000000
1244#define SDR0_PFC1_ETH_GIGA 0x00200000
1245#define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
1246#define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1247#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
1248#define SDR0_PFC1_CPU_NO_TRACE 0x00000000
1249#define SDR0_PFC1_CPU_TRACE 0x00080000
1250#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
1251#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
1252
1253#define SDR0_MFR 0x4300
1254#endif /* CONFIG_440SPE */
1255
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1256#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1257/* Pin Function Control Register 0 (SDR0_PFC0) */
1258#define SDR0_PFC0 0x4100
1259#define SDR0_PFC0_DBG 0x00008000 /* debug enable */
1260#define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */
1261#define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */
1262#define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */
1263#define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */
1264#define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */
1265#define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */
1266#define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */
1267#define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */
1268#define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */
1269#define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */
1270#define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */
1271#define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */
1272#define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */
1273#define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */
1274#define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */
1275
1276/* Pin Function Control Register 1 (SDR0_PFC1) */
1277#define SDR0_PFC1 0x4101
1278#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1279#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1280#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1281#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1282#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1283#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1284#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1285#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/
1286#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/
1287#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1288#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1289#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1290
1291/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
1292#define SDR0_ETH_PLL 0x4102
1293#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
1294#define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */
1295#define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */
1296#define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */
1297#define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */
1298#define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16)
1299#define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */
1300#define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8)
1301#define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */
1302#define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4)
1303#define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */
1304#define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f)
1305
1306/* Ethernet Configuration Register (SDR0_ETH_CFG) */
1307#define SDR0_ETH_CFG 0x4103
1308#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */
1309#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */
1310#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */
1311#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */
1312#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */
1313#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */
1314#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */
1315#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */
1316#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */
1317#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */
1318#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */
1319#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */
1320#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */
1321#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */
1322#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */
1323#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */
1324#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */
1325#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */
1326#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */
1327#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */
1328#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */
1329#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */
1330#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */
1331#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */
1332#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */
1333#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */
1334#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */
1335#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */
1336
1337#define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4
1338#define SDR0_ETH_CFG_ZMII_MII_MODE 0x00
1339#define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01
1340#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
1341#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
1342
Adam Grahamf09f09d2008-10-08 10:12:53 -0700[diff] [blame]1343/* Ethernet Status Register */
1344#define SDR0_ETH_STS 0x4104
1345
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1346/* Miscealleneaous Function Reg. (SDR0_MFR) */
1347#define SDR0_MFR 0x4300
1348#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
1349#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */
1350#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */
1351#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */
1352#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */
1353#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */
1354#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */
1355#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */
1356#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */
1357#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */
1358#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */
1359#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */
1360#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */
1361#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */
1362#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */
1363#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */
1364#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */
1365#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */
1366#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */
1367#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */
1368
1369/* EMACx TX Status Register (SDR0_EMACxTXST)*/
1370#define SDR0_EMAC0TXST 0x4400
1371#define SDR0_EMAC1TXST 0x4401
1372#define SDR0_EMAC2TXST 0x4402
1373#define SDR0_EMAC3TXST 0x4403
1374
1375#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
1376#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
1377#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
1378#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
1379#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
1380#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */
1381#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
1382#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
1383#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
1384#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
1385#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
1386#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
1387#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
1388#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
1389#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
1390#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
1391#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
1392#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
1393#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
1394#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
1395#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
1396#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
1397#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
1398#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
1399
1400/* EMACx RX Status Register (SDR0_EMACxRXST)*/
1401#define SDR0_EMAC0RXST 0x4404
1402#define SDR0_EMAC1RXST 0x4405
1403#define SDR0_EMAC2RXST 0x4406
1404#define SDR0_EMAC3RXST 0x4407
1405
1406#define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */
1407#define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */
1408#define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */
1409#define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */
1410#define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */
1411#define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23)
1412#define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */
1413#define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */
1414#define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */
1415#define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */
1416#define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/
1417#define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/
1418#define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */
1419#define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */
1420#define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */
1421#define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */
1422#define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */
1423#define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */
1424#define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */
1425#define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */
1426#define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */
1427#define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */
1428#define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */
1429#define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */
1430#define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */
1431#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */
1432#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
1433#define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */
1434
1435/* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
1436#define SDR0_EMAC0REJCNT 0x4408
1437#define SDR0_EMAC1REJCNT 0x4409
1438#define SDR0_EMAC2REJCNT 0x440A
1439#define SDR0_EMAC3REJCNT 0x440B
1440
1441#define SDR0_DDR0 0x00E1
1442#define SDR0_DDR0_DPLLRST 0x80000000
1443#define SDR0_DDR0_DDRM_MASK 0x60000000
1444#define SDR0_DDR0_DDRM_DDR1 0x20000000
1445#define SDR0_DDR0_DDRM_DDR2 0x40000000
1446#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1447#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1448#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1449#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
Stefan Roese41712b42008-03-05 12:31:53 +0100[diff] [blame]1450
1451#define AHB_TOP 0xA4
1452#define AHB_BOT 0xA5
Stefan Roese745d8a02008-06-28 14:56:17 +0200[diff] [blame]1453#define SDR0_AHB_CFG 0x370
1454#define SDR0_USB2HOST_CFG 0x371
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1455#endif /* CONFIG_460EX || CONFIG_460GT */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200[diff] [blame]1456
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]1457#define SDR0_SDCS_SDD (0x80000000 >> 31)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1458
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]1459#if defined(CONFIG_440GP)
1460#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
1461#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
1462#endif /* defined(CONFIG_440GP) */
1463#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
1464#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
1465#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
1466#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1467#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1468 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]1469#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
1470#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
1471#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1472
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1473#define SDR0_UARTX_UXICS_MASK 0xF0000000
1474#define SDR0_UARTX_UXICS_PLB 0x20000000
1475#define SDR0_UARTX_UXEC_MASK 0x00800000
1476#define SDR0_UARTX_UXEC_INT 0x00000000
1477#define SDR0_UARTX_UXEC_EXT 0x00800000
1478#define SDR0_UARTX_UXDTE_MASK 0x00400000
1479#define SDR0_UARTX_UXDTE_DISABLE 0x00000000
1480#define SDR0_UARTX_UXDTE_ENABLE 0x00400000
1481#define SDR0_UARTX_UXDRE_MASK 0x00200000
1482#define SDR0_UARTX_UXDRE_DISABLE 0x00000000
1483#define SDR0_UARTX_UXDRE_ENABLE 0x00200000
1484#define SDR0_UARTX_UXDC_MASK 0x00100000
1485#define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
1486#define SDR0_UARTX_UXDC_CLEARED 0x00100000
1487#define SDR0_UARTX_UXDIV_MASK 0x000000FF
1488#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1489#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1490
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1491#define SDR0_CPU440_EARV_MASK 0x30000000
1492#define SDR0_CPU440_EARV_EBC 0x10000000
1493#define SDR0_CPU440_EARV_PCI 0x20000000
1494#define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1495#define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1496#define SDR0_CPU440_NTO1_MASK 0x00000002
1497#define SDR0_CPU440_NTO1_NTOP 0x00000000
1498#define SDR0_CPU440_NTO1_NTO1 0x00000002
1499#define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1500#define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1501
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1502#define SDR0_XCR_PAE_MASK 0x80000000
1503#define SDR0_XCR_PAE_DISABLE 0x00000000
1504#define SDR0_XCR_PAE_ENABLE 0x80000000
1505#define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1506#define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1507#define SDR0_XCR_PHCE_MASK 0x40000000
1508#define SDR0_XCR_PHCE_DISABLE 0x00000000
1509#define SDR0_XCR_PHCE_ENABLE 0x40000000
1510#define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1511#define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1512#define SDR0_XCR_PISE_MASK 0x20000000
1513#define SDR0_XCR_PISE_DISABLE 0x00000000
1514#define SDR0_XCR_PISE_ENABLE 0x20000000
1515#define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1516#define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1517#define SDR0_XCR_PCWE_MASK 0x10000000
1518#define SDR0_XCR_PCWE_DISABLE 0x00000000
1519#define SDR0_XCR_PCWE_ENABLE 0x10000000
1520#define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1521#define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1522#define SDR0_XCR_PPIM_MASK 0x0F000000
1523#define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1524#define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1525#define SDR0_XCR_PR64E_MASK 0x00800000
1526#define SDR0_XCR_PR64E_DISABLE 0x00000000
1527#define SDR0_XCR_PR64E_ENABLE 0x00800000
1528#define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1529#define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1530#define SDR0_XCR_PXFS_MASK 0x00600000
1531#define SDR0_XCR_PXFS_HIGH 0x00000000
1532#define SDR0_XCR_PXFS_MED 0x00200000
1533#define SDR0_XCR_PXFS_LOW 0x00400000
1534#define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1535#define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1536#define SDR0_XCR_PDM_MASK 0x00000040
1537#define SDR0_XCR_PDM_MULTIPOINT 0x00000000
1538#define SDR0_XCR_PDM_P2P 0x00000040
1539#define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
1540#define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1541
1542#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1543#define SDR0_PFC0_GEIE_MASK 0x00003E00
1544#define SDR0_PFC0_GEIE_TRE 0x00003E00
1545#define SDR0_PFC0_GEIE_NOTRE 0x00000000
1546#define SDR0_PFC0_TRE_MASK 0x00000100
1547#define SDR0_PFC0_TRE_DISABLE 0x00000000
1548#define SDR0_PFC0_TRE_ENABLE 0x00000100
1549#define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1550#define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1551
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1552#define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
1553#define SDR0_PFC1_EPS_MASK 0x01C00000
1554#define SDR0_PFC1_EPS_GROUP0 0x00000000
1555#define SDR0_PFC1_EPS_GROUP1 0x00400000
1556#define SDR0_PFC1_EPS_GROUP2 0x00800000
1557#define SDR0_PFC1_EPS_GROUP3 0x00C00000
1558#define SDR0_PFC1_EPS_GROUP4 0x01000000
1559#define SDR0_PFC1_EPS_GROUP5 0x01400000
1560#define SDR0_PFC1_EPS_GROUP6 0x01800000
1561#define SDR0_PFC1_EPS_GROUP7 0x01C00000
1562#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1563#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1564#define SDR0_PFC1_RMII_MASK 0x00200000
1565#define SDR0_PFC1_RMII_100MBIT 0x00000000
1566#define SDR0_PFC1_RMII_10MBIT 0x00200000
1567#define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
1568#define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1569#define SDR0_PFC1_CTEMS_MASK 0x00100000
1570#define SDR0_PFC1_CTEMS_EMS 0x00000000
1571#define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1572
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1573#define SDR0_MFR_TAH0_MASK 0x80000000
1574#define SDR0_MFR_TAH0_ENABLE 0x00000000
1575#define SDR0_MFR_TAH0_DISABLE 0x80000000
1576#define SDR0_MFR_TAH1_MASK 0x40000000
1577#define SDR0_MFR_TAH1_ENABLE 0x00000000
1578#define SDR0_MFR_TAH1_DISABLE 0x40000000
1579#define SDR0_MFR_PCM_MASK 0x20000000
1580#define SDR0_MFR_PCM_PPC440GX 0x00000000
1581#define SDR0_MFR_PCM_PPC440GP 0x20000000
1582#define SDR0_MFR_ECS_MASK 0x10000000
1583#define SDR0_MFR_ECS_INTERNAL 0x10000000
1584
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1585#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
1586#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
1587#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1588#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1589#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1590#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1591#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1592#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1593#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1594#define SDR0_MFR_ERRATA3_EN0 0x00800000
1595#define SDR0_MFR_ERRATA3_EN1 0x00400000
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1596#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1597#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
1598#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1599#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
1600#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
1601#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1602#endif
1603
1604#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1605#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1606#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1607#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
1608#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
1609#endif
1610
1611#define SDR0_MFR_ECS_MASK 0x10000000
1612#define SDR0_MFR_ECS_INTERNAL 0x10000000
1613
1614#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1615#define SDR0_SRST0 0x200
1616#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1617#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1618#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1619#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1620#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1621#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1622#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1623#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
1624#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
1625#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1626#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1627#define SDR0_SRST0_PCI 0x00100000 /* PCI */
1628#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
1629#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
1630#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1631#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
1632#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
1633#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
1634#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
1635#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
1636#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
1637#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
1638#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
1639#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1640#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
1641#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1642#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
1643#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
1644#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
1645#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
1646#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
1647
1648#define SDR0_SRST1 0x201
1649#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
1650#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
1651#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
1652#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
1653#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
1654#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
1655#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
1656#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
1657#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
1658#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
1659#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
1660#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
1661#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
1662#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
1663#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
1664#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
1665#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
1666#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
1667#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
1668#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
1669
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1670#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1671
1672#define SDR0_SRST0 0x0200
1673#define SDR0_SRST SDR0_SRST0 /* for compatability reasons */
1674#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1675#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1676#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1677#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1678#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1679#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1680#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1681#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
1682#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
1683#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1684#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1685#define SDR0_SRST0_PCI 0x00100000 /* PCI */
1686#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1687#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */
1688#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/
1689#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/
1690#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/
1691#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
1692#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
1693#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
1694#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */
1695#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1696#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1697#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
1698#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */
1699#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
1700
1701#define SDR0_SRST1 0x201
1702#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */
1703#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */
1704#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
1705#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
1706#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
1707#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */
1708#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */
1709#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */
1710#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */
1711#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
1712#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
1713#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
1714#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
1715#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
1716#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
1717#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */
1718#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
1719#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
1720#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
1721#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */
1722#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */
1723#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */
1724#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */
1725#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */
1726#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */
1727#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
1728#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */
1729#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */
1730#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */
1731#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */
1732#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */
1733#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */
1734
1735#define SDR0_PCI0 0x1c0 /* PCI Configuration Register */
1736
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1737#else
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1738
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1739#define SDR0_SRST_BGO 0x80000000
1740#define SDR0_SRST_PLB 0x40000000
1741#define SDR0_SRST_EBC 0x20000000
1742#define SDR0_SRST_OPB 0x10000000
1743#define SDR0_SRST_UART0 0x08000000
1744#define SDR0_SRST_UART1 0x04000000
1745#define SDR0_SRST_IIC0 0x02000000
1746#define SDR0_SRST_IIC1 0x01000000
1747#define SDR0_SRST_GPIO 0x00800000
1748#define SDR0_SRST_GPT 0x00400000
1749#define SDR0_SRST_DMC 0x00200000
1750#define SDR0_SRST_PCI 0x00100000
1751#define SDR0_SRST_EMAC0 0x00080000
1752#define SDR0_SRST_EMAC1 0x00040000
1753#define SDR0_SRST_CPM 0x00020000
1754#define SDR0_SRST_IMU 0x00010000
1755#define SDR0_SRST_UIC01 0x00008000
1756#define SDR0_SRST_UICB2 0x00004000
1757#define SDR0_SRST_SRAM 0x00002000
1758#define SDR0_SRST_EBM 0x00001000
1759#define SDR0_SRST_BGI 0x00000800
1760#define SDR0_SRST_DMA 0x00000400
1761#define SDR0_SRST_DMAC 0x00000200
1762#define SDR0_SRST_MAL 0x00000100
1763#define SDR0_SRST_ZMII 0x00000080
1764#define SDR0_SRST_GPTR 0x00000040
1765#define SDR0_SRST_PPM 0x00000020
1766#define SDR0_SRST_EMAC2 0x00000010
1767#define SDR0_SRST_EMAC3 0x00000008
1768#define SDR0_SRST_RGMII 0x00000001
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1769
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1770#endif
1771
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1772/*-----------------------------------------------------------------------------+
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1773| Clocking
1774+-----------------------------------------------------------------------------*/
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]1775#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1776 defined(CONFIG_460SX)
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]1777#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
1778#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
1779#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
1780#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
1781#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
1782#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1783#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
1784#elif !defined (CONFIG_440GX) && \
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1785 !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
1786 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1787 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]1788#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
1789#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
1790#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
1791#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
1792#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
1793#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
1794#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
1795#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
1796#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
1797#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
1798#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
1799#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1800
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]1801#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1802#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1803#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1804#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200[diff] [blame]1805#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]1806#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
1807#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
1808#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
1809#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
1810#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
1811#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
1812#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
1813#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
1814#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
1815
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1816#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
1817#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
1818#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
1819#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
1820#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
1821#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
1822
1823#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
1824#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
1825#define PRADV_MASK 0x07000000 /* Primary Divisor A */
1826#define PRBDV_MASK 0x07000000 /* Primary Divisor B */
1827#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
1828
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]1829#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
1830#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
1831#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
1832#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
1833
1834/* Strap 1 Register */
1835#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
1836#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
1837#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
1838#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
1839#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
1840#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
1841#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
1842#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
1843#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
1844#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
1845#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
1846#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
1847#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
1848#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
1849#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
1850#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
1851#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
1852#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200[diff] [blame]1853#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1854
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1855#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
Stefan Roese26173fc2008-06-30 14:11:07 +0200[diff] [blame]1856#define CPR0_ICFG_RLI_MASK 0x80000000
1857#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
1858#define CPR0_PERD_PERDV0_MASK 0x07000000
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1859#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1860
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1861/*-----------------------------------------------------------------------------
1862| IIC Register Offsets
1863'----------------------------------------------------------------------------*/
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1864#define IICMDBUF 0x00
1865#define IICSDBUF 0x02
1866#define IICLMADR 0x04
1867#define IICHMADR 0x05
1868#define IICCNTL 0x06
1869#define IICMDCNTL 0x07
1870#define IICSTS 0x08
1871#define IICEXTSTS 0x09
1872#define IICLSADR 0x0A
1873#define IICHSADR 0x0B
1874#define IICCLKDIV 0x0C
1875#define IICINTRMSK 0x0D
1876#define IICXFRCNT 0x0E
1877#define IICXTCNTLSS 0x0F
1878#define IICDIRECTCNTL 0x10
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1879
1880/*-----------------------------------------------------------------------------
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1881| PCI Internal Registers et. al. (accessed via plb)
1882+----------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1883#define PCIX0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
1884#define PCIX0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
1885#define PCIX0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
1886#define PCIX0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1887
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1888#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1889 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1890
1891/* PCI Local Configuration Registers
1892 --------------------------------- */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1893#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1894
1895/* PCI Master Local Configuration Registers */
1896#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
1897#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
1898#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
1899#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
1900#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
1901#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
1902#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
1903#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
1904#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
1905#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
1906#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
1907#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
1908
1909/* PCI Target Local Configuration Registers */
1910#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
1911#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
1912#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
1913#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
1914
1915#else
1916
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1917#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
1918#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
1919#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
1920#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
1921#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
1922#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
1923#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
1924#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
1925#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
1926#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
1927#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
1928#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
1929#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
1930#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
1931#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
1932#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
1933#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
1934#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
1935#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
1936#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
1937#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
1938#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
1939#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
1940#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
1941#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
1942#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
1943#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
1944#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1945
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1946#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
1947#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1948
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1949#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
1950#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
1951#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1952#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
1953#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1954#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
1955#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
1956#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
wdenk63153492005-04-03 20:55:38 +0000[diff] [blame]1957#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
1958#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1959#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1960
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1961#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
1962#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
1963#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
1964#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
1965#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
1966#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
1967#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
1968#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
1969#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1970
wdenk0e6d7982004-03-14 00:07:33 +0000[diff] [blame]1971#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]1972
Stefan Roese846b0dd2005-08-08 12:42:22 +0200[diff] [blame]1973#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]1974
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1975#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1976
1977/* USB2.0 Device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]1978#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]1979
1980#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
1981
1982#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
1983#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
1984#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
1985#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
1986#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
1987#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
1988#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
1989#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
1990#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
1991#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
1992#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
1993#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
1994#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
1995#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
1996#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
1997#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
1998#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
1999#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
2000#endif
2001
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]2002/******************************************************************************
2003 * GPIO macro register defines
2004 ******************************************************************************/
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100[diff] [blame]2005#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
Feng Kan96e5fc02008-07-08 22:48:07 -0700[diff] [blame]2006 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2007 defined(CONFIG_460SX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]2008#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700)
Stefan Roesea4c8d132006-06-02 16:18:04 +0200[diff] [blame]2009
2010#define GPIO0_OR (GPIO0_BASE+0x0)
2011#define GPIO0_TCR (GPIO0_BASE+0x4)
2012#define GPIO0_ODR (GPIO0_BASE+0x18)
2013#define GPIO0_IR (GPIO0_BASE+0x1C)
Stefan Roese5568e612005-11-22 13:20:42 +0100[diff] [blame]2014#endif /* CONFIG_440GP */
2015
Stefan Roese887e2ec2006-09-07 11:51:23 +0200[diff] [blame]2016#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese43c60992008-03-11 15:11:43 +0100[diff] [blame]2017 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
2018 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]2019#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00)
2020#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]2021
Stefan Roesea4c8d132006-06-02 16:18:04 +0200[diff] [blame]2022#define GPIO0_OR (GPIO0_BASE+0x0)
2023#define GPIO0_TCR (GPIO0_BASE+0x4)
2024#define GPIO0_OSRL (GPIO0_BASE+0x8)
2025#define GPIO0_OSRH (GPIO0_BASE+0xC)
2026#define GPIO0_TSRL (GPIO0_BASE+0x10)
2027#define GPIO0_TSRH (GPIO0_BASE+0x14)
2028#define GPIO0_ODR (GPIO0_BASE+0x18)
2029#define GPIO0_IR (GPIO0_BASE+0x1C)
2030#define GPIO0_RR1 (GPIO0_BASE+0x20)
2031#define GPIO0_RR2 (GPIO0_BASE+0x24)
2032#define GPIO0_RR3 (GPIO0_BASE+0x28)
2033#define GPIO0_ISR1L (GPIO0_BASE+0x30)
2034#define GPIO0_ISR1H (GPIO0_BASE+0x34)
2035#define GPIO0_ISR2L (GPIO0_BASE+0x38)
2036#define GPIO0_ISR2H (GPIO0_BASE+0x3C)
2037#define GPIO0_ISR3L (GPIO0_BASE+0x40)
2038#define GPIO0_ISR3H (GPIO0_BASE+0x44)
2039
2040#define GPIO1_OR (GPIO1_BASE+0x0)
2041#define GPIO1_TCR (GPIO1_BASE+0x4)
2042#define GPIO1_OSRL (GPIO1_BASE+0x8)
2043#define GPIO1_OSRH (GPIO1_BASE+0xC)
2044#define GPIO1_TSRL (GPIO1_BASE+0x10)
2045#define GPIO1_TSRH (GPIO1_BASE+0x14)
2046#define GPIO1_ODR (GPIO1_BASE+0x18)
2047#define GPIO1_IR (GPIO1_BASE+0x1C)
2048#define GPIO1_RR1 (GPIO1_BASE+0x20)
2049#define GPIO1_RR2 (GPIO1_BASE+0x24)
2050#define GPIO1_RR3 (GPIO1_BASE+0x28)
2051#define GPIO1_ISR1L (GPIO1_BASE+0x30)
2052#define GPIO1_ISR1H (GPIO1_BASE+0x34)
2053#define GPIO1_ISR2L (GPIO1_BASE+0x38)
2054#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
2055#define GPIO1_ISR3L (GPIO1_BASE+0x40)
2056#define GPIO1_ISR3H (GPIO1_BASE+0x44)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200[diff] [blame]2057#endif
2058
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2059#ifndef __ASSEMBLY__
2060
wdenkba56f622004-02-06 23:19:44 +0000[diff] [blame]2061#endif /* _ASMLANGUAGE */
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2062
wdenkc00b5f82002-11-03 11:12:02 +0000[diff] [blame]2063#endif /* __PPC440_H__ */