| Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. |
| 4 | * - only support for S3C6400 |
| 5 | * |
| 6 | * (C) Copyright 2008 |
| 7 | * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | /************************************************ |
| 26 | * NAME : s3c6400.h |
| 27 | * |
| 28 | * Based on S3C6400 User's manual Rev 0.0 |
| 29 | ************************************************/ |
| 30 | |
| 31 | #ifndef __S3C6400_H__ |
| 32 | #define __S3C6400_H__ |
| 33 | |
| 34 | #ifndef CONFIG_S3C6400 |
| 35 | #define CONFIG_S3C6400 1 |
| 36 | #endif |
| 37 | |
| 38 | #define S3C64XX_UART_CHANNELS 3 |
| 39 | #define S3C64XX_SPI_CHANNELS 2 |
| 40 | |
| 41 | #include <asm/hardware.h> |
| 42 | |
| 43 | #define ELFIN_CLOCK_POWER_BASE 0x7e00f000 |
| 44 | |
| 45 | /* Clock & Power Controller for mDirac3*/ |
| 46 | #define APLL_LOCK_OFFSET 0x00 |
| 47 | #define MPLL_LOCK_OFFSET 0x04 |
| 48 | #define EPLL_LOCK_OFFSET 0x08 |
| 49 | #define APLL_CON_OFFSET 0x0C |
| 50 | #define MPLL_CON_OFFSET 0x10 |
| 51 | #define EPLL_CON0_OFFSET 0x14 |
| 52 | #define EPLL_CON1_OFFSET 0x18 |
| 53 | #define CLK_SRC_OFFSET 0x1C |
| 54 | #define CLK_DIV0_OFFSET 0x20 |
| 55 | #define CLK_DIV1_OFFSET 0x24 |
| 56 | #define CLK_DIV2_OFFSET 0x28 |
| 57 | #define CLK_OUT_OFFSET 0x2C |
| 58 | #define HCLK_GATE_OFFSET 0x30 |
| 59 | #define PCLK_GATE_OFFSET 0x34 |
| 60 | #define SCLK_GATE_OFFSET 0x38 |
| 61 | #define AHB_CON0_OFFSET 0x100 |
| 62 | #define AHB_CON1_OFFSET 0x104 |
| 63 | #define AHB_CON2_OFFSET 0x108 |
| 64 | #define SELECT_DMA_OFFSET 0x110 |
| 65 | #define SW_RST_OFFSET 0x114 |
| 66 | #define SYS_ID_OFFSET 0x118 |
| 67 | #define MEM_SYS_CFG_OFFSET 0x120 |
| 68 | #define QOS_OVERRIDE0_OFFSET 0x124 |
| 69 | #define QOS_OVERRIDE1_OFFSET 0x128 |
| 70 | #define MEM_CFG_STAT_OFFSET 0x12C |
| 71 | #define PWR_CFG_OFFSET 0x804 |
| 72 | #define EINT_MASK_OFFSET 0x808 |
| 73 | #define NOR_CFG_OFFSET 0x810 |
| 74 | #define STOP_CFG_OFFSET 0x814 |
| 75 | #define SLEEP_CFG_OFFSET 0x818 |
| 76 | #define OSC_FREQ_OFFSET 0x820 |
| 77 | #define OSC_STABLE_OFFSET 0x824 |
| 78 | #define PWR_STABLE_OFFSET 0x828 |
| 79 | #define FPC_STABLE_OFFSET 0x82C |
| 80 | #define MTC_STABLE_OFFSET 0x830 |
| 81 | #define OTHERS_OFFSET 0x900 |
| 82 | #define RST_STAT_OFFSET 0x904 |
| 83 | #define WAKEUP_STAT_OFFSET 0x908 |
| 84 | #define BLK_PWR_STAT_OFFSET 0x90C |
| 85 | #define INF_REG0_OFFSET 0xA00 |
| 86 | #define INF_REG1_OFFSET 0xA04 |
| 87 | #define INF_REG2_OFFSET 0xA08 |
| 88 | #define INF_REG3_OFFSET 0xA0C |
| 89 | #define INF_REG4_OFFSET 0xA10 |
| 90 | #define INF_REG5_OFFSET 0xA14 |
| 91 | #define INF_REG6_OFFSET 0xA18 |
| 92 | #define INF_REG7_OFFSET 0xA1C |
| 93 | |
| 94 | #define OSC_CNT_VAL_OFFSET 0x824 |
| 95 | #define PWR_CNT_VAL_OFFSET 0x828 |
| 96 | #define FPC_CNT_VAL_OFFSET 0x82C |
| 97 | #define MTC_CNT_VAL_OFFSET 0x830 |
| 98 | |
| 99 | #define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) |
| 100 | #define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) |
| 101 | #define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) |
| 102 | #define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) |
| 103 | #define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) |
| 104 | #define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) |
| 105 | #define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) |
| 106 | #define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) |
| 107 | #define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) |
| 108 | #define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) |
| 109 | #define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) |
| 110 | #define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) |
| 111 | #define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) |
| 112 | #define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) |
| 113 | #define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) |
| 114 | #define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) |
| 115 | #define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) |
| 116 | #define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) |
| 117 | #define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 118 | SELECT_DMA_OFFSET) |
| 119 | #define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) |
| 120 | #define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) |
| 121 | #define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 122 | MEM_SYS_CFG_OFFSET) |
| 123 | #define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 124 | QOS_OVERRIDE0_OFFSET) |
| 125 | #define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 126 | QOS_OVERRIDE1_OFFSET) |
| 127 | #define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 128 | MEM_CFG_STAT_OFFSET) |
| 129 | #define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) |
| 130 | #define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) |
| 131 | #define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) |
| 132 | #define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) |
| 133 | #define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) |
| 134 | #define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) |
| 135 | #define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 136 | OSC_CNT_VAL_OFFSET) |
| 137 | #define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 138 | PWR_CNT_VAL_OFFSET) |
| 139 | #define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 140 | FPC_CNT_VAL_OFFSET) |
| 141 | #define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 142 | MTC_CNT_VAL_OFFSET) |
| 143 | #define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) |
| 144 | #define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) |
| 145 | #define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 146 | WAKEUP_STAT_OFFSET) |
| 147 | #define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ |
| 148 | BLK_PWR_STAT_OFFSET) |
| 149 | #define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) |
| 150 | #define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) |
| 151 | #define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) |
| 152 | #define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) |
| 153 | #define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) |
| 154 | #define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) |
| 155 | #define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) |
| 156 | #define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) |
| 157 | |
| 158 | #define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) |
| 159 | #define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) |
| 160 | #define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) |
| 161 | #define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) |
| 162 | #define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) |
| 163 | #define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) |
| 164 | #define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) |
| 165 | #define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) |
| 166 | #define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) |
| 167 | #define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) |
| 168 | #define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) |
| 169 | #define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) |
| 170 | #define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) |
| 171 | #define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) |
| 172 | #define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) |
| 173 | #define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) |
| 174 | #define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) |
| 175 | #define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) |
| 176 | #define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) |
| 177 | #define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) |
| 178 | #define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) |
| 179 | #define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) |
| 180 | #define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) |
| 181 | #define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) |
| 182 | #define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) |
| 183 | #define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) |
| 184 | #define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) |
| 185 | #define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) |
| 186 | #define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) |
| 187 | #define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) |
| 188 | #define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) |
| 189 | #define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) |
| 190 | #define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) |
| 191 | #define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) |
| 192 | #define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) |
| 193 | #define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) |
| 194 | #define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) |
| 195 | #define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) |
| 196 | #define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) |
| 197 | #define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) |
| 198 | #define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) |
| 199 | #define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) |
| 200 | #define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) |
| 201 | #define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) |
| 202 | #define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) |
| 203 | #define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) |
| 204 | #define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) |
| 205 | |
| 206 | |
| 207 | /* |
| 208 | * GPIO |
| 209 | */ |
| 210 | #define ELFIN_GPIO_BASE 0x7f008000 |
| 211 | |
| 212 | #define GPACON_OFFSET 0x00 |
| 213 | #define GPADAT_OFFSET 0x04 |
| 214 | #define GPAPUD_OFFSET 0x08 |
| 215 | #define GPACONSLP_OFFSET 0x0C |
| 216 | #define GPAPUDSLP_OFFSET 0x10 |
| 217 | #define GPBCON_OFFSET 0x20 |
| Minkyu Kang | 342c1a5 | 2009-04-03 09:56:16 +0900 | [diff] [blame] | 218 | #define GPBDAT_OFFSET 0x24 |
| 219 | #define GPBPUD_OFFSET 0x28 |
| 220 | #define GPBCONSLP_OFFSET 0x2C |
| Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 221 | #define GPBPUDSLP_OFFSET 0x30 |
| 222 | #define GPCCON_OFFSET 0x40 |
| 223 | #define GPCDAT_OFFSET 0x44 |
| 224 | #define GPCPUD_OFFSET 0x48 |
| 225 | #define GPCCONSLP_OFFSET 0x4C |
| 226 | #define GPCPUDSLP_OFFSET 0x50 |
| 227 | #define GPDCON_OFFSET 0x60 |
| 228 | #define GPDDAT_OFFSET 0x64 |
| 229 | #define GPDPUD_OFFSET 0x68 |
| 230 | #define GPDCONSLP_OFFSET 0x6C |
| 231 | #define GPDPUDSLP_OFFSET 0x70 |
| 232 | #define GPECON_OFFSET 0x80 |
| 233 | #define GPEDAT_OFFSET 0x84 |
| 234 | #define GPEPUD_OFFSET 0x88 |
| 235 | #define GPECONSLP_OFFSET 0x8C |
| 236 | #define GPEPUDSLP_OFFSET 0x90 |
| 237 | #define GPFCON_OFFSET 0xA0 |
| 238 | #define GPFDAT_OFFSET 0xA4 |
| 239 | #define GPFPUD_OFFSET 0xA8 |
| 240 | #define GPFCONSLP_OFFSET 0xAC |
| 241 | #define GPFPUDSLP_OFFSET 0xB0 |
| 242 | #define GPGCON_OFFSET 0xC0 |
| 243 | #define GPGDAT_OFFSET 0xC4 |
| 244 | #define GPGPUD_OFFSET 0xC8 |
| 245 | #define GPGCONSLP_OFFSET 0xCC |
| 246 | #define GPGPUDSLP_OFFSET 0xD0 |
| 247 | #define GPHCON0_OFFSET 0xE0 |
| 248 | #define GPHCON1_OFFSET 0xE4 |
| 249 | #define GPHDAT_OFFSET 0xE8 |
| 250 | #define GPHPUD_OFFSET 0xEC |
| 251 | #define GPHCONSLP_OFFSET 0xF0 |
| 252 | #define GPHPUDSLP_OFFSET 0xF4 |
| 253 | #define GPICON_OFFSET 0x100 |
| 254 | #define GPIDAT_OFFSET 0x104 |
| 255 | #define GPIPUD_OFFSET 0x108 |
| 256 | #define GPICONSLP_OFFSET 0x10C |
| 257 | #define GPIPUDSLP_OFFSET 0x110 |
| 258 | #define GPJCON_OFFSET 0x120 |
| 259 | #define GPJDAT_OFFSET 0x124 |
| 260 | #define GPJPUD_OFFSET 0x128 |
| 261 | #define GPJCONSLP_OFFSET 0x12C |
| 262 | #define GPJPUDSLP_OFFSET 0x130 |
| 263 | #define MEM0DRVCON_OFFSET 0x1D0 |
| 264 | #define MEM1DRVCON_OFFSET 0x1D4 |
| 265 | #define GPKCON0_OFFSET 0x800 |
| 266 | #define GPKCON1_OFFSET 0x804 |
| 267 | #define GPKDAT_OFFSET 0x808 |
| 268 | #define GPKPUD_OFFSET 0x80C |
| 269 | #define GPLCON0_OFFSET 0x810 |
| 270 | #define GPLCON1_OFFSET 0x814 |
| 271 | #define GPLDAT_OFFSET 0x818 |
| 272 | #define GPLPUD_OFFSET 0x81C |
| 273 | #define GPMCON_OFFSET 0x820 |
| 274 | #define GPMDAT_OFFSET 0x824 |
| 275 | #define GPMPUD_OFFSET 0x828 |
| 276 | #define GPNCON_OFFSET 0x830 |
| 277 | #define GPNDAT_OFFSET 0x834 |
| 278 | #define GPNPUD_OFFSET 0x838 |
| 279 | #define GPOCON_OFFSET 0x140 |
| 280 | #define GPODAT_OFFSET 0x144 |
| 281 | #define GPOPUD_OFFSET 0x148 |
| 282 | #define GPOCONSLP_OFFSET 0x14C |
| 283 | #define GPOPUDSLP_OFFSET 0x150 |
| 284 | #define GPPCON_OFFSET 0x160 |
| 285 | #define GPPDAT_OFFSET 0x164 |
| 286 | #define GPPPUD_OFFSET 0x168 |
| 287 | #define GPPCONSLP_OFFSET 0x16C |
| 288 | #define GPPPUDSLP_OFFSET 0x170 |
| 289 | #define GPQCON_OFFSET 0x180 |
| 290 | #define GPQDAT_OFFSET 0x184 |
| 291 | #define GPQPUD_OFFSET 0x188 |
| 292 | #define GPQCONSLP_OFFSET 0x18C |
| 293 | #define GPQPUDSLP_OFFSET 0x190 |
| 294 | |
| 295 | #define EINTPEND_OFFSET 0x924 |
| 296 | |
| 297 | #define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) |
| 298 | #define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) |
| 299 | #define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) |
| 300 | #define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) |
| 301 | #define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) |
| 302 | #define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) |
| 303 | #define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) |
| 304 | #define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) |
| 305 | #define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) |
| 306 | #define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) |
| 307 | #define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) |
| 308 | #define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) |
| 309 | #define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) |
| 310 | #define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) |
| 311 | #define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) |
| 312 | #define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) |
| 313 | #define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) |
| 314 | #define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) |
| 315 | #define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) |
| 316 | #define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) |
| 317 | #define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) |
| 318 | #define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) |
| 319 | #define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) |
| 320 | #define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) |
| 321 | #define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) |
| 322 | #define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) |
| 323 | #define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) |
| 324 | #define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) |
| 325 | #define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) |
| 326 | #define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) |
| 327 | #define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) |
| 328 | #define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) |
| 329 | #define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) |
| 330 | #define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) |
| 331 | #define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) |
| 332 | #define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) |
| 333 | #define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) |
| 334 | #define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) |
| 335 | #define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) |
| 336 | #define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) |
| 337 | #define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) |
| 338 | #define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) |
| 339 | #define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) |
| 340 | #define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) |
| 341 | #define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) |
| 342 | #define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) |
| 343 | #define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) |
| 344 | #define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) |
| 345 | #define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) |
| 346 | #define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) |
| 347 | #define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) |
| 348 | #define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) |
| 349 | #define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) |
| 350 | #define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) |
| 351 | #define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) |
| 352 | #define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) |
| 353 | #define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) |
| 354 | #define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) |
| 355 | #define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) |
| 356 | #define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) |
| 357 | #define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) |
| 358 | #define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) |
| 359 | #define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) |
| 360 | #define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) |
| 361 | #define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) |
| 362 | #define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) |
| 363 | #define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) |
| 364 | #define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) |
| 365 | #define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) |
| 366 | #define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) |
| 367 | #define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) |
| 368 | #define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) |
| 369 | #define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) |
| 370 | #define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) |
| 371 | #define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) |
| 372 | #define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) |
| 373 | #define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) |
| 374 | #define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) |
| 375 | #define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) |
| 376 | #define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) |
| 377 | |
| 378 | /* |
| 379 | * Bus Matrix |
| 380 | */ |
| 381 | #define ELFIN_MEM_SYS_CFG 0x7e00f120 |
| 382 | |
| Kyungmin Park | ab0689c | 2008-11-26 10:18:13 +0900 | [diff] [blame] | 383 | #define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) |
| 384 | |
| 385 | #define S3C64XX_MEM_SYS_CFG_NAND 0x0008 |
| 386 | #define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT |
| 387 | |
| Guennadi Liakhovetski | 9b07773 | 2008-08-31 00:39:46 +0200 | [diff] [blame] | 388 | #define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) |
| 389 | #define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) |
| 390 | #define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) |
| 391 | #define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) |
| 392 | #define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) |
| 393 | #define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) |
| 394 | #define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) |
| 395 | #define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) |
| 396 | #define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) |
| 397 | #define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) |
| 398 | #define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) |
| 399 | #define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) |
| 400 | #define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) |
| 401 | #define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) |
| 402 | #define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) |
| 403 | #define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) |
| 404 | #define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) |
| 405 | #define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) |
| 406 | #define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) |
| 407 | #define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) |
| 408 | #define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) |
| 409 | #define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) |
| 410 | #define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) |
| 411 | #define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) |
| 412 | #define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) |
| 413 | #define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) |
| 414 | #define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) |
| 415 | #define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) |
| 416 | #define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) |
| 417 | #define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) |
| 418 | #define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) |
| 419 | #define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) |
| 420 | #define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) |
| 421 | #define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) |
| 422 | #define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) |
| 423 | #define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) |
| 424 | #define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) |
| 425 | #define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) |
| 426 | #define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) |
| 427 | #define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) |
| 428 | #define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) |
| 429 | #define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) |
| 430 | #define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) |
| 431 | #define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) |
| 432 | #define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) |
| 433 | #define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) |
| 434 | #define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) |
| 435 | #define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) |
| 436 | #define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) |
| 437 | #define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) |
| 438 | #define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) |
| 439 | #define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) |
| 440 | #define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) |
| 441 | #define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) |
| 442 | #define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) |
| 443 | #define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) |
| 444 | #define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) |
| 445 | #define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) |
| 446 | #define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) |
| 447 | #define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) |
| 448 | #define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) |
| 449 | #define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) |
| 450 | #define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) |
| 451 | #define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) |
| 452 | #define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) |
| 453 | #define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) |
| 454 | #define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) |
| 455 | #define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) |
| 456 | #define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) |
| 457 | #define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) |
| 458 | #define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) |
| 459 | #define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) |
| 460 | #define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) |
| 461 | #define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) |
| 462 | #define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) |
| 463 | #define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) |
| 464 | #define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) |
| 465 | #define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) |
| 466 | #define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) |
| 467 | #define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) |
| 468 | |
| 469 | /* |
| 470 | * Memory controller |
| 471 | */ |
| 472 | #define ELFIN_SROM_BASE 0x70000000 |
| 473 | |
| 474 | #define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) |
| 475 | #define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) |
| 476 | #define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) |
| 477 | #define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) |
| 478 | #define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) |
| 479 | #define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) |
| 480 | #define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) |
| 481 | |
| 482 | /* |
| 483 | * SDRAM Controller |
| 484 | */ |
| 485 | #define ELFIN_DMC0_BASE 0x7e000000 |
| 486 | #define ELFIN_DMC1_BASE 0x7e001000 |
| 487 | |
| 488 | #define INDEX_DMC_MEMC_STATUS 0x00 |
| 489 | #define INDEX_DMC_MEMC_CMD 0x04 |
| 490 | #define INDEX_DMC_DIRECT_CMD 0x08 |
| 491 | #define INDEX_DMC_MEMORY_CFG 0x0C |
| 492 | #define INDEX_DMC_REFRESH_PRD 0x10 |
| 493 | #define INDEX_DMC_CAS_LATENCY 0x14 |
| 494 | #define INDEX_DMC_T_DQSS 0x18 |
| 495 | #define INDEX_DMC_T_MRD 0x1C |
| 496 | #define INDEX_DMC_T_RAS 0x20 |
| 497 | #define INDEX_DMC_T_RC 0x24 |
| 498 | #define INDEX_DMC_T_RCD 0x28 |
| 499 | #define INDEX_DMC_T_RFC 0x2C |
| 500 | #define INDEX_DMC_T_RP 0x30 |
| 501 | #define INDEX_DMC_T_RRD 0x34 |
| 502 | #define INDEX_DMC_T_WR 0x38 |
| 503 | #define INDEX_DMC_T_WTR 0x3C |
| 504 | #define INDEX_DMC_T_XP 0x40 |
| 505 | #define INDEX_DMC_T_XSR 0x44 |
| 506 | #define INDEX_DMC_T_ESR 0x48 |
| 507 | #define INDEX_DMC_MEMORY_CFG2 0x4C |
| 508 | #define INDEX_DMC_CHIP_0_CFG 0x200 |
| 509 | #define INDEX_DMC_CHIP_1_CFG 0x204 |
| 510 | #define INDEX_DMC_CHIP_2_CFG 0x208 |
| 511 | #define INDEX_DMC_CHIP_3_CFG 0x20C |
| 512 | #define INDEX_DMC_USER_STATUS 0x300 |
| 513 | #define INDEX_DMC_USER_CONFIG 0x304 |
| 514 | |
| 515 | /* |
| 516 | * Memory Chip direct command |
| 517 | */ |
| 518 | #define DMC_NOP0 0x0c0000 |
| 519 | #define DMC_NOP1 0x1c0000 |
| 520 | #define DMC_PA0 0x000000 /* Precharge all */ |
| 521 | #define DMC_PA1 0x100000 |
| 522 | #define DMC_AR0 0x040000 /* Autorefresh */ |
| 523 | #define DMC_AR1 0x140000 |
| 524 | #define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ |
| 525 | #define DMC_SDR_MR1 0x180032 |
| 526 | #define DMC_DDR_MR0 0x080162 |
| 527 | #define DMC_DDR_MR1 0x180162 |
| 528 | #define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ |
| 529 | #define DMC_mDDR_MR1 0x180032 |
| 530 | #define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ |
| 531 | #define DMC_mSDR_EMR1 0x1a0000 |
| 532 | #define DMC_DDR_EMR0 0x090000 |
| 533 | #define DMC_DDR_EMR1 0x190000 |
| 534 | #define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ |
| 535 | #define DMC_mDDR_EMR1 0x1a0000 |
| 536 | |
| 537 | /* |
| 538 | * Definitions for memory configuration |
| 539 | * Set memory configuration |
| 540 | * active_chips = 1'b0 (1 chip) |
| 541 | * qos_master_chip = 3'b000(ARID[3:0]) |
| 542 | * memory burst = 3'b010(burst 4) |
| 543 | * stop_mem_clock = 1'b0(disable dynamical stop) |
| 544 | * auto_power_down = 1'b0(disable auto power-down mode) |
| 545 | * power_down_prd = 6'b00_0000(0 cycle for auto power-down) |
| 546 | * ap_bit = 1'b0 (bit position of auto-precharge is 10) |
| 547 | * row_bits = 3'b010(# row address 13) |
| 548 | * column_bits = 3'b010(# column address 10 ) |
| 549 | * |
| 550 | * Set user configuration |
| 551 | * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR |
| 552 | * |
| 553 | * Set chip select for chip [n] |
| 554 | * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff |
| 555 | * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] |
| 556 | */ |
| 557 | |
| 558 | /* |
| 559 | * Nand flash controller |
| 560 | */ |
| 561 | #define ELFIN_NAND_BASE 0x70200000 |
| 562 | |
| 563 | #define NFCONF_OFFSET 0x00 |
| 564 | #define NFCONT_OFFSET 0x04 |
| 565 | #define NFCMMD_OFFSET 0x08 |
| 566 | #define NFADDR_OFFSET 0x0c |
| 567 | #define NFDATA_OFFSET 0x10 |
| 568 | #define NFMECCDATA0_OFFSET 0x14 |
| 569 | #define NFMECCDATA1_OFFSET 0x18 |
| 570 | #define NFSECCDATA0_OFFSET 0x1c |
| 571 | #define NFSBLK_OFFSET 0x20 |
| 572 | #define NFEBLK_OFFSET 0x24 |
| 573 | #define NFSTAT_OFFSET 0x28 |
| 574 | #define NFESTAT0_OFFSET 0x2c |
| 575 | #define NFESTAT1_OFFSET 0x30 |
| 576 | #define NFMECC0_OFFSET 0x34 |
| 577 | #define NFMECC1_OFFSET 0x38 |
| 578 | #define NFSECC_OFFSET 0x3c |
| 579 | #define NFMLCBITPT_OFFSET 0x40 |
| 580 | |
| 581 | #define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) |
| 582 | #define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) |
| 583 | #define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) |
| 584 | #define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) |
| 585 | #define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) |
| 586 | #define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) |
| 587 | #define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) |
| 588 | #define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) |
| 589 | #define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) |
| 590 | #define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) |
| 591 | #define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) |
| 592 | #define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) |
| 593 | #define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) |
| 594 | #define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) |
| 595 | #define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) |
| 596 | #define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) |
| 597 | #define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) |
| 598 | |
| 599 | #define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) |
| 600 | #define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) |
| 601 | #define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) |
| 602 | #define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) |
| 603 | #define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) |
| 604 | #define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) |
| 605 | #define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) |
| 606 | #define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) |
| 607 | #define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) |
| 608 | #define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) |
| 609 | #define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) |
| 610 | #define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) |
| 611 | #define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) |
| 612 | #define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) |
| 613 | #define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) |
| 614 | #define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) |
| 615 | #define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) |
| 616 | #define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) |
| 617 | |
| 618 | #define NFCONF_ECC_4BIT (1<<24) |
| 619 | |
| 620 | #define NFCONT_ECC_ENC (1<<18) |
| 621 | #define NFCONT_WP (1<<16) |
| 622 | #define NFCONT_MECCLOCK (1<<7) |
| 623 | #define NFCONT_SECCLOCK (1<<6) |
| 624 | #define NFCONT_INITMECC (1<<5) |
| 625 | #define NFCONT_INITSECC (1<<4) |
| 626 | #define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) |
| 627 | #define NFCONT_CS_ALT (1<<2) |
| 628 | #define NFCONT_CS (1<<1) |
| 629 | #define NFCONT_ENABLE (1<<0) |
| 630 | |
| 631 | #define NFSTAT_ECCENCDONE (1<<7) |
| 632 | #define NFSTAT_ECCDECDONE (1<<6) |
| 633 | #define NFSTAT_RnB (1<<0) |
| 634 | |
| 635 | #define NFESTAT0_ECCBUSY (1<<31) |
| 636 | |
| 637 | /* |
| 638 | * Interrupt |
| 639 | */ |
| 640 | #define ELFIN_VIC0_BASE_ADDR 0x71200000 |
| 641 | #define ELFIN_VIC1_BASE_ADDR 0x71300000 |
| 642 | #define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ |
| 643 | #define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ |
| 644 | #define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ |
| 645 | #define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ |
| 646 | #define oVECTADDR 0xF00 /* VIC ADDRESS */ |
| 647 | |
| 648 | /* |
| 649 | * Watchdog timer |
| 650 | */ |
| 651 | #define ELFIN_WATCHDOG_BASE 0x7E004000 |
| 652 | |
| 653 | #define WTCON_REG __REG(0x7E004004) |
| 654 | #define WTDAT_REG __REG(0x7E004008) |
| 655 | #define WTCNT_REG __REG(0x7E00400C) |
| 656 | |
| 657 | |
| 658 | /* |
| 659 | * UART |
| 660 | */ |
| 661 | #define ELFIN_UART_BASE 0x7F005000 |
| 662 | |
| 663 | #define ELFIN_UART0_OFFSET 0x0000 |
| 664 | #define ELFIN_UART1_OFFSET 0x0400 |
| 665 | #define ELFIN_UART2_OFFSET 0x0800 |
| 666 | |
| 667 | #define ULCON_OFFSET 0x00 |
| 668 | #define UCON_OFFSET 0x04 |
| 669 | #define UFCON_OFFSET 0x08 |
| 670 | #define UMCON_OFFSET 0x0C |
| 671 | #define UTRSTAT_OFFSET 0x10 |
| 672 | #define UERSTAT_OFFSET 0x14 |
| 673 | #define UFSTAT_OFFSET 0x18 |
| 674 | #define UMSTAT_OFFSET 0x1C |
| 675 | #define UTXH_OFFSET 0x20 |
| 676 | #define URXH_OFFSET 0x24 |
| 677 | #define UBRDIV_OFFSET 0x28 |
| 678 | #define UDIVSLOT_OFFSET 0x2C |
| 679 | #define UINTP_OFFSET 0x30 |
| 680 | #define UINTSP_OFFSET 0x34 |
| 681 | #define UINTM_OFFSET 0x38 |
| 682 | |
| 683 | #define ULCON0_REG __REG(0x7F005000) |
| 684 | #define UCON0_REG __REG(0x7F005004) |
| 685 | #define UFCON0_REG __REG(0x7F005008) |
| 686 | #define UMCON0_REG __REG(0x7F00500C) |
| 687 | #define UTRSTAT0_REG __REG(0x7F005010) |
| 688 | #define UERSTAT0_REG __REG(0x7F005014) |
| 689 | #define UFSTAT0_REG __REG(0x7F005018) |
| 690 | #define UMSTAT0_REG __REG(0x7F00501c) |
| 691 | #define UTXH0_REG __REG(0x7F005020) |
| 692 | #define URXH0_REG __REG(0x7F005024) |
| 693 | #define UBRDIV0_REG __REG(0x7F005028) |
| 694 | #define UDIVSLOT0_REG __REG(0x7F00502c) |
| 695 | #define UINTP0_REG __REG(0x7F005030) |
| 696 | #define UINTSP0_REG __REG(0x7F005034) |
| 697 | #define UINTM0_REG __REG(0x7F005038) |
| 698 | |
| 699 | #define ULCON1_REG __REG(0x7F005400) |
| 700 | #define UCON1_REG __REG(0x7F005404) |
| 701 | #define UFCON1_REG __REG(0x7F005408) |
| 702 | #define UMCON1_REG __REG(0x7F00540C) |
| 703 | #define UTRSTAT1_REG __REG(0x7F005410) |
| 704 | #define UERSTAT1_REG __REG(0x7F005414) |
| 705 | #define UFSTAT1_REG __REG(0x7F005418) |
| 706 | #define UMSTAT1_REG __REG(0x7F00541c) |
| 707 | #define UTXH1_REG __REG(0x7F005420) |
| 708 | #define URXH1_REG __REG(0x7F005424) |
| 709 | #define UBRDIV1_REG __REG(0x7F005428) |
| 710 | #define UDIVSLOT1_REG __REG(0x7F00542c) |
| 711 | #define UINTP1_REG __REG(0x7F005430) |
| 712 | #define UINTSP1_REG __REG(0x7F005434) |
| 713 | #define UINTM1_REG __REG(0x7F005438) |
| 714 | |
| 715 | #define UTRSTAT_TX_EMPTY (1 << 2) |
| 716 | #define UTRSTAT_RX_READY (1 << 0) |
| 717 | #define UART_ERR_MASK 0xF |
| 718 | |
| 719 | /* |
| 720 | * PWM timer |
| 721 | */ |
| 722 | #define ELFIN_TIMER_BASE 0x7F006000 |
| 723 | |
| 724 | #define TCFG0_REG __REG(0x7F006000) |
| 725 | #define TCFG1_REG __REG(0x7F006004) |
| 726 | #define TCON_REG __REG(0x7F006008) |
| 727 | #define TCNTB0_REG __REG(0x7F00600c) |
| 728 | #define TCMPB0_REG __REG(0x7F006010) |
| 729 | #define TCNTO0_REG __REG(0x7F006014) |
| 730 | #define TCNTB1_REG __REG(0x7F006018) |
| 731 | #define TCMPB1_REG __REG(0x7F00601c) |
| 732 | #define TCNTO1_REG __REG(0x7F006020) |
| 733 | #define TCNTB2_REG __REG(0x7F006024) |
| 734 | #define TCMPB2_REG __REG(0x7F006028) |
| 735 | #define TCNTO2_REG __REG(0x7F00602c) |
| 736 | #define TCNTB3_REG __REG(0x7F006030) |
| 737 | #define TCMPB3_REG __REG(0x7F006034) |
| 738 | #define TCNTO3_REG __REG(0x7F006038) |
| 739 | #define TCNTB4_REG __REG(0x7F00603c) |
| 740 | #define TCNTO4_REG __REG(0x7F006040) |
| 741 | |
| 742 | /* Fields */ |
| 743 | #define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ |
| 744 | #define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ |
| 745 | #define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ |
| 746 | #define fTCFG1_MUX4 Fld(4, 16) |
| 747 | /* bits */ |
| 748 | #define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) |
| 749 | #define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) |
| 750 | #define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) |
| 751 | #define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ |
| 752 | #define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ |
| 753 | #define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ |
| 754 | #define COUNT_4_ON (TCON_4_ONOFF * 1) |
| 755 | #define COUNT_4_OFF (TCON_4_ONOFF * 0) |
| 756 | #define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ |
| 757 | #define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) |
| 758 | #define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) |
| 759 | #define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ |
| 760 | #define TIMER3_IVT_ON (TCON_3_INVERT * 1) |
| 761 | #define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) |
| 762 | #define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ |
| 763 | #define TIMER3_MANUP (TCON_3_MAN*1) |
| 764 | #define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) |
| 765 | #define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ |
| 766 | #define TIMER3_ON (TCON_3_ONOFF * 1) |
| 767 | #define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) |
| 768 | |
| 769 | #if defined(CONFIG_CLK_400_100_50) |
| 770 | #define STARTUP_AMDIV 400 |
| 771 | #define STARTUP_MDIV 400 |
| 772 | #define STARTUP_PDIV 6 |
| 773 | #define STARTUP_SDIV 1 |
| 774 | #elif defined(CONFIG_CLK_400_133_66) |
| 775 | #define STARTUP_AMDIV 400 |
| 776 | #define STARTUP_MDIV 533 |
| 777 | #define STARTUP_PDIV 6 |
| 778 | #define STARTUP_SDIV 1 |
| 779 | #elif defined(CONFIG_CLK_533_133_66) |
| 780 | #define STARTUP_AMDIV 533 |
| 781 | #define STARTUP_MDIV 533 |
| 782 | #define STARTUP_PDIV 6 |
| 783 | #define STARTUP_SDIV 1 |
| 784 | #elif defined(CONFIG_CLK_667_133_66) |
| 785 | #define STARTUP_AMDIV 667 |
| 786 | #define STARTUP_MDIV 533 |
| 787 | #define STARTUP_PDIV 6 |
| 788 | #define STARTUP_SDIV 1 |
| 789 | #endif |
| 790 | |
| 791 | #define STARTUP_PCLKDIV 3 |
| 792 | #define STARTUP_HCLKX2DIV 1 |
| 793 | #define STARTUP_HCLKDIV 1 |
| 794 | #define STARTUP_MPLLDIV 1 |
| 795 | #define STARTUP_APLLDIV 0 |
| 796 | |
| 797 | #define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ |
| 798 | (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) |
| 799 | #define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ |
| 800 | (STARTUP_PDIV << 8) | STARTUP_SDIV) |
| 801 | #define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ |
| 802 | STARTUP_PDIV) * STARTUP_MDIV) |
| 803 | |
| 804 | #if defined(CONFIG_SYNC_MODE) |
| 805 | #define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ |
| 806 | (STARTUP_PDIV << 8) | STARTUP_SDIV) |
| 807 | #define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ |
| 808 | STARTUP_PDIV) * STARTUP_MDIV) |
| 809 | #define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ |
| 810 | (STARTUP_HCLKDIV + 1)) |
| 811 | #else |
| 812 | #define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ |
| 813 | (STARTUP_PDIV << 8) | STARTUP_SDIV) |
| 814 | #define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ |
| 815 | STARTUP_PDIV) * STARTUP_AMDIV) |
| 816 | #define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ |
| 817 | (STARTUP_HCLKDIV + 1)) |
| 818 | #endif |
| 819 | |
| 820 | |
| 821 | /*----------------------------------------------------------------------- |
| 822 | * Physical Memory Map |
| 823 | */ |
| 824 | #define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ |
| 825 | #define DMC1_MEM_CFG2 0xB45 |
| 826 | #define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ |
| 827 | #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ |
| 828 | |
| 829 | /* Memory Parameters */ |
| 830 | /* DDR Parameters */ |
| 831 | #define DDR_tREFRESH 7800 /* ns */ |
| 832 | #define DDR_tRAS 45 /* ns (min: 45ns)*/ |
| 833 | #define DDR_tRC 68 /* ns (min: 67.5ns)*/ |
| 834 | #define DDR_tRCD 23 /* ns (min: 22.5ns)*/ |
| 835 | #define DDR_tRFC 80 /* ns (min: 80ns)*/ |
| 836 | #define DDR_tRP 23 /* ns (min: 22.5ns)*/ |
| 837 | #define DDR_tRRD 15 /* ns (min: 15ns)*/ |
| 838 | #define DDR_tWR 15 /* ns (min: 15ns)*/ |
| 839 | #define DDR_tXSR 120 /* ns (min: 120ns)*/ |
| 840 | #define DDR_CASL 3 /* CAS Latency 3 */ |
| 841 | |
| 842 | /* |
| 843 | * mDDR memory configuration |
| 844 | */ |
| 845 | |
| 846 | #define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) |
| 847 | |
| 848 | #define DMC_DDR_BA_EMRS 2 |
| 849 | #define DMC_DDR_MEM_CASLAT 3 |
| 850 | /* 6 Set Cas Latency to 3 */ |
| 851 | #define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) |
| 852 | /* Min 0.75 ~ 1.25 */ |
| 853 | #define DMC_DDR_t_DQSS 1 |
| 854 | /* Min 2 tck */ |
| 855 | #define DMC_DDR_t_MRD 2 |
| 856 | /* 7, Min 45ns */ |
| 857 | #define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) |
| 858 | /* 10, Min 67.5ns */ |
| 859 | #define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) |
| 860 | /* 4,5(TRM), Min 22.5ns */ |
| 861 | #define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) |
| 862 | #define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) |
| 863 | /* 11,18(TRM) Min 80ns */ |
| 864 | #define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) |
| 865 | #define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) |
| 866 | /* 4, 5(TRM) Min 22.5ns */ |
| 867 | #define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) |
| 868 | #define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) |
| 869 | /* 3, Min 15ns */ |
| 870 | #define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) |
| 871 | /* Min 15ns */ |
| 872 | #define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) |
| 873 | #define DMC_DDR_t_WTR 2 |
| 874 | /* 1tck + tIS(1.5ns) */ |
| 875 | #define DMC_DDR_t_XP 2 |
| 876 | /* 17, Min 120ns */ |
| 877 | #define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) |
| 878 | #define DMC_DDR_t_ESR DMC_DDR_t_XSR |
| 879 | /* TRM 2656 */ |
| 880 | #define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) |
| 881 | /* 2b01 : mDDR */ |
| 882 | #define DMC_DDR_USER_CONFIG 1 |
| 883 | |
| 884 | #ifndef __ASSEMBLY__ |
| 885 | enum s3c64xx_uarts_nr { |
| 886 | S3C64XX_UART0, |
| 887 | S3C64XX_UART1, |
| 888 | S3C64XX_UART2, |
| 889 | }; |
| 890 | |
| 891 | #include "s3c64x0.h" |
| 892 | |
| 893 | static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) |
| 894 | { |
| 895 | return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); |
| 896 | } |
| 897 | #endif |
| 898 | |
| 899 | #endif /*__S3C6400_H__*/ |