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Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +02003 */
Heiko Schocherca43ba12007-01-11 15:44:44 +01004#include <config.h>
Stefan Roeseb36df562010-09-09 19:18:00 +02005#include <asm/ppc4xx.h>
Heiko Schocherca43ba12007-01-11 15:44:44 +01006
7#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
8
9#include <ppc_asm.tmpl>
10#include <ppc_defs.h>
11
12#include <asm/cache.h>
13#include <asm/mmu.h>
14
15/**
16 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
17 *
18 * IMPORTANT: For pass1 this code must run from cache since you can not
19 * reliably change a peripheral banks timing register (pbxap) while running
20 * code from that bank. For ex., since we are running from ROM on bank 0, we
21 * can NOT execute the code that modifies bank 0 timings from ROM, so
22 * we run it from cache.
23 *
24 * Bank 0 - Boot-Flash
25 * Bank 1 - NAND-Flash
26 * Bank 2 - ISA bus
27 * Bank 3 - Second Flash
28 * Bank 4 - USB controller
29 */
30 .globl ext_bus_cntlr_init
31ext_bus_cntlr_init:
32/*
33 * We need the current boot up configuration to set correct
34 * timings into internal flash and external flash
35 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020036 mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
Wolfgang Denkf11033e2007-01-15 13:41:04 +010037 0 0 -> 8 bit external ROM
38 0 1 -> 16 bit internal ROM */
Heiko Schocherca43ba12007-01-11 15:44:44 +010039 addi r4,0,2
40 srw r24,r24,r4 /* shift right r24 two positions */
41 andi. r24,r24,0x06000
Wolfgang Denkf11033e2007-01-15 13:41:04 +010042/*
Heiko Schocherca43ba12007-01-11 15:44:44 +010043 * All calculations are based on 33MHz EBC clock.
44 *
45 * First, create a "very slow" timing (~250ns) with burst mode enabled
46 * This is need for the external flash access
47 */
48 lis r25,0x0800
Jeroen Hofstee3fd1e852013-01-08 13:35:53 +000049 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
50 ori r25,r25,0x0280
Heiko Schocherca43ba12007-01-11 15:44:44 +010051/*
52 * Second, create a fast timing:
53 * 90ns first cycle - 3 clock access
54 * and 90ns burst cycle, plus 1 clock after the last access
55 * This is used for the internal access
56 */
57 lis r26,0x8900
Jeroen Hofstee3fd1e852013-01-08 13:35:53 +000058 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
59 ori r26,r26,0x0280
Heiko Schocherca43ba12007-01-11 15:44:44 +010060/*
61 * We can't change settings on CS# if we currently use them.
62 * -> load a few instructions into cache and run this code from cache
63 */
64 mflr r4 /* save link register */
65 bl ..getAddr
66..getAddr:
67 mflr r3 /* get address of ..getAddr */
68 mtlr r4 /* restore link register */
69 addi r4,0,14 /* set ctr to 10; used to prefetch */
70 mtctr r4 /* 10 cache lines to fit this function
71 in cache (gives us 8x10=80 instructions) */
72..ebcloop:
73 icbt r0,r3 /* prefetch cache line for addr in r3 */
74 addi r3,r3,32 /* move to next cache line */
75 bdnz ..ebcloop /* continue for 10 cache lines */
76/*
77 * Delay to ensure all accesses to ROM are complete before changing
78 * bank 0 timings. 200usec should be enough.
79 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
80 */
81 lis r3,0x0
82 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
83 mtctr r3
84..spinlp:
85 bdnz ..spinlp /* spin loop */
86
87/*-----------------------------------------------------------------------
88 * Memory Bank 0 (BOOT-ROM) initialization
89 * 0xFFEF00000....0xFFFFFFF
90 * We only have to change the timing. Mapping is ok by boot-strapping
91 *----------------------------------------------------------------------- */
92
Stefan Roesed1c3b272009-09-09 16:25:29 +020093 li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
94 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +010095
96 mr r4,r26 /* assume internal fast flash is boot flash */
97 cmpwi r24,0x2000 /* assumption true? ... */
98 beq 1f /* ...yes! */
99 mr r4,r25 /* ...no, use the slow variant */
100 mr r25,r26 /* use this for the other flash */
1011:
Stefan Roesed1c3b272009-09-09 16:25:29 +0200102 mtdcr EBC0_CFGDATA,r4 /* change timing now */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100103
Stefan Roesed1c3b272009-09-09 16:25:29 +0200104 li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
105 mtdcr EBC0_CFGADDR,r4
106 mfdcr r4,EBC0_CFGDATA
Heiko Schocherca43ba12007-01-11 15:44:44 +0100107 lis r3,0x0001
108 ori r3,r3,0x8000 /* allow reads and writes */
109 or r4,r4,r3
Stefan Roesed1c3b272009-09-09 16:25:29 +0200110 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100111
112/*-----------------------------------------------------------------------
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100113 * Memory Bank 3 (Second-Flash) initialization
Heiko Schocherca43ba12007-01-11 15:44:44 +0100114 * 0xF0000000...0xF01FFFFF -> 2MB
115 *----------------------------------------------------------------------- */
116
Stefan Roesed1c3b272009-09-09 16:25:29 +0200117 li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
118 mtdcr EBC0_CFGADDR,r4
119 mtdcr EBC0_CFGDATA,r2 /* change timing */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100120
Stefan Roesed1c3b272009-09-09 16:25:29 +0200121 li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
122 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100123
124 lis r4,0xF003
125 ori r4,r4,0x8000
126/*
127 * Consider boot configuration
128 */
129 xori r24,r24,0x2000 /* invert current bus width */
130 or r4,r4,r24
Stefan Roesed1c3b272009-09-09 16:25:29 +0200131 mtdcr EBC0_CFGDATA,r4
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100132
Heiko Schocherca43ba12007-01-11 15:44:44 +0100133/*-----------------------------------------------------------------------
134 * Memory Bank 1 (NAND-Flash) initialization
135 * 0x77D00000...0x77DFFFFF -> 1MB
136 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
137 * - the setup time is 0ns
138 * - the hold time is 15ns
139 * ->
140 * - TWT = 0
141 * - CSN = 0
142 * - OEN = 0
143 * - WBN = 0
144 * - WBF = 0
145 * - TH = 1
146 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
147 *----------------------------------------------------------------------- */
148
Stefan Roesed1c3b272009-09-09 16:25:29 +0200149 li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
150 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100151
152 lis r4,0x0000
153 ori r4,r4,0x0200
Stefan Roesed1c3b272009-09-09 16:25:29 +0200154 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100155
Stefan Roesed1c3b272009-09-09 16:25:29 +0200156 li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
157 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100158
159 lis r4,0x77D1
160 ori r4,r4,0x8000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200161 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100162
163
164/* USB init (without acceleration) */
165#ifndef CONFIG_ISP1161_PRESENT
Stefan Roesed1c3b272009-09-09 16:25:29 +0200166 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
167 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100168 lis r4,0x0180
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100169 ori r4,r4,0x5940
Stefan Roesed1c3b272009-09-09 16:25:29 +0200170 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100171#endif
172
173/*-----------------------------------------------------------------------
174 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
175 * 0x78000000...0x7BFFFFFF -> 64 MB
176 * Wir arbeiten bei 33 MHz -> 30ns
177 *-----------------------------------------------------------------------
178
179 A7 (ppc notation) or A24 (standard notation) decides about
180 the type of access:
181 A7/A24=0 -> memory cycle
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100182 A7/ /A24=1 -> I/O cycle
Heiko Schocherca43ba12007-01-11 15:44:44 +0100183*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200184 li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
185 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100186/*
187 We emulate an ISA access
188
189 1. Address active
190 2. wait 0 EBC clocks -> CSN=0
191 3. set CS#
192 4. wait 0 EBC clock -> OEN/WBN=0
193 5. set OE#/WE#
194 6. wait 4 clocks (ca. 90ns) and for Ready signal
195 7. hold for 4 clocks -> TH=4
196*/
197
198#if 1
199/* faster access to isa-bus */
200 lis r4,0x0180
201 ori r4,r4,0x5940
202#else
203 lis r4,0x0100
204 ori r4,r4,0x0340
205#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200206 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100207
208#ifdef IDE_USES_ISA_EMULATION
Stefan Roesed1c3b272009-09-09 16:25:29 +0200209 li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
210 mtdcr EBC0_CFGADDR,r25
211 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100212#endif
213
Stefan Roesed1c3b272009-09-09 16:25:29 +0200214 li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
215 mtdcr EBC0_CFGADDR,r25
216 mtdcr EBC0_CFGDATA,r4
217 li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
218 mtdcr EBC0_CFGADDR,r25
219 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100220
Stefan Roesed1c3b272009-09-09 16:25:29 +0200221 li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
222 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100223
224 lis r4,0x780B
225 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200226 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100227/*
228 * the other areas are only 1MiB in size
229 */
230 lis r4,0x7401
231 ori r4,r4,0xA000
232
Stefan Roesed1c3b272009-09-09 16:25:29 +0200233 li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
234 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100235 lis r4,0x7401
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100236 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200237 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100238
Stefan Roesed1c3b272009-09-09 16:25:29 +0200239 li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
240 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100241 lis r4,0x7411
242 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200243 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100244
245#ifndef CONFIG_ISP1161_PRESENT
Stefan Roesed1c3b272009-09-09 16:25:29 +0200246 li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
247 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100248 lis r4,0x7421
249 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200250 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100251#endif
252#ifdef IDE_USES_ISA_EMULATION
Stefan Roesed1c3b272009-09-09 16:25:29 +0200253 li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
254 mtdcr EBC0_CFGADDR,r25
Heiko Schocherca43ba12007-01-11 15:44:44 +0100255 lis r4,0x0000
256 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200257 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100258#endif
259
260/*-----------------------------------------------------------------------
261 * Memory bank 4: USB controller Philips ISP6111
262 * 0x77C00000 ... 0x77CFFFFF
263 *
264 * The chip is connected to:
265 * - CPU CS#4
266 * - CPU IRQ#2
267 * - CPU DMA 3
268 *
269 * Timing:
270 * - command to first data: 300ns. Software must ensure this timing!
271 * - Write pulse: 26ns
272 * - Read pulse: 33ns
273 * - read cycle time: 150ns
274 * - write cycle time: 140ns
275 *
276 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
277 *
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100278 * |- 300ns --|
279 * |---- 420ns ---|---- 420ns ---| cycle
Heiko Schocherca43ba12007-01-11 15:44:44 +0100280 * CS ############:###____#######:###____#######
281 * OE ############:####___#######:####___#######
282 * WE ############:####__########:####__########
283 *
284 * ----> 2 clocks RD/WR pulses: 60ns
285 * ----> CSN: 3 clock, 90ns
286 * ----> OEN: 1 clocks (read cycle)
287 * ----> WBN: 1 clocks (write cycle)
288 * ----> WBE: 2 clocks
289 * ----> TH: 7 clock, 210ns
290 * ----> TWT: 7 clocks
291 *----------------------------------------------------------------------- */
292
293#ifdef CONFIG_ISP1161_PRESENT
294
Stefan Roesed1c3b272009-09-09 16:25:29 +0200295 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
296 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100297
298 lis r4,0x030D
299 ori r4,r4,0x5E80
Stefan Roesed1c3b272009-09-09 16:25:29 +0200300 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100301
Stefan Roesed1c3b272009-09-09 16:25:29 +0200302 li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
303 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100304
305 lis r4,0x77C1
306 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200307 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100308
309#endif
310
311#ifndef IDE_USES_ISA_EMULATION
312
313/*-----------------------------------------------------------------------
314 * Memory Bank 5 used for IDE access
315 *
316 * Timings for IDE Interface
317 *
318 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
319 * 70 165 30 PIO-Mode 0, [ns]
320 * 3 6 1 [Cycles] ----> AP=0x040C0200
321 * 50 125 20 PIO-Mode 1, [ns]
322 * 2 5 1 [Cycles] ----> AP=0x03080200
323 * 30 100 15 PIO-Mode 2, [ns]
324 * 1 4 1 [Cycles] ----> AP=0x02040200
325 * 30 80 10 PIO-Mode 3, [ns]
326 * 1 3 1 [Cycles] ----> AP=0x01840200
327 * 25 70 10 PIO-Mode 4, [ns]
328 * 1 3 1 [Cycles] ----> AP=0x01840200
329 *
330 *----------------------------------------------------------------------- */
331
Stefan Roesed1c3b272009-09-09 16:25:29 +0200332 li r4,PB5AP
333 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100334 lis r4,0x040C
335 ori r4,r4,0x0200
Stefan Roesed1c3b272009-09-09 16:25:29 +0200336 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100337
Stefan Roesed1c3b272009-09-09 16:25:29 +0200338 li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
339 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100340
341 lis r4,0x7A01
342 ori r4,r4,0xA000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200343 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100344#endif
345/*
346 * External Peripheral Control Register
347 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200348 li r4,EBC0_CFG
349 mtdcr EBC0_CFGADDR,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100350
351 lis r4,0xB84E
352 ori r4,r4,0xF000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200353 mtdcr EBC0_CFGDATA,r4
Heiko Schocherca43ba12007-01-11 15:44:44 +0100354/*
355 * drive POST code
356 */
357 lis r4,0x7900
358 ori r4,r4,0x0080
359 li r3,0x0001
360 stb r3,0(r4) /* 01 -> external bus controller is initialized */
361 nop /* pass2 DCR errata #8 */
362 blr