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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 713a02a2ce46199c83c3cee0bd02f99dadaa4c8a / . / drivers / net / ax88796.h
blob: 510606610662101f061c3b3ff5b5a96c9c68385b [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]2/*
3 * AX88796L(NE2000) support
4 *
5 * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]6 */
7
8#ifndef __DRIVERS_AX88796L_H__
9#define __DRIVERS_AX88796L_H__
10
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]11#define DP_DATA (0x10 << 1)
12#define START_PG 0x40 /* First page of TX buffer */
13#define START_PG2 0x48
14#define STOP_PG 0x80 /* Last page +1 of RX ring */
15#define TX_PAGES 12
16#define RX_START (START_PG+TX_PAGES)
17#define RX_END STOP_PG
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]18
19#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]20#define AX88796L_BYTE_ACCESS 0x00001000
21#define AX88796L_OFFSET 0x00000400
22#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]23 AX88796L_BYTE_ACCESS + AX88796L_OFFSET
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]24#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1)
25#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1)
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]26
27#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR))
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]28#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR))
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]29
30#define EECS_HIGH (AX88796L_MEMR |= 0x10)
31#define EECS_LOW (AX88796L_MEMR &= 0xef)
32#define EECLK_HIGH (AX88796L_MEMR |= 0x80)
33#define EECLK_LOW (AX88796L_MEMR &= 0x7f)
34#define EEDI_HIGH (AX88796L_MEMR |= 0x20)
35#define EEDI_LOW (AX88796L_MEMR &= 0xdf)
36#define EEDO ((AX88796L_MEMR & 0x40)>>6)
37
38#define PAGE0_SET (AX88796L_CR &= 0x3f)
39#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
40
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]41#define BIT_DUMMY 0
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]42#define MAC_EEP_READ 1
43#define MAC_EEP_WRITE 2
44#define MAC_EEP_ERACE 3
45#define MAC_EEP_EWEN 4
46#define MAC_EEP_EWDS 5
47
48/* R7780MP Specific code */
49#if defined(CONFIG_R7780MP)
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]50#define ISA_OFFSET 0x1400
51#define DP_IN(_b_, _o_, _d_) (_d_) = \
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]52 *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
53#define DP_OUT(_b_, _o_, _d_) \
54 *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]55#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
56#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]57#else
58/* Please change for your target boards */
Jean-Christophe PLAGNIOL-VILLARD4acbc6c2008-04-24 07:57:16 +0200[diff] [blame]59#define ISA_OFFSET 0x0000
60#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
61#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
62#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
63#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]64#endif
65
goda.yusuke6a8a5dc2008-03-05 17:08:33 +0900[diff] [blame]66#endif /* __DRIVERS_AX88796L_H__ */