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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 713a02a2ce46199c83c3cee0bd02f99dadaa4c8a / . / drivers / pinctrl / mediatek / pinctrl-mt8512.c
blob: af43754a4d3784e3b7947603220a150d9cdaca77 [file] [log] [blame]
mingming lee51fcd562019-12-31 11:29:23 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Mingming Lee <mingming.lee@mediatek.com>
5 */
6
7#include <dm.h>
8
9#include "pinctrl-mtk-common.h"
10
11#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
12 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
13 _x_bits, 32, false)
14#define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
15 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
16 _x_bits, 32, true)
17#define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
18 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
19 _x_bits, 30, false)
20
21static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = {
22 PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3),
23};
24
25static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = {
26 PIN_FIELD(0, 115, 0x140, 0x10, 0, 1),
27};
28
29static const struct mtk_pin_field_calc mt8512_pin_di_range[] = {
30 PIN_FIELD(0, 115, 0x000, 0x10, 0, 1),
31};
32
33static const struct mtk_pin_field_calc mt8512_pin_do_range[] = {
34 PIN_FIELD(0, 115, 0x860, 0x10, 0, 1),
35};
36
37static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = {
38 PIN_FIELD(0, 115, 0x900, 0x10, 0, 1),
39};
40
41static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = {
42 PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1),
43};
44
45static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = {
46 PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1),
47 PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1),
48 PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1),
49 PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1),
50 PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1),
51 PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1),
52 PIN_FIELD(20, 20, 0x410, 0x10, 6, 1),
53 PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1),
54 PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1),
55 PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1),
56 PIN_FIELD(32, 32, 0x410, 0x10, 10, 1),
57 PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1),
58 PIN_FIELD(40, 40, 0x410, 0x10, 12, 1),
59 PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1),
60 PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1),
61 PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1),
62 PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1),
63 PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1),
64 PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1),
65 PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1),
66 PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1),
67 PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1),
68 PIN_FIELD(70, 70, 0x410, 0x10, 22, 1),
69 PIN_FIELD(71, 71, 0x410, 0x10, 23, 1),
70 PIN_FIELD(72, 72, 0x410, 0x10, 24, 1),
71 PIN_FIELD(73, 73, 0x410, 0x10, 25, 1),
72 PIN_FIELD(74, 74, 0x410, 0x10, 26, 1),
73 PIN_FIELD(75, 75, 0x410, 0x10, 27, 1),
74 PIN_FIELD(76, 76, 0x410, 0x10, 28, 1),
75 PIN_FIELD(77, 77, 0x410, 0x10, 29, 1),
76 PIN_FIELD(78, 78, 0x410, 0x10, 30, 1),
77 PIN_FIELD(79, 79, 0x410, 0x10, 31, 1),
78 PIN_FIELD(80, 80, 0x420, 0x10, 0, 1),
79 PIN_FIELD(81, 81, 0x420, 0x10, 1, 1),
80 PIN_FIELD(82, 82, 0x420, 0x10, 2, 1),
81 PIN_FIELD(83, 83, 0x420, 0x10, 3, 1),
82 PIN_FIELD(84, 84, 0x420, 0x10, 4, 1),
83 PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1),
84 PIN_FIELD(87, 87, 0x420, 0x10, 6, 1),
85 PIN_FIELDS(88, 91, 0x420, 0x10, 7, 1),
86 PIN_FIELDS(92, 98, 0x420, 0x10, 8, 1),
87 PIN_FIELDS(99, 101, 0x420, 0x10, 9, 1),
88 PIN_FIELDS(102, 104, 0x420, 0x10, 10, 1),
89 PIN_FIELDS(105, 111, 0x420, 0x10, 11, 1),
90 PIN_FIELDS(112, 115, 0x420, 0x10, 12, 1),
91};
92
93static const struct mtk_pin_field_calc mt8512_pin_smt_range[] = {
94 PIN_FIELDS(0, 2, 0x470, 0x10, 0, 1),
95 PIN_FIELDS(3, 5, 0x470, 0x10, 1, 1),
96 PIN_FIELDS(6, 7, 0x470, 0x10, 2, 1),
97 PIN_FIELDS(8, 11, 0x470, 0x10, 3, 1),
98 PIN_FIELDS(12, 15, 0x470, 0x10, 4, 1),
99 PIN_FIELDS(16, 19, 0x470, 0x10, 5, 1),
100 PIN_FIELD(20, 20, 0x470, 0x10, 6, 1),
101 PIN_FIELDS(21, 25, 0x470, 0x10, 7, 1),
102 PIN_FIELDS(26, 27, 0x470, 0x10, 8, 1),
103 PIN_FIELDS(28, 31, 0x470, 0x10, 9, 1),
104 PIN_FIELD(32, 32, 0x470, 0x10, 10, 1),
105 PIN_FIELDS(33, 39, 0x470, 0x10, 11, 1),
106 PIN_FIELD(40, 40, 0x470, 0x10, 12, 1),
107 PIN_FIELDS(41, 43, 0x470, 0x10, 13, 1),
108 PIN_FIELDS(44, 47, 0x470, 0x10, 14, 1),
109 PIN_FIELDS(48, 51, 0x470, 0x10, 15, 1),
110 PIN_FIELDS(52, 53, 0x470, 0x10, 16, 1),
111 PIN_FIELDS(54, 57, 0x470, 0x10, 17, 1),
112 PIN_FIELDS(58, 63, 0x470, 0x10, 18, 1),
113 PIN_FIELDS(64, 65, 0x470, 0x10, 19, 1),
114 PIN_FIELDS(66, 67, 0x470, 0x10, 20, 1),
115 PIN_FIELDS(68, 69, 0x470, 0x10, 21, 1),
116 PIN_FIELD(70, 70, 0x470, 0x10, 22, 1),
117 PIN_FIELD(71, 71, 0x470, 0x10, 23, 1),
118 PIN_FIELD(72, 72, 0x470, 0x10, 24, 1),
119 PIN_FIELD(73, 73, 0x470, 0x10, 25, 1),
120 PIN_FIELD(74, 74, 0x470, 0x10, 26, 1),
121 PIN_FIELD(75, 75, 0x470, 0x10, 27, 1),
122 PIN_FIELD(76, 76, 0x470, 0x10, 28, 1),
123 PIN_FIELD(77, 77, 0x470, 0x10, 29, 1),
124 PIN_FIELD(78, 78, 0x470, 0x10, 30, 1),
125 PIN_FIELD(79, 79, 0x470, 0x10, 31, 1),
126 PIN_FIELD(80, 80, 0x480, 0x10, 0, 1),
127 PIN_FIELD(81, 81, 0x480, 0x10, 1, 1),
128 PIN_FIELD(82, 82, 0x480, 0x10, 2, 1),
129 PIN_FIELD(83, 83, 0x480, 0x10, 3, 1),
130 PIN_FIELD(84, 84, 0x480, 0x10, 4, 1),
131 PIN_FIELDS(85, 86, 0x480, 0x10, 5, 1),
132 PIN_FIELD(87, 87, 0x480, 0x10, 6, 1),
133 PIN_FIELDS(88, 91, 0x480, 0x10, 7, 1),
134 PIN_FIELDS(92, 98, 0x480, 0x10, 8, 1),
135 PIN_FIELDS(99, 101, 0x480, 0x10, 9, 1),
136 PIN_FIELDS(102, 104, 0x480, 0x10, 10, 1),
137 PIN_FIELDS(105, 111, 0x480, 0x10, 11, 1),
138 PIN_FIELDS(112, 115, 0x480, 0x10, 12, 1),
139};
140
141static const struct mtk_pin_field_calc mt8512_pin_drv_range[] = {
142 PIN_FIELDS(0, 2, 0x710, 0x10, 0, 4),
143 PIN_FIELDS(3, 5, 0x710, 0x10, 4, 4),
144 PIN_FIELDS(6, 7, 0x710, 0x10, 8, 4),
145 PIN_FIELDS(8, 11, 0x710, 0x10, 12, 4),
146 PIN_FIELDS(12, 15, 0x710, 0x10, 16, 4),
147 PIN_FIELDS(16, 19, 0x710, 0x10, 20, 4),
148 PIN_FIELD(20, 20, 0x710, 0x10, 24, 4),
149 PIN_FIELDS(21, 25, 0x710, 0x10, 28, 4),
150 PIN_FIELDS(26, 27, 0x720, 0x10, 0, 4),
151 PIN_FIELDS(28, 31, 0x720, 0x10, 4, 4),
152 PIN_FIELD(32, 32, 0x720, 0x10, 8, 4),
153 PIN_FIELDS(33, 39, 0x720, 0x10, 12, 4),
154 PIN_FIELD(40, 40, 0x720, 0x10, 16, 4),
155 PIN_FIELDS(41, 43, 0x720, 0x10, 20, 4),
156 PIN_FIELDS(44, 47, 0x720, 0x10, 24, 4),
157 PIN_FIELDS(48, 51, 0x720, 0x10, 28, 4),
158 PIN_FIELDS(52, 53, 0x730, 0x10, 0, 4),
159 PIN_FIELDS(54, 57, 0x730, 0x10, 4, 4),
160 PIN_FIELDS(58, 63, 0x730, 0x10, 8, 4),
161 PIN_FIELDS(64, 65, 0x730, 0x10, 12, 4),
162 PIN_FIELDS(66, 67, 0x730, 0x10, 16, 4),
163 PIN_FIELDS(68, 69, 0x730, 0x10, 20, 4),
164 PIN_FIELD(70, 70, 0x730, 0x10, 24, 4),
165 PIN_FIELD(71, 71, 0x730, 0x10, 28, 4),
166 PIN_FIELDS(72, 75, 0x740, 0x10, 0, 4),
167 PIN_FIELDS(76, 79, 0x740, 0x10, 16, 4),
168 PIN_FIELD(80, 80, 0x750, 0x10, 0, 4),
169 PIN_FIELD(81, 81, 0x750, 0x10, 4, 4),
170 PIN_FIELD(82, 82, 0x750, 0x10, 8, 4),
171 PIN_FIELDS(83, 86, 0x740, 0x10, 16, 4),
172 PIN_FIELD(87, 87, 0x750, 0x10, 24, 4),
173 PIN_FIELDS(88, 91, 0x750, 0x10, 28, 4),
174 PIN_FIELDS(92, 98, 0x760, 0x10, 0, 4),
175 PIN_FIELDS(99, 101, 0x760, 0x10, 4, 4),
176 PIN_FIELDS(102, 104, 0x760, 0x10, 8, 4),
177 PIN_FIELDS(105, 111, 0x760, 0x10, 12, 4),
178 PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4),
179};
180
181static const struct mtk_pin_reg_calc mt8512_reg_cals[] = {
182 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range),
183 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range),
184 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range),
185 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8512_pin_do_range),
186 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8512_pin_ies_range),
187 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8512_pin_smt_range),
188 [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8512_pin_pullsel_range),
189 [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8512_pin_pullen_range),
190 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8512_pin_drv_range),
191};
192
193static const struct mtk_pin_desc mt8512_pins[] = {
194 MTK_PIN(0, "GPIO0", DRV_GRP4),
195 MTK_PIN(1, "GPIO1", DRV_GRP4),
196 MTK_PIN(2, "GPIO2", DRV_GRP4),
197 MTK_PIN(3, "GPIO3", DRV_GRP4),
198 MTK_PIN(4, "GPIO4", DRV_GRP4),
199 MTK_PIN(5, "GPIO5", DRV_GRP4),
200 MTK_PIN(6, "GPIO6", DRV_GRP4),
201 MTK_PIN(7, "GPIO7", DRV_GRP4),
202 MTK_PIN(8, "GPIO8", DRV_GRP4),
203 MTK_PIN(9, "GPIO9", DRV_GRP4),
204 MTK_PIN(10, "GPIO10", DRV_GRP4),
205 MTK_PIN(11, "GPIO11", DRV_GRP4),
206 MTK_PIN(12, "GPIO12", DRV_GRP4),
207 MTK_PIN(13, "GPIO13", DRV_GRP4),
208 MTK_PIN(14, "GPIO14", DRV_GRP4),
209 MTK_PIN(15, "GPIO15", DRV_GRP4),
210 MTK_PIN(16, "GPIO16", DRV_GRP4),
211 MTK_PIN(17, "GPIO17", DRV_GRP4),
212 MTK_PIN(18, "GPIO18", DRV_GRP4),
213 MTK_PIN(19, "GPIO19", DRV_GRP4),
214 MTK_PIN(20, "GPIO20", DRV_GRP4),
215 MTK_PIN(21, "AUDIO_SYNC", DRV_GRP4),
216 MTK_PIN(22, "WIFI_INTB", DRV_GRP4),
217 MTK_PIN(23, "BT_INTB", DRV_GRP4),
218 MTK_PIN(24, "BT_STEREO", DRV_GRP4),
219 MTK_PIN(25, "RSTNB", DRV_GRP4),
220 MTK_PIN(26, "USB_ID", DRV_GRP4),
221 MTK_PIN(27, "USB_DRV", DRV_GRP4),
222 MTK_PIN(28, "EINT_GAUGEING", DRV_GRP4),
223 MTK_PIN(29, "CHG_IRQ", DRV_GRP4),
224 MTK_PIN(30, "CHG_OTG", DRV_GRP4),
225 MTK_PIN(31, "CHG_CEB", DRV_GRP4),
226 MTK_PIN(32, "FL_EN", DRV_GRP4),
227 MTK_PIN(33, "WAN_SMS_RDY", DRV_GRP4),
228 MTK_PIN(34, "SOC2WAN_RESET", DRV_GRP4),
229 MTK_PIN(35, "WAN_FM_RDY", DRV_GRP4),
230 MTK_PIN(36, "WAN_DIS", DRV_GRP4),
231 MTK_PIN(37, "WAN_VBUS_EN", DRV_GRP4),
232 MTK_PIN(38, "WAN_VBAT_EN", DRV_GRP4),
233 MTK_PIN(39, "WAN_PWR_EN", DRV_GRP4),
234 MTK_PIN(40, "KPROW0", DRV_GRP4),
235 MTK_PIN(41, "KPROW1", DRV_GRP4),
236 MTK_PIN(42, "KPCOL0", DRV_GRP4),
237 MTK_PIN(43, "KPCOL1", DRV_GRP4),
238 MTK_PIN(44, "PWM0", DRV_GRP4),
239 MTK_PIN(45, "PWM1", DRV_GRP4),
240 MTK_PIN(46, "PWM2", DRV_GRP4),
241 MTK_PIN(47, "PWM3", DRV_GRP4),
242 MTK_PIN(48, "JTMS", DRV_GRP4),
243 MTK_PIN(49, "JTCK", DRV_GRP4),
244 MTK_PIN(50, "JTDI", DRV_GRP4),
245 MTK_PIN(51, "JTDO", DRV_GRP4),
246 MTK_PIN(52, "URXD0", DRV_GRP4),
247 MTK_PIN(53, "UTXD0", DRV_GRP4),
248 MTK_PIN(54, "URXD1", DRV_GRP4),
249 MTK_PIN(55, "UTXD1", DRV_GRP4),
250 MTK_PIN(56, "URTS1", DRV_GRP4),
251 MTK_PIN(57, "UCTS1", DRV_GRP4),
252 MTK_PIN(58, "RTC32K_CK", DRV_GRP4),
253 MTK_PIN(59, "PMIC_DVS_REQ0", DRV_GRP4),
254 MTK_PIN(60, "PMIC_DVS_REQ1", DRV_GRP4),
255 MTK_PIN(61, "WATCHDOG", DRV_GRP4),
256 MTK_PIN(62, "PMIC_INT", DRV_GRP4),
257 MTK_PIN(63, "SUSPEND", DRV_GRP4),
258 MTK_PIN(64, "SDA0", DRV_GRP4),
259 MTK_PIN(65, "SCL0", DRV_GRP4),
260 MTK_PIN(66, "SDA1", DRV_GRP4),
261 MTK_PIN(67, "SCL1", DRV_GRP4),
262 MTK_PIN(68, "SDA2", DRV_GRP4),
263 MTK_PIN(69, "SCL2", DRV_GRP4),
264 MTK_PIN(70, "MSDC1_CMD", DRV_GRP4),
265 MTK_PIN(71, "MSDC1_CLK", DRV_GRP4),
266 MTK_PIN(72, "MSDC1_DAT0", DRV_GRP4),
267 MTK_PIN(73, "MSDC1_DAT1", DRV_GRP4),
268 MTK_PIN(74, "MSDC1_DAT2", DRV_GRP4),
269 MTK_PIN(75, "MSDC1_DAT3", DRV_GRP4),
270 MTK_PIN(76, "MSDC0_DAT7", DRV_GRP4),
271 MTK_PIN(77, "MSDC0_DAT6", DRV_GRP4),
272 MTK_PIN(78, "MSDC0_DAT5", DRV_GRP4),
273 MTK_PIN(79, "MSDC0_DAT4", DRV_GRP4),
274 MTK_PIN(80, "MSDC0_RSTB", DRV_GRP4),
275 MTK_PIN(81, "MSDC0_CMD", DRV_GRP4),
276 MTK_PIN(82, "MSDC0_CLK", DRV_GRP4),
277 MTK_PIN(83, "MSDC0_DAT3", DRV_GRP4),
278 MTK_PIN(84, "MSDC0_DAT2", DRV_GRP4),
279 MTK_PIN(85, "MSDC0_DAT1", DRV_GRP4),
280 MTK_PIN(86, "MSDC0_DAT0", DRV_GRP4),
281 MTK_PIN(87, "SPDIF", DRV_GRP4),
282 MTK_PIN(88, "PCM_CLK", DRV_GRP4),
283 MTK_PIN(89, "PCM_SYNC", DRV_GRP4),
284 MTK_PIN(90, "PCM_RX", DRV_GRP4),
285 MTK_PIN(91, "PCM_TX", DRV_GRP4),
286 MTK_PIN(92, "I2SIN_MCLK", DRV_GRP4),
287 MTK_PIN(93, "I2SIN_LRCK", DRV_GRP4),
288 MTK_PIN(94, "I2SIN_BCK", DRV_GRP4),
289 MTK_PIN(95, "I2SIN_DAT0", DRV_GRP4),
290 MTK_PIN(96, "I2SIN_DAT1", DRV_GRP4),
291 MTK_PIN(97, "I2SIN_DAT2", DRV_GRP4),
292 MTK_PIN(98, "I2SIN_DAT3", DRV_GRP4),
293 MTK_PIN(99, "DMIC0_CLK", DRV_GRP4),
294 MTK_PIN(100, "DMIC0_DAT0", DRV_GRP4),
295 MTK_PIN(101, "DMIC0_DAT1", DRV_GRP4),
296 MTK_PIN(102, "DMIC1_CLK", DRV_GRP4),
297 MTK_PIN(103, "DMIC1_DAT0", DRV_GRP4),
298 MTK_PIN(104, "DMIC1_DAT1", DRV_GRP4),
299 MTK_PIN(105, "I2SO_BCK", DRV_GRP4),
300 MTK_PIN(106, "I2SO_LRCK", DRV_GRP4),
301 MTK_PIN(107, "I2SO_MCLK", DRV_GRP4),
302 MTK_PIN(108, "I2SO_DAT0", DRV_GRP4),
303 MTK_PIN(109, "I2SO_DAT1", DRV_GRP4),
304 MTK_PIN(110, "I2SO_DAT2", DRV_GRP4),
305 MTK_PIN(111, "I2SO_DAT3", DRV_GRP4),
306 MTK_PIN(112, "SPI_CSB", DRV_GRP4),
307 MTK_PIN(113, "SPI_CLK", DRV_GRP4),
308 MTK_PIN(114, "SPI_MISO", DRV_GRP4),
309 MTK_PIN(115, "SPI_MOSI", DRV_GRP4),
310};
311
312/* List all groups consisting of these pins dedicated to the enablement of
313 * certain hardware block and the corresponding mode for all of the pins.
314 * The hardware probably has multiple combinations of these pinouts.
315 */
316
317/* UART */
318static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, };
319static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, };
320static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, };
321static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, };
322static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, };
323static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, };
324
325/* Joint those groups owning the same capability in user point of view which
326 * allows that people tend to use through the device tree.
327 */
328static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd",
329 "uart1_0_rxd_txd",
330 "uart2_0_rxd_txd", };
331
332/* SNAND */
333static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, };
334static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
335
336/* MMC0 */
337static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84,
338 85, 86, };
339static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
340
341static const struct mtk_group_desc mt8512_groups[] = {
342 PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd),
343 PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8512_uart1_0_rxd_txd),
344 PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8512_uart2_0_rxd_txd),
345
346 PINCTRL_PIN_GROUP("msdc0", mt8512_msdc0),
347
348 PINCTRL_PIN_GROUP("snfi", mt8512_snfi),
349};
350
351static const char *const mt8512_msdc_groups[] = { "msdc0" };
352
353static const struct mtk_function_desc mt8512_functions[] = {
354 {"uart", mt8512_uart_groups, ARRAY_SIZE(mt8512_uart_groups)},
355 {"msdc", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
356 {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)},
357};
358
359static struct mtk_pinctrl_soc mt8512_data = {
360 .name = "mt8512_pinctrl",
361 .reg_cal = mt8512_reg_cals,
362 .pins = mt8512_pins,
363 .npins = ARRAY_SIZE(mt8512_pins),
364 .grps = mt8512_groups,
365 .ngrps = ARRAY_SIZE(mt8512_groups),
366 .funcs = mt8512_functions,
367 .nfuncs = ARRAY_SIZE(mt8512_functions),
368};
369
370static int mtk_pinctrl_mt8512_probe(struct udevice *dev)
371{
372 return mtk_pinctrl_common_probe(dev, &mt8512_data);
373}
374
375static const struct udevice_id mt8512_pctrl_match[] = {
376 { .compatible = "mediatek,mt8512-pinctrl" },
377 { /* sentinel */ }
378};
379
380U_BOOT_DRIVER(mt8512_pinctrl) = {
381 .name = "mt8512_pinctrl",
382 .id = UCLASS_PINCTRL,
383 .of_match = mt8512_pctrl_match,
384 .ops = &mtk_pinctrl_ops,
385 .probe = mtk_pinctrl_mt8512_probe,
386 .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
387};