blob: 7cfda50c8cdbe2692e330aa5dc7ea4abbbd4b6da [file] [log] [blame]
Priyanka Jain062ef1a2013-10-18 17:19:06 +05301/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * T1040 RDB board configuration file
28 */
29#define CONFIG_T104xRDB
30#define CONFIG_T1040RDB
31#define CONFIG_PHYS_64BIT
32
33#ifdef CONFIG_RAMBOOT_PBL
34#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36#endif
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE
40#define CONFIG_E500 /* BOOKE e500 family */
41#define CONFIG_E500MC /* BOOKE e500mc family */
42#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Priyanka Jain062ef1a2013-10-18 17:19:06 +053043#define CONFIG_MP /* support multiple processors */
44
45#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053046#define CONFIG_SYS_TEXT_BASE 0xeff40000
Priyanka Jain062ef1a2013-10-18 17:19:06 +053047#endif
48
49#ifndef CONFIG_RESET_VECTOR_ADDRESS
50#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
51#endif
52
53#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
54#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
55#define CONFIG_FSL_IFC /* Enable IFC Support */
56#define CONFIG_PCI /* Enable PCI/PCIE */
57#define CONFIG_PCI_INDIRECT_BRIDGE
58#define CONFIG_PCIE1 /* PCIE controler 1 */
59#define CONFIG_PCIE2 /* PCIE controler 2 */
60#define CONFIG_PCIE3 /* PCIE controler 3 */
61#define CONFIG_PCIE4 /* PCIE controler 4 */
62
63#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
64#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
65
66#define CONFIG_FSL_LAW /* Use common FSL init code */
67
68#define CONFIG_ENV_OVERWRITE
69
70#ifdef CONFIG_SYS_NO_FLASH
71#define CONFIG_ENV_IS_NOWHERE
72#else
73#define CONFIG_FLASH_CFI_DRIVER
74#define CONFIG_SYS_FLASH_CFI
75#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
76#endif
77
78#ifndef CONFIG_SYS_NO_FLASH
79#if defined(CONFIG_SPIFLASH)
80#define CONFIG_SYS_EXTRA_ENV_RELOC
81#define CONFIG_ENV_IS_IN_SPI_FLASH
Priyanka Jain062ef1a2013-10-18 17:19:06 +053082#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
83#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
84#define CONFIG_ENV_SECT_SIZE 0x10000
85#elif defined(CONFIG_SDCARD)
86#define CONFIG_SYS_EXTRA_ENV_RELOC
87#define CONFIG_ENV_IS_IN_MMC
88#define CONFIG_SYS_MMC_ENV_DEV 0
89#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053090#define CONFIG_ENV_OFFSET (512 * 1658)
Priyanka Jain062ef1a2013-10-18 17:19:06 +053091#elif defined(CONFIG_NAND)
92#define CONFIG_SYS_EXTRA_ENV_RELOC
93#define CONFIG_ENV_IS_IN_NAND
94#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053095#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
Priyanka Jain062ef1a2013-10-18 17:19:06 +053096#else
97#define CONFIG_ENV_IS_IN_FLASH
98#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
99#define CONFIG_ENV_SIZE 0x2000
100#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
101#endif
102#else /* CONFIG_SYS_NO_FLASH */
103#define CONFIG_ENV_SIZE 0x2000
104#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
105#endif
106
107#define CONFIG_SYS_CLK_FREQ 100000000
108#define CONFIG_DDR_CLK_FREQ 66666666
109
110/*
111 * These can be toggled for performance analysis, otherwise use default.
112 */
113#define CONFIG_SYS_CACHE_STASHING
114#define CONFIG_BACKSIDE_L2_CACHE
115#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
116#define CONFIG_BTB /* toggle branch predition */
117#define CONFIG_DDR_ECC
118#ifdef CONFIG_DDR_ECC
119#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
121#endif
122
123#define CONFIG_ENABLE_36BIT_PHYS
124
125#define CONFIG_ADDR_MAP
126#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
127
128#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
129#define CONFIG_SYS_MEMTEST_END 0x00400000
130#define CONFIG_SYS_ALT_MEMTEST
131#define CONFIG_PANIC_HANG /* do not reset board on panic */
132
133/*
134 * Config the L3 Cache as L3 SRAM
135 */
136#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
137
138#define CONFIG_SYS_DCSRBAR 0xf0000000
139#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
140
141/*
142 * DDR Setup
143 */
144#define CONFIG_VERY_BIG_RAM
145#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
147
148/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
149#define CONFIG_DIMM_SLOTS_PER_CTLR 1
150#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
151
152#define CONFIG_DDR_SPD
153#define CONFIG_SYS_DDR_RAW_TIMING
York Sun5614e712013-09-30 09:22:09 -0700154#define CONFIG_SYS_FSL_DDR3
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530155
156#define CONFIG_SYS_SPD_BUS_NUM 0
157#define SPD_EEPROM_ADDRESS 0x51
158
159#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
160
161/*
162 * IFC Definitions
163 */
164#define CONFIG_SYS_FLASH_BASE 0xe8000000
165#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
166
167#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
168#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
169 CSPR_PORT_SIZE_16 | \
170 CSPR_MSEL_NOR | \
171 CSPR_V)
172#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
173/* NOR Flash Timing Params */
174#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
175#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
176 FTIM0_NOR_TEADC(0x5) | \
177 FTIM0_NOR_TEAHC(0x5))
178#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
179 FTIM1_NOR_TRAD_NOR(0x1A) |\
180 FTIM1_NOR_TSEQRAD_NOR(0x13))
181#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
182 FTIM2_NOR_TCH(0x4) | \
183 FTIM2_NOR_TWPH(0x0E) | \
184 FTIM2_NOR_TWP(0x1c))
185#define CONFIG_SYS_NOR_FTIM3 0x0
186
187#define CONFIG_SYS_FLASH_QUIET_TEST
188#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
189
190#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
191#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
192#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
193#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
194
195#define CONFIG_SYS_FLASH_EMPTY_INFO
196#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
197
198/* CPLD on IFC */
199#define CONFIG_SYS_CPLD_BASE 0xffdf0000
200#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
Priyanka Jain9b444be2014-01-27 14:07:11 +0530201#define CONFIG_SYS_CSPR2_EXT (0xf)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530202#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
203 | CSPR_PORT_SIZE_8 \
204 | CSPR_MSEL_GPCM \
205 | CSPR_V)
206#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
207#define CONFIG_SYS_CSOR2 0x0
208/* CPLD Timing parameters for IFC CS2 */
209#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
210 FTIM0_GPCM_TEADC(0x0e) | \
211 FTIM0_GPCM_TEAHC(0x0e))
212#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
213 FTIM1_GPCM_TRAD(0x1f))
214#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
215 FTIM2_GPCM_TCH(0x0) | \
216 FTIM2_GPCM_TWP(0x1f))
217#define CONFIG_SYS_CS2_FTIM3 0x0
218
219/* NAND Flash on IFC */
220#define CONFIG_NAND_FSL_IFC
221#define CONFIG_SYS_NAND_BASE 0xff800000
222#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
223
224#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
225#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
226 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
227 | CSPR_MSEL_NAND /* MSEL = NAND */ \
228 | CSPR_V)
229#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
230
231#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
232 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
233 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
234 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
235 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
236 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
237 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
238
239#define CONFIG_SYS_NAND_ONFI_DETECTION
240
241/* ONFI NAND Flash mode0 Timing Params */
242#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
243 FTIM0_NAND_TWP(0x18) | \
244 FTIM0_NAND_TWCHT(0x07) | \
245 FTIM0_NAND_TWH(0x0a))
246#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
247 FTIM1_NAND_TWBE(0x39) | \
248 FTIM1_NAND_TRR(0x0e) | \
249 FTIM1_NAND_TRP(0x18))
250#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
251 FTIM2_NAND_TREH(0x0a) | \
252 FTIM2_NAND_TWHRE(0x1e))
253#define CONFIG_SYS_NAND_FTIM3 0x0
254
255#define CONFIG_SYS_NAND_DDR_LAW 11
256#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
257#define CONFIG_SYS_MAX_NAND_DEVICE 1
258#define CONFIG_MTD_NAND_VERIFY_WRITE
259#define CONFIG_CMD_NAND
260
261#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
262
263#if defined(CONFIG_NAND)
264#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
265#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
266#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
267#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
268#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
269#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
270#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
271#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
272#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
273#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
274#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
275#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
276#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
277#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
278#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
279#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
280#else
281#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
282#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
283#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
284#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
285#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
286#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
287#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
288#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
289#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
290#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
291#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
292#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
293#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
294#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
295#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
296#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
297#endif
298
299#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
300
301#if defined(CONFIG_RAMBOOT_PBL)
302#define CONFIG_SYS_RAMBOOT
303#endif
304
305#define CONFIG_BOARD_EARLY_INIT_R
306#define CONFIG_MISC_INIT_R
307
308#define CONFIG_HWCONFIG
309
310/* define to use L1 as initial stack */
311#define CONFIG_L1_INIT_RAM
312#define CONFIG_SYS_INIT_RAM_LOCK
313#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
314#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
315#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
316/* The assembler doesn't like typecast */
317#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
318 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
319 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
320#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
321
322#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
323 GENERATED_GBL_DATA_SIZE)
324#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
325
326#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
327#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
328
329/* Serial Port - controlled on board with jumper J8
330 * open - index 2
331 * shorted - index 1
332 */
333#define CONFIG_CONS_INDEX 1
334#define CONFIG_SYS_NS16550
335#define CONFIG_SYS_NS16550_SERIAL
336#define CONFIG_SYS_NS16550_REG_SIZE 1
337#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
338
339#define CONFIG_SYS_BAUDRATE_TABLE \
340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
341
342#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
343#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
344#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
345#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
346#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
347#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
348
349/* Use the HUSH parser */
350#define CONFIG_SYS_HUSH_PARSER
351#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
352
353/* pass open firmware flat tree */
354#define CONFIG_OF_LIBFDT
355#define CONFIG_OF_BOARD_SETUP
356#define CONFIG_OF_STDOUT_VIA_ALIAS
357
358/* new uImage format support */
359#define CONFIG_FIT
360#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
361
362/* I2C */
363#define CONFIG_SYS_I2C
364#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
365#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
366#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
367#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
368#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
369#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
370#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
371
372/* I2C bus multiplexer */
373#define I2C_MUX_PCA_ADDR 0x70
374#define I2C_MUX_CH_DEFAULT 0x8
375
376
377/*
378 * eSPI - Enhanced SPI
379 */
380#define CONFIG_FSL_ESPI
381#define CONFIG_SPI_FLASH
382#define CONFIG_SPI_FLASH_STMICRO
383#define CONFIG_CMD_SF
384#define CONFIG_SF_DEFAULT_SPEED 10000000
385#define CONFIG_SF_DEFAULT_MODE 0
Priyanka Jain9b444be2014-01-27 14:07:11 +0530386#define CONFIG_ENV_SPI_BUS 0
387#define CONFIG_ENV_SPI_CS 0
388#define CONFIG_ENV_SPI_MAX_HZ 10000000
389#define CONFIG_ENV_SPI_MODE 0
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530390
391/*
392 * General PCI
393 * Memory space is mapped 1-1, but I/O space must start from 0.
394 */
395
396#ifdef CONFIG_PCI
397/* controller 1, direct to uli, tgtid 3, Base address 20000 */
398#ifdef CONFIG_PCIE1
399#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
400#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
401#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
402#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
403#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
404#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
405#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
406#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
407#endif
408
409/* controller 2, Slot 2, tgtid 2, Base address 201000 */
410#ifdef CONFIG_PCIE2
411#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
412#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
413#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
414#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
415#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
416#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
417#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
418#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
419#endif
420
421/* controller 3, Slot 1, tgtid 1, Base address 202000 */
422#ifdef CONFIG_PCIE3
423#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
424#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
425#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
426#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
427#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
428#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
429#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
430#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
431#endif
432
433/* controller 4, Base address 203000 */
434#ifdef CONFIG_PCIE4
435#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
436#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
437#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
438#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
439#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
440#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
441#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
442#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
443#endif
444
445#define CONFIG_PCI_PNP /* do pci plug-and-play */
446#define CONFIG_E1000
447
448#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
449#define CONFIG_DOS_PARTITION
450#endif /* CONFIG_PCI */
451
452/* SATA */
453#define CONFIG_FSL_SATA_V2
454#ifdef CONFIG_FSL_SATA_V2
455#define CONFIG_LIBATA
456#define CONFIG_FSL_SATA
457
458#define CONFIG_SYS_SATA_MAX_DEVICE 1
459#define CONFIG_SATA1
460#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
461#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
462
463#define CONFIG_LBA48
464#define CONFIG_CMD_SATA
465#define CONFIG_DOS_PARTITION
466#define CONFIG_CMD_EXT2
467#endif
468
469/*
470* USB
471*/
472#define CONFIG_HAS_FSL_DR_USB
473
474#ifdef CONFIG_HAS_FSL_DR_USB
475#define CONFIG_USB_EHCI
476
477#ifdef CONFIG_USB_EHCI
478#define CONFIG_CMD_USB
479#define CONFIG_USB_STORAGE
480#define CONFIG_USB_EHCI_FSL
481#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
482#define CONFIG_CMD_EXT2
483#endif
484#endif
485
486#define CONFIG_MMC
487
488#ifdef CONFIG_MMC
489#define CONFIG_FSL_ESDHC
490#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
491#define CONFIG_CMD_MMC
492#define CONFIG_GENERIC_MMC
493#define CONFIG_CMD_EXT2
494#define CONFIG_CMD_FAT
495#define CONFIG_DOS_PARTITION
496#endif
497
498/* Qman/Bman */
499#ifndef CONFIG_NOBQFMAN
500#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
501#define CONFIG_SYS_BMAN_NUM_PORTALS 25
502#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
503#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
504#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
505#define CONFIG_SYS_QMAN_NUM_PORTALS 25
506#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
507#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
508#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
509
510#define CONFIG_SYS_DPAA_FMAN
511#define CONFIG_SYS_DPAA_PME
512
513/* Default address of microcode for the Linux Fman driver */
514#if defined(CONFIG_SPIFLASH)
515/*
516 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
517 * env, so we got 0x110000.
518 */
519#define CONFIG_SYS_QE_FW_IN_SPIFLASH
520#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
521#elif defined(CONFIG_SDCARD)
522/*
523 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530524 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
525 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530526 */
527#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530528#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530529#elif defined(CONFIG_NAND)
530#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530531#define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530532#else
533#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530534#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530535#endif
536#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
537#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
538#endif /* CONFIG_NOBQFMAN */
539
540#ifdef CONFIG_SYS_DPAA_FMAN
541#define CONFIG_FMAN_ENET
542#define CONFIG_PHY_VITESSE
543#define CONFIG_PHY_REALTEK
544#endif
545
546#ifdef CONFIG_FMAN_ENET
Priyanka Jain714fd402014-01-30 11:30:04 +0530547#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
548#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
549#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530550
551#define CONFIG_MII /* MII PHY management */
Priyanka Jain714fd402014-01-30 11:30:04 +0530552#define CONFIG_ETHPRIME "FM1@DTSEC4"
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530553#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
554#endif
555
556/*
557 * Environment
558 */
559#define CONFIG_LOADS_ECHO /* echo on for serial download */
560#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
561
562/*
563 * Command line configuration.
564 */
565#include <config_cmd_default.h>
566
567#define CONFIG_CMD_DHCP
568#define CONFIG_CMD_ELF
569#define CONFIG_CMD_ERRATA
570#define CONFIG_CMD_GREPENV
571#define CONFIG_CMD_IRQ
572#define CONFIG_CMD_I2C
573#define CONFIG_CMD_MII
574#define CONFIG_CMD_PING
575#define CONFIG_CMD_REGINFO
576#define CONFIG_CMD_SETEXPR
577
578#ifdef CONFIG_PCI
579#define CONFIG_CMD_PCI
580#define CONFIG_CMD_NET
581#endif
582
583/*
584 * Miscellaneous configurable options
585 */
586#define CONFIG_SYS_LONGHELP /* undef to save memory */
587#define CONFIG_CMDLINE_EDITING /* Command-line editing */
588#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
589#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
590#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
591#ifdef CONFIG_CMD_KGDB
592#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
593#else
594#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
595#endif
596#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
597#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
598#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
599#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
600
601/*
602 * For booting Linux, the board info and command line data
603 * have to be in the first 64 MB of memory, since this is
604 * the maximum mapped by the Linux kernel during initialization.
605 */
606#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
607#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
608
609#ifdef CONFIG_CMD_KGDB
610#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530611#endif
612
613/*
614 * Environment Configuration
615 */
616#define CONFIG_ROOTPATH "/opt/nfsroot"
617#define CONFIG_BOOTFILE "uImage"
618#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
619
620/* default location for tftp and bootm */
621#define CONFIG_LOADADDR 1000000
622
623#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
624
625#define CONFIG_BAUDRATE 115200
626
627#define __USB_PHY_TYPE utmi
628
629#define CONFIG_EXTRA_ENV_SETTINGS \
Priyanka Jain9b444be2014-01-27 14:07:11 +0530630 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
631 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
632 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530633 "netdev=eth0\0" \
634 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
635 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
636 "tftpflash=tftpboot $loadaddr $uboot && " \
637 "protect off $ubootaddr +$filesize && " \
638 "erase $ubootaddr +$filesize && " \
639 "cp.b $loadaddr $ubootaddr $filesize && " \
640 "protect on $ubootaddr +$filesize && " \
641 "cmp.b $loadaddr $ubootaddr $filesize\0" \
642 "consoledev=ttyS0\0" \
643 "ramdiskaddr=2000000\0" \
644 "ramdiskfile=t1040rdb/ramdisk.uboot\0" \
645 "fdtaddr=c00000\0" \
646 "fdtfile=t1040rdb/t1040rdb.dtb\0" \
647 "bdev=sda3\0" \
648 "c=ffe\0"
649
650#define CONFIG_LINUX \
651 "setenv bootargs root=/dev/ram rw " \
652 "console=$consoledev,$baudrate $othbootargs;" \
653 "setenv ramdiskaddr 0x02000000;" \
654 "setenv fdtaddr 0x00c00000;" \
655 "setenv loadaddr 0x1000000;" \
656 "bootm $loadaddr $ramdiskaddr $fdtaddr"
657
658#define CONFIG_HDBOOT \
659 "setenv bootargs root=/dev/$bdev rw " \
660 "console=$consoledev,$baudrate $othbootargs;" \
661 "tftp $loadaddr $bootfile;" \
662 "tftp $fdtaddr $fdtfile;" \
663 "bootm $loadaddr - $fdtaddr"
664
665#define CONFIG_NFSBOOTCOMMAND \
666 "setenv bootargs root=/dev/nfs rw " \
667 "nfsroot=$serverip:$rootpath " \
668 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
669 "console=$consoledev,$baudrate $othbootargs;" \
670 "tftp $loadaddr $bootfile;" \
671 "tftp $fdtaddr $fdtfile;" \
672 "bootm $loadaddr - $fdtaddr"
673
674#define CONFIG_RAMBOOTCOMMAND \
675 "setenv bootargs root=/dev/ram rw " \
676 "console=$consoledev,$baudrate $othbootargs;" \
677 "tftp $ramdiskaddr $ramdiskfile;" \
678 "tftp $loadaddr $bootfile;" \
679 "tftp $fdtaddr $fdtfile;" \
680 "bootm $loadaddr $ramdiskaddr $fdtaddr"
681
682#define CONFIG_BOOTCOMMAND CONFIG_LINUX
683
684#ifdef CONFIG_SECURE_BOOT
685#include <asm/fsl_secure_boot.h>
686#endif
687
688#endif /* __CONFIG_H */