blob: 742bc6b5a21c42b010c83b9a68516036ff665acc [file] [log] [blame]
Haavard Skinnemoen3ace2522008-05-02 15:21:40 +02001/*
2 * Copyright (C) 2005-2008 Atmel Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22#include <common.h>
23
24#include <asm/io.h>
25
26#include <asm/arch/clk.h>
27#include <asm/arch/memory-map.h>
Haavard Skinnemoen98090cd2008-08-31 18:05:32 +020028#include <asm/arch/portmux.h>
Haavard Skinnemoen3ace2522008-05-02 15:21:40 +020029
30#include "sm.h"
31
32void clk_init(void)
33{
34 uint32_t cksel;
35
36 /* in case of soft resets, disable watchdog */
37 sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
38 sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
39
40#ifdef CONFIG_PLL
41 /* Initialize the PLL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES)
43 | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1)
44 | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1)
45 | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT)
Haavard Skinnemoen3ace2522008-05-02 15:21:40 +020046 | SM_BF(PLLOSC, 0)
47 | SM_BIT(PLLEN)));
48
49 /* Wait for lock */
50 while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
51#endif
52
53 /* Set up clocks for the CPU and all peripheral buses */
54 cksel = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055 if (CONFIG_SYS_CLKDIV_CPU)
56 cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1);
57 if (CONFIG_SYS_CLKDIV_HSB)
58 cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1);
59 if (CONFIG_SYS_CLKDIV_PBA)
60 cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1);
61 if (CONFIG_SYS_CLKDIV_PBB)
62 cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1);
Haavard Skinnemoen3ace2522008-05-02 15:21:40 +020063 sm_writel(PM_CKSEL, cksel);
64
65#ifdef CONFIG_PLL
66 /* Use PLL0 as main clock */
67 sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
Mark Jackson716ece12009-07-21 11:11:37 +010068
69#ifdef CONFIG_LCD
70 /* Set up pixel clock for the LCDC */
71 sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN));
72#endif
Haavard Skinnemoen3ace2522008-05-02 15:21:40 +020073#endif
74}
Haavard Skinnemoen98090cd2008-08-31 18:05:32 +020075
76unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
77 unsigned long rate, unsigned long parent_rate)
78{
79 unsigned long divider;
80
81 if (rate == 0 || parent_rate == 0) {
82 sm_writel(PM_GCCTRL(id), 0);
83 return 0;
84 }
85
86 divider = (parent_rate + rate / 2) / rate;
87 if (divider <= 1) {
88 sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
89 rate = parent_rate;
90 } else {
91 divider = min(255, divider / 2 - 1);
92 sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
93 | SM_BF(DIV, divider));
94 rate = parent_rate / (2 * (divider + 1));
95 }
96
97 return rate;
98}