blob: 5daa6b2752c3278fc515b2b587007811b24e9537 [file] [log] [blame]
wdenk0de1ffc2002-10-25 20:52:57 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
wdenk0de1ffc2002-10-25 20:52:57 +000025#include <mpc8xx.h>
26#include <mpc8xx_irq.h>
27#include <asm/processor.h>
28#include <commproc.h>
29
wdenk7c7a23b2002-12-07 00:20:59 +000030/************************************************************************/
wdenk0de1ffc2002-10-25 20:52:57 +000031
wdenk0de1ffc2002-10-25 20:52:57 +000032/*
33 * CPM interrupt vector functions.
34 */
wdenk7c7a23b2002-12-07 00:20:59 +000035struct interrupt_action {
36 interrupt_handler_t *handler;
37 void *arg;
wdenk0de1ffc2002-10-25 20:52:57 +000038};
39
wdenk7c7a23b2002-12-07 00:20:59 +000040static struct interrupt_action cpm_vecs[CPMVEC_NR];
41static struct interrupt_action irq_vecs[NR_IRQS];
wdenk0de1ffc2002-10-25 20:52:57 +000042
43static void cpm_interrupt_init (void);
wdenk7c7a23b2002-12-07 00:20:59 +000044static void cpm_interrupt (void *regs);
wdenk0de1ffc2002-10-25 20:52:57 +000045
wdenk7c7a23b2002-12-07 00:20:59 +000046/************************************************************************/
wdenk0de1ffc2002-10-25 20:52:57 +000047
wdenka8c7c702003-12-06 19:49:23 +000048int interrupt_init_cpu (unsigned *decrementer_count)
wdenk0de1ffc2002-10-25 20:52:57 +000049{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk0de1ffc2002-10-25 20:52:57 +000051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
wdenk0de1ffc2002-10-25 20:52:57 +000053
wdenk7c7a23b2002-12-07 00:20:59 +000054 /* disable all interrupts */
55 immr->im_siu_conf.sc_simask = 0;
wdenk0de1ffc2002-10-25 20:52:57 +000056
wdenk7c7a23b2002-12-07 00:20:59 +000057 /* Configure CPM interrupts */
58 cpm_interrupt_init ();
wdenk0de1ffc2002-10-25 20:52:57 +000059
wdenk0de1ffc2002-10-25 20:52:57 +000060 return (0);
61}
62
wdenk7c7a23b2002-12-07 00:20:59 +000063/************************************************************************/
wdenk0de1ffc2002-10-25 20:52:57 +000064
65/*
66 * Handle external interrupts
67 */
wdenk7c7a23b2002-12-07 00:20:59 +000068void external_interrupt (struct pt_regs *regs)
wdenk0de1ffc2002-10-25 20:52:57 +000069{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk7c7a23b2002-12-07 00:20:59 +000071 int irq;
72 ulong simask, newmask;
73 ulong vec, v_bit;
wdenk0de1ffc2002-10-25 20:52:57 +000074
75 /*
76 * read the SIVEC register and shift the bits down
77 * to get the irq number
78 */
79 vec = immr->im_siu_conf.sc_sivec;
80 irq = vec >> 26;
81 v_bit = 0x80000000UL >> irq;
82
83 /*
84 * Read Interrupt Mask Register and Mask Interrupts
85 */
86 simask = immr->im_siu_conf.sc_simask;
87 newmask = simask & (~(0xFFFF0000 >> irq));
88 immr->im_siu_conf.sc_simask = newmask;
89
wdenk7c7a23b2002-12-07 00:20:59 +000090 if (!(irq & 0x1)) { /* External Interrupt ? */
wdenk0de1ffc2002-10-25 20:52:57 +000091 ulong siel;
wdenk7c7a23b2002-12-07 00:20:59 +000092
wdenk0de1ffc2002-10-25 20:52:57 +000093 /*
94 * Read Interrupt Edge/Level Register
95 */
96 siel = immr->im_siu_conf.sc_siel;
97
wdenk7c7a23b2002-12-07 00:20:59 +000098 if (siel & v_bit) { /* edge triggered interrupt ? */
wdenk0de1ffc2002-10-25 20:52:57 +000099 /*
100 * Rewrite SIPEND Register to clear interrupt
101 */
102 immr->im_siu_conf.sc_sipend = v_bit;
103 }
104 }
105
wdenk7c7a23b2002-12-07 00:20:59 +0000106 if (irq_vecs[irq].handler != NULL) {
107 irq_vecs[irq].handler (irq_vecs[irq].arg);
108 } else {
wdenk0de1ffc2002-10-25 20:52:57 +0000109 printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
wdenk7c7a23b2002-12-07 00:20:59 +0000110 irq, vec);
wdenk0de1ffc2002-10-25 20:52:57 +0000111 /* turn off the bogus interrupt to avoid it from now */
112 simask &= ~v_bit;
wdenk0de1ffc2002-10-25 20:52:57 +0000113 }
wdenk0de1ffc2002-10-25 20:52:57 +0000114 /*
115 * Re-Enable old Interrupt Mask
116 */
117 immr->im_siu_conf.sc_simask = simask;
118}
119
wdenk7c7a23b2002-12-07 00:20:59 +0000120/************************************************************************/
wdenk0de1ffc2002-10-25 20:52:57 +0000121
122/*
123 * CPM interrupt handler
124 */
wdenk7c7a23b2002-12-07 00:20:59 +0000125static void cpm_interrupt (void *regs)
wdenk0de1ffc2002-10-25 20:52:57 +0000126{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk7c7a23b2002-12-07 00:20:59 +0000128 uint vec;
wdenk0de1ffc2002-10-25 20:52:57 +0000129
130 /*
131 * Get the vector by setting the ACK bit
132 * and then reading the register.
133 */
134 immr->im_cpic.cpic_civr = 1;
135 vec = immr->im_cpic.cpic_civr;
136 vec >>= 11;
137
138 if (cpm_vecs[vec].handler != NULL) {
wdenk7c7a23b2002-12-07 00:20:59 +0000139 (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
wdenk0de1ffc2002-10-25 20:52:57 +0000140 } else {
141 immr->im_cpic.cpic_cimr &= ~(1 << vec);
142 printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
143 }
144 /*
wdenk7c7a23b2002-12-07 00:20:59 +0000145 * After servicing the interrupt,
146 * we have to remove the status indicator.
wdenk0de1ffc2002-10-25 20:52:57 +0000147 */
148 immr->im_cpic.cpic_cisr |= (1 << vec);
149}
150
151/*
152 * The CPM can generate the error interrupt when there is a race
153 * condition between generating and masking interrupts. All we have
154 * to do is ACK it and return. This is a no-op function so we don't
155 * need any special tests in the interrupt handler.
156 */
wdenk7c7a23b2002-12-07 00:20:59 +0000157static void cpm_error_interrupt (void *dummy)
wdenk0de1ffc2002-10-25 20:52:57 +0000158{
159}
160
wdenk7c7a23b2002-12-07 00:20:59 +0000161/************************************************************************/
wdenk0de1ffc2002-10-25 20:52:57 +0000162/*
wdenk7c7a23b2002-12-07 00:20:59 +0000163 * Install and free an interrupt handler
wdenk0de1ffc2002-10-25 20:52:57 +0000164 */
wdenk7c7a23b2002-12-07 00:20:59 +0000165void irq_install_handler (int vec, interrupt_handler_t * handler,
166 void *arg)
wdenk0de1ffc2002-10-25 20:52:57 +0000167{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk0de1ffc2002-10-25 20:52:57 +0000169
wdenk7c7a23b2002-12-07 00:20:59 +0000170 if ((vec & CPMVEC_OFFSET) != 0) {
171 /* CPM interrupt */
172 vec &= 0xffff;
173 if (cpm_vecs[vec].handler != NULL) {
174 printf ("CPM interrupt 0x%x replacing 0x%x\n",
175 (uint) handler,
176 (uint) cpm_vecs[vec].handler);
177 }
178 cpm_vecs[vec].handler = handler;
179 cpm_vecs[vec].arg = arg;
180 immr->im_cpic.cpic_cimr |= (1 << vec);
181#if 0
182 printf ("Install CPM interrupt for vector %d ==> %p\n",
183 vec, handler);
184#endif
185 } else {
186 /* SIU interrupt */
187 if (irq_vecs[vec].handler != NULL) {
188 printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
189 vec,
190 (uint) handler,
191 (uint) cpm_vecs[vec].handler);
192 }
193 irq_vecs[vec].handler = handler;
194 irq_vecs[vec].arg = arg;
195 immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
196#if 0
197 printf ("Install SIU interrupt for vector %d ==> %p\n",
198 vec, handler);
199#endif
wdenk0de1ffc2002-10-25 20:52:57 +0000200 }
wdenk0de1ffc2002-10-25 20:52:57 +0000201}
202
wdenk7c7a23b2002-12-07 00:20:59 +0000203void irq_free_handler (int vec)
wdenk0de1ffc2002-10-25 20:52:57 +0000204{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk7c7a23b2002-12-07 00:20:59 +0000206
207 if ((vec & CPMVEC_OFFSET) != 0) {
208 /* CPM interrupt */
209 vec &= 0xffff;
wdenk0de1ffc2002-10-25 20:52:57 +0000210#if 0
wdenk7c7a23b2002-12-07 00:20:59 +0000211 printf ("Free CPM interrupt for vector %d ==> %p\n",
212 vec, cpm_vecs[vec].handler);
wdenk0de1ffc2002-10-25 20:52:57 +0000213#endif
wdenk7c7a23b2002-12-07 00:20:59 +0000214 immr->im_cpic.cpic_cimr &= ~(1 << vec);
215 cpm_vecs[vec].handler = NULL;
216 cpm_vecs[vec].arg = NULL;
217 } else {
218 /* SIU interrupt */
219#if 0
220 printf ("Free CPM interrupt for vector %d ==> %p\n",
221 vec, cpm_vecs[vec].handler);
222#endif
223 immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
224 irq_vecs[vec].handler = NULL;
225 irq_vecs[vec].arg = NULL;
226 }
wdenk0de1ffc2002-10-25 20:52:57 +0000227}
228
wdenk7c7a23b2002-12-07 00:20:59 +0000229/************************************************************************/
wdenk0de1ffc2002-10-25 20:52:57 +0000230
wdenk7c7a23b2002-12-07 00:20:59 +0000231static void cpm_interrupt_init (void)
wdenk0de1ffc2002-10-25 20:52:57 +0000232{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk0de1ffc2002-10-25 20:52:57 +0000234
235 /*
236 * Initialize the CPM interrupt controller.
237 */
238
239 immr->im_cpic.cpic_cicr =
wdenk7c7a23b2002-12-07 00:20:59 +0000240 (CICR_SCD_SCC4 |
241 CICR_SCC_SCC3 |
242 CICR_SCB_SCC2 |
243 CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
wdenk0de1ffc2002-10-25 20:52:57 +0000244
245 immr->im_cpic.cpic_cimr = 0;
246
247 /*
248 * Install the error handler.
249 */
wdenk7c7a23b2002-12-07 00:20:59 +0000250 irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
wdenk0de1ffc2002-10-25 20:52:57 +0000251
252 immr->im_cpic.cpic_cicr |= CICR_IEN;
wdenk7c7a23b2002-12-07 00:20:59 +0000253
254 /*
255 * Install the cpm interrupt handler
256 */
257 irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
wdenk0de1ffc2002-10-25 20:52:57 +0000258}
259
wdenk7c7a23b2002-12-07 00:20:59 +0000260/************************************************************************/
wdenk0de1ffc2002-10-25 20:52:57 +0000261
wdenk0de1ffc2002-10-25 20:52:57 +0000262/*
263 * timer_interrupt - gets called when the decrementer overflows,
264 * with interrupts disabled.
265 * Trivial implementation - no need to be really accurate.
266 */
wdenka8c7c702003-12-06 19:49:23 +0000267void timer_interrupt_cpu (struct pt_regs *regs)
wdenk0de1ffc2002-10-25 20:52:57 +0000268{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk7c7a23b2002-12-07 00:20:59 +0000270
wdenk0de1ffc2002-10-25 20:52:57 +0000271#if 0
272 printf ("*** Timer Interrupt *** ");
273#endif
274 /* Reset Timer Expired and Timers Interrupt Status */
275 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
wdenk7c7a23b2002-12-07 00:20:59 +0000276 __asm__ ("nop");
wdenk180d3f72004-01-04 16:28:35 +0000277 /*
278 Clear TEXPS (and TMIST on older chips). SPLSS (on older
279 chips) is cleared too.
280
281 Bitwise OR is a read-modify-write operation so ALL bits
282 which are cleared by writing `1' would be cleared by
283 operations like
284
285 immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
286
287 The same can be achieved by simple writing of the PLPRCR
288 to itself. If a bit value should be preserved, read the
289 register, ZERO the bit and write, not OR, the result back.
290 */
291 immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr;
wdenk0de1ffc2002-10-25 20:52:57 +0000292}
293
wdenk7c7a23b2002-12-07 00:20:59 +0000294/************************************************************************/