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Vignesh R778572d2019-02-05 11:29:25 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 *
4 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
5 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com>
6 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
7 */
8
9#include <common.h>
10#include <spi.h>
11#include <spi_flash.h>
12
13#include "sf_internal.h"
14
15/* Exclude chip names for SPL to save space */
16#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY)
17#define INFO_NAME(_name) .name = _name,
18#else
19#define INFO_NAME(_name)
20#endif
21
22/* Used when the "_ext_id" is two bytes at most */
23#define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
24 INFO_NAME(_name) \
25 .id = { \
26 ((_jedec_id) >> 16) & 0xff, \
27 ((_jedec_id) >> 8) & 0xff, \
28 (_jedec_id) & 0xff, \
29 ((_ext_id) >> 8) & 0xff, \
30 (_ext_id) & 0xff, \
31 }, \
32 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
33 .sector_size = (_sector_size), \
34 .n_sectors = (_n_sectors), \
35 .page_size = 256, \
36 .flags = (_flags),
37
38#define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
39 INFO_NAME(_name) \
40 .id = { \
41 ((_jedec_id) >> 16) & 0xff, \
42 ((_jedec_id) >> 8) & 0xff, \
43 (_jedec_id) & 0xff, \
44 ((_ext_id) >> 16) & 0xff, \
45 ((_ext_id) >> 8) & 0xff, \
46 (_ext_id) & 0xff, \
47 }, \
48 .id_len = 6, \
49 .sector_size = (_sector_size), \
50 .n_sectors = (_n_sectors), \
51 .page_size = 256, \
52 .flags = (_flags),
53
54/* NOTE: double check command sets and memory organization when you add
55 * more nor chips. This current list focusses on newer chips, which
56 * have been converging on command sets which including JEDEC ID.
57 *
58 * All newly added entries should describe *hardware* and should use SECT_4K
59 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
60 * scenarios excluding small sectors there is config option that can be
61 * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
62 * For historical (and compatibility) reasons (before we got above config) some
63 * old entries may be missing 4K flag.
64 */
65const struct flash_info spi_nor_ids[] = {
66#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
67 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
68 { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
69 { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
70
71 { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
72 { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
73 { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
74 { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
75 { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
76 { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
77 { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
78 { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
79#endif
80#ifdef CONFIG_SPI_FLASH_EON /* EON */
81 /* EON -- en25xxx */
82 { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
83 { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
84 { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
85 { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
86#endif
87#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
88 /* GigaDevice */
89 {
90 INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32,
91 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
92 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
93 },
94 {
95 INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64,
96 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
97 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
98 },
99 {
100 INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64,
101 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
102 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
103 },
104 {
105 INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128,
106 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
107 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
108 },
Neil Armstrong30b9a282019-04-12 11:50:10 +0200109 {
110 INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
111 SECT_4K | SPI_NOR_DUAL_READ |
112 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
113 },
Vignesh R778572d2019-02-05 11:29:25 +0530114#endif
115#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
116 /* ISSI */
117 { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
118 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
119 { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
120 { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
121 { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
122 SECT_4K | SPI_NOR_DUAL_READ) },
123 { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
124 SECT_4K | SPI_NOR_DUAL_READ) },
125 { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
126 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
127 { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
128 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
129 { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
130 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
131#endif
132#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
133 /* Macronix */
134 { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) },
135 { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) },
136 { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) },
137 { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) },
138 { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) },
139 { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
140 { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
141 { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
142 { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
143 { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
144 { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
145 { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
146 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
147 { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
148 { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
149 { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
Marek Vasut3d2f12c2019-03-07 23:27:46 +0100150 { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
Vignesh R778572d2019-02-05 11:29:25 +0530151 { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
152 { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
153#endif
154
155#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
156 /* Micron */
157 { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
158 { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
159 { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
160 { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
161 { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
162 { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
163 { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
164 { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
165 { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
Ashish Kumar83855202019-07-17 11:45:00 +0530166 { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
167 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
Vignesh R778572d2019-02-05 11:29:25 +0530168 { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
169 { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
170 { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
171 { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
172 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
Ashish Kumar9454fee2019-07-18 16:43:15 +0530173 { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_4B_OPCODES) },
174 { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_4B_OPCODES) },
Vignesh R778572d2019-02-05 11:29:25 +0530175#endif
176#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
177 /* Spansion/Cypress -- single (large) sector size only, at least
178 * for the chips listed here (without boot sectors).
179 */
180 { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
181 { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
182 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
183 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
184 { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
185 { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
186 { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
187 { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
188 { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) },
189 { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) },
190 { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
191 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
192 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
193 { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) },
194 { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) },
195 { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) },
196 { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) },
197 { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
198 { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) },
199 { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },
Heiko Schochera2dc8b12019-02-08 11:03:39 +0100200 { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
Vignesh R778572d2019-02-05 11:29:25 +0530201 { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
202#endif
203#ifdef CONFIG_SPI_FLASH_SST /* SST */
204 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
205 { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
206 { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
207 { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
208 { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
209 { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
210 { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
211 { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
212 { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
213 { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) },
214 { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) },
215 { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
216 { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
Eugeniy Paltsev718fd832019-09-09 22:33:15 +0300217 { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
218 { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
219 { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
220 { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
Vignesh R778572d2019-02-05 11:29:25 +0530221#endif
222#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
223 /* ST Microelectronics -- newer production may have feature updates */
224 { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) },
225 { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) },
226 { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) },
227 { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) },
228 { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) },
229 { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) },
230 { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) },
231 { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) },
232 { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) },
233 { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
234 { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) },
235#endif
236#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
237 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
238 { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) },
239 { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) },
240 { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) },
241 { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) },
242 { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) },
243 { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) },
244 {
245 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32,
246 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
247 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
248 },
249 { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) },
250 { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },
251 { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },
252 { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },
253 { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
254 {
255 INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64,
256 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
257 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
258 },
259 {
260 INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64,
261 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
262 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
263 },
264 { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },
265 {
266 INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128,
267 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
268 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
269 },
270 {
271 INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128,
272 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
273 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
274 },
275 {
276 INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256,
277 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
278 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
279 },
280 {
281 INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256,
282 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
283 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
284 },
285 {
286 INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512,
287 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
288 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
289 },
290 {
291 INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512,
292 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
293 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
294 },
295 { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
296 { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
297 { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
298 { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
299 { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
300 { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
301#endif
302#ifdef CONFIG_SPI_FLASH_XMC
303 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
304 { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
305 { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
306#endif
307 { },
308};