blob: 110c1d78fbc67e38158bba0413b1fc85f76b46f2 [file] [log] [blame]
Alex Marginean120b5ef2019-07-03 12:11:40 +03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * ENETC ethernet controller driver
4 * Copyright 2017-2019 NXP
5 */
6
7#ifndef _ENETC_H
8#define _ENETC_H
9
Simon Glasscd93d622020-05-10 11:40:13 -060010#include <linux/bitops.h>
Alex Marginean120b5ef2019-07-03 12:11:40 +030011#define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
12
13/* PCI function IDs */
14#define PCI_DEVICE_ID_ENETC_ETH 0xE100
Alex Marginean1d995342019-07-03 12:11:41 +030015#define PCI_DEVICE_ID_ENETC_MDIO 0xEE01
Alex Marginean120b5ef2019-07-03 12:11:40 +030016
17/* ENETC Ethernet controller registers */
18/* Station interface register offsets */
19#define ENETC_SIMR 0x000
20#define ENETC_SIMR_EN BIT(31)
21#define ENETC_SICAR0 0x040
22/* write cache cfg: snoop, no allocate, data & BD coherent */
23#define ENETC_SICAR_WR_CFG 0x6767
24/* read cache cfg: coherent copy, look up, don't alloc in cache */
25#define ENETC_SICAR_RD_CFG 0x27270000
26#define ENETC_SIROCT 0x300
27#define ENETC_SIRFRM 0x308
28#define ENETC_SITOCT 0x320
29#define ENETC_SITFRM 0x328
30
31/* Rx/Tx Buffer Descriptor Ring registers */
32enum enetc_bdr_type {TX, RX};
33#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
34#define ENETC_BDR_IDX_MASK 0xffff
35
36/* Rx BDR reg offsets */
37#define ENETC_RBMR 0x00
38#define ENETC_RBMR_EN BIT(31)
39#define ENETC_RBBSR 0x08
40/* initial consumer index for Rx BDR */
41#define ENETC_RBCIR 0x0c
42#define ENETC_RBBAR0 0x10
43#define ENETC_RBBAR1 0x14
44#define ENETC_RBPIR 0x18
45#define ENETC_RBLENR 0x20
46
47/* Tx BDR reg offsets */
48#define ENETC_TBMR 0x00
49#define ENETC_TBMR_EN BIT(31)
50#define ENETC_TBBAR0 0x10
51#define ENETC_TBBAR1 0x14
52#define ENETC_TBPIR 0x18
53#define ENETC_TBCIR 0x1c
54#define ENETC_TBLENR 0x20
55
56/* Port registers offset */
57#define ENETC_PORT_REGS_OFF 0x10000
58
59/* Port registers */
60#define ENETC_PMR 0x0000
61#define ENETC_PMR_SI0_EN BIT(16)
62#define ENETC_PSIPMMR 0x0018
63#define ENETC_PSIPMAR0 0x0100
64#define ENETC_PSIPMAR1 0x0104
Alex Margineane4aafd52019-07-03 12:11:42 +030065#define ENETC_PCAPR0 0x0900
66#define ENETC_PCAPRO_MDIO BIT(11)
Alex Marginean120b5ef2019-07-03 12:11:40 +030067#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
68#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
69#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
70/* MAC configuration */
71#define ENETC_PM_CC 0x8008
72#define ENETC_PM_CC_DEFAULT 0x0810
73#define ENETC_PM_CC_RX_TX_EN 0x8813
74#define ENETC_PM_MAXFRM 0x8014
75#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
Alex Margineane4aafd52019-07-03 12:11:42 +030076#define ENETC_PM_IMDIO_BASE 0x8030
77#define ENETC_PM_IF_MODE 0x8300
78#define ENETC_PM_IF_MODE_RG BIT(2)
79#define ENETC_PM_IF_MODE_AN_ENA BIT(15)
80#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0)
Alex Marginean120b5ef2019-07-03 12:11:40 +030081
82/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
83#define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
84#define ENETC_BD_ALIGN 128
85
86/* single pair of Rx/Tx rings */
87#define ENETC_RX_BDR_CNT 1
88#define ENETC_TX_BDR_CNT 1
89#define ENETC_RX_BDR_ID 0
90#define ENETC_TX_BDR_ID 0
91
92/* Tx buffer descriptor */
93struct enetc_tx_bd {
94 __le64 addr;
95 __le16 buf_len;
96 __le16 frm_len;
97 __le16 err_csum;
98 __le16 flags;
99};
100
101#define ENETC_TXBD_FLAGS_F BIT(15)
102#define ENETC_POLL_TRIES 32000
103
104/* Rx buffer descriptor */
105union enetc_rx_bd {
106 /* SW provided BD format */
107 struct {
108 __le64 addr;
109 u8 reserved[8];
110 } w;
111
112 /* ENETC returned BD format */
113 struct {
114 __le16 inet_csum;
115 __le16 parse_summary;
116 __le32 rss_hash;
117 __le16 buf_len;
118 __le16 vlan_opt;
119 union {
120 struct {
121 __le16 flags;
122 __le16 error;
123 };
124 __le32 lstatus;
125 };
126 } r;
127};
128
129#define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
130#define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
131#define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
132#define ENETC_RXBD_STATUS(flags) ((flags) << 16)
133
134/* Tx/Rx ring info */
135struct bd_ring {
136 void *cons_idx;
137 void *prod_idx;
138 /* next BD index to use */
139 int next_prod_idx;
140 int next_cons_idx;
141 int bd_count;
142};
143
144/* ENETC private structure */
145struct enetc_priv {
146 struct enetc_tx_bd *enetc_txbd;
147 union enetc_rx_bd *enetc_rxbd;
148
149 void *regs_base; /* base ENETC registers */
150 void *port_regs; /* base ENETC port registers */
151
152 /* Rx/Tx buffer descriptor rings info */
153 struct bd_ring tx_bdr;
154 struct bd_ring rx_bdr;
Alex Marginean1d995342019-07-03 12:11:41 +0300155
156 int if_type;
Alex Margineane4aafd52019-07-03 12:11:42 +0300157 struct mii_dev imdio;
Alex Marginean17bd7ea2019-11-25 17:15:13 +0200158 struct phy_device *phy;
Alex Marginean120b5ef2019-07-03 12:11:40 +0300159};
160
161/* register accessors */
162#define enetc_read_reg(x) readl((x))
163#define enetc_write_reg(x, val) writel((val), (x))
164#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
165#define enetc_write(priv, off, v) \
166 enetc_write_reg((priv)->regs_base + (off), v)
167
168/* port register accessors */
169#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
170#define enetc_read_port(priv, off) \
171 enetc_read_reg(enetc_port_regs((priv), (off)))
172#define enetc_write_port(priv, off, v) \
173 enetc_write_reg(enetc_port_regs((priv), (off)), v)
174
175/* BDR register accessors, see ENETC_BDR() */
176#define enetc_bdr_read(priv, t, n, off) \
177 enetc_read(priv, ENETC_BDR(t, n, off))
178#define enetc_bdr_write(priv, t, n, off, val) \
179 enetc_write(priv, ENETC_BDR(t, n, off), val)
180
Alex Margineane4aafd52019-07-03 12:11:42 +0300181/* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
182#define ENETC_PCS_PHY_ADDR 0
183
184/* PCS registers */
185#define ENETC_PCS_CR 0x00
186#define ENETC_PCS_CR_RESET_AN 0x1200
187#define ENETC_PCS_CR_DEF_VAL 0x0140
Alex Marginean9bc07e812019-07-15 11:48:47 +0300188#define ENETC_PCS_CR_RST BIT(15)
Alex Margineane4aafd52019-07-03 12:11:42 +0300189#define ENETC_PCS_DEV_ABILITY 0x04
190#define ENETC_PCS_DEV_ABILITY_SGMII 0x4001
191#define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001
192#define ENETC_PCS_LINK_TIMER1 0x12
193#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
194#define ENETC_PCS_LINK_TIMER2 0x13
195#define ENETC_PCS_LINK_TIMER2_VAL 0x0003
196#define ENETC_PCS_IF_MODE 0x14
Alex Marginean9bc07e812019-07-15 11:48:47 +0300197#define ENETC_PCS_IF_MODE_SGMII BIT(0)
198#define ENETC_PCS_IF_MODE_SGMII_AN BIT(1)
199#define ENETC_PCS_IF_MODE_SPEED_1G BIT(3)
Alex Margineane4aafd52019-07-03 12:11:42 +0300200
201/* PCS replicator block for USXGMII */
202#define ENETC_PCS_DEVAD_REPL 0x1f
203
Alex Marginean71a2d1e2021-01-25 14:23:55 +0200204#define ENETC_PCS_REPL_LINK_TIMER_1 0x12
205#define ENETC_PCS_REPL_LINK_TIMER_1_DEF 0x0003
206#define ENETC_PCS_REPL_LINK_TIMER_2 0x13
207#define ENETC_PCS_REPL_LINK_TIMER_2_DEF 0x06a0
208
Alex Marginean1d995342019-07-03 12:11:41 +0300209/* ENETC external MDIO registers */
210#define ENETC_MDIO_BASE 0x1c00
211#define ENETC_MDIO_CFG 0x00
212#define ENETC_EMDIO_CFG_C22 0x00809508
213#define ENETC_EMDIO_CFG_C45 0x00809548
214#define ENETC_EMDIO_CFG_RD_ER BIT(1)
215#define ENETC_EMDIO_CFG_BSY BIT(0)
216#define ENETC_MDIO_CTL 0x04
217#define ENETC_MDIO_CTL_READ BIT(15)
218#define ENETC_MDIO_DATA 0x08
219#define ENETC_MDIO_STAT 0x0c
220
221#define ENETC_MDIO_READ_ERR 0xffff
222
223struct enetc_mdio_priv {
224 void *regs_base;
225};
226
Alex Margineane4aafd52019-07-03 12:11:42 +0300227/*
228 * these functions are implemented by ENETC_MDIO and are re-used by ENETC driver
229 * to drive serdes / internal SoC PHYs
230 */
231int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
232 int reg);
233int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
234 int reg, u16 val);
235
Alex Marginean9c2aee12019-12-10 16:55:39 +0200236/* sets up primary MAC addresses in DT/IERB */
237void fdt_fixup_enetc_mac(void *blob);
238
Alex Marginean120b5ef2019-07-03 12:11:40 +0300239#endif /* _ENETC_H */