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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 71b358cc26792889bbac35054d8e89d59b3fabc4 / . / cpu / mcf5445x / start.S
blob: 26fb2ce0cbd8933407fb19830358fe83eadf5c98 [file] [log] [blame]
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]25#include <timestamp.h>
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]26#include "version.h"
27
28#ifndef CONFIG_IDENT_STRING
29#define CONFIG_IDENT_STRING ""
30#endif
31
32/* last three long word reserved for cache status */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]33#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
34#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
35#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]36
37#define _START _start
38#define _FAULT _fault
39
40#define SAVE_ALL \
41 move.w #0x2700,%sr; /* disable intrs */ \
42 subl #60,%sp; /* space for 15 regs */ \
43 moveml %d0-%d7/%a0-%a6,%sp@;
44
45#define RESTORE_ALL \
46 moveml %sp@,%d0-%d7/%a0-%a6; \
47 addl #60,%sp; /* space for 15 regs */ \
48 rte;
49
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]50#if defined(CONFIG_CF_SBF)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]51#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
52#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]53#endif
54
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]55.text
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]56
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]57/*
58 * Vector table. This is used for initial platform startup.
59 * These vectors are to catch any un-intended traps.
60 */
61_vectors:
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]62#if defined(CONFIG_CF_SBF)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]63
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]64INITSP: .long 0 /* Initial SP */
65INITPC: .long ASM_DRAMINIT /* Initial PC */
66
67#else
68
69INITSP: .long 0 /* Initial SP */
70INITPC: .long _START /* Initial PC */
71
72#endif
73
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]74vector02: .long _FAULT /* Access Error */
75vector03: .long _FAULT /* Address Error */
76vector04: .long _FAULT /* Illegal Instruction */
77vector05: .long _FAULT /* Reserved */
78vector06: .long _FAULT /* Reserved */
79vector07: .long _FAULT /* Reserved */
80vector08: .long _FAULT /* Privilege Violation */
81vector09: .long _FAULT /* Trace */
82vector0A: .long _FAULT /* Unimplemented A-Line */
83vector0B: .long _FAULT /* Unimplemented F-Line */
84vector0C: .long _FAULT /* Debug Interrupt */
85vector0D: .long _FAULT /* Reserved */
86vector0E: .long _FAULT /* Format Error */
87vector0F: .long _FAULT /* Unitialized Int. */
88
89/* Reserved */
90vector10_17:
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92
93vector18: .long _FAULT /* Spurious Interrupt */
94vector19: .long _FAULT /* Autovector Level 1 */
95vector1A: .long _FAULT /* Autovector Level 2 */
96vector1B: .long _FAULT /* Autovector Level 3 */
97vector1C: .long _FAULT /* Autovector Level 4 */
98vector1D: .long _FAULT /* Autovector Level 5 */
99vector1E: .long _FAULT /* Autovector Level 6 */
100vector1F: .long _FAULT /* Autovector Level 7 */
101
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]102#if !defined(CONFIG_CF_SBF)
103
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]104/* TRAP #0 - #15 */
105vector20_2F:
106.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108
109/* Reserved */
110vector30_3F:
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113
114vector64_127:
115.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
116.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
122.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
123
124vector128_191:
125.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
126.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
127.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
128.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
129.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
130.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
131.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
132.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
133
134vector192_255:
135.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
136.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
137.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
138.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
139.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
140.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
141.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
142.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]143#endif
144
145#if defined(CONFIG_CF_SBF)
146 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
147asm_sbf_img_hdr:
148 .long 0x00000000 /* checksum, not yet implemented */
149 .long 0x00030000 /* image length */
150 .long TEXT_BASE /* image to be relocated at */
151
152asm_dram_init:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]153 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]154 movec %d0, %RAMBAR1 /* init Rambar */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]155 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]156 clr.l %sp@-
157
158 /* Must disable global address */
159 move.l #0xFC008000, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]160 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]161 move.l #0xFC008008, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]162 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]163 move.l #0xFC008004, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]164 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]165
166 /*
167 * Dram Initialization
168 * a1, a2, and d0
169 */
170 /* mscr sdram */
171 move.l #0xFC0A4074, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]172 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]173 nop
174
175 /* SDRAM Chip 0 and 1 */
176 move.l #0xFC0B8110, %a1
177 move.l #0xFC0B8114, %a2
178
179 /* calculate the size */
180 move.l #0x13, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]181 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
182#ifdef CONFIG_SYS_SDRAM_BASE1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]183 lsr.l #1, %d2
184#endif
185
186dramsz_loop:
187 lsr.l #1, %d2
188 add.l #1, %d1
189 cmp.l #1, %d2
190 bne dramsz_loop
191
192 /* SDRAM Chip 0 and 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]193 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]194 or.l %d1, (%a1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]195#ifdef CONFIG_SYS_SDRAM_BASE1
196 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]197 or.l %d1, (%a2)
198#endif
199 nop
200
201 /* dram cfg1 and cfg2 */
202 move.l #0xFC0B8008, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]203 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]204 nop
205 move.l #0xFC0B800C, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]206 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]207 nop
208
209 move.l #0xFC0B8000, %a1 /* Mode */
210 move.l #0xFC0B8004, %a2 /* Ctrl */
211
212#ifdef CONFIG_M54455EVB
213 /* Issue PALL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]214 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]215 nop
216
217 /* Issue LEMR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]218 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]219 nop
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]220 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]221 nop
222
223 move.l #1000, %d0
224wait1000:
225 nop
226 subq.l #1, %d0
227 bne wait1000
228#endif
229
230 /* Issue PALL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]231 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]232 nop
233
234 /* Perform two refresh cycles */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]235 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]236 nop
237 move.l %d0, (%a2)
238 move.l %d0, (%a2)
239 nop
240
241#ifdef CONFIG_M54455EVB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]242 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]243 nop
244#elif defined(CONFIG_M54451EVB)
245 /* Issue LEMR */
TsiChung Liewc3a9e632009-02-18 11:49:31 +0000[diff] [blame]246 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]247 nop
TsiChung Liewc3a9e632009-02-18 11:49:31 +0000[diff] [blame]248 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]249 nop
250#endif
251
252 move.l #500, %d0
253wait500:
254 nop
255 subq.l #1, %d0
256 bne wait500
257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]258 move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]259 and.l #0x7FFFFFFF, %d0
260#ifdef CONFIG_M54455EVB
261 or.l #0x10000c00, %d0
262#elif defined(CONFIG_M54451EVB)
263 or.l #0x10000000, %d0
264#endif
265 move.l %d0, (%a2)
266 nop
267
268 /*
269 * DSPI Initialization
270 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
271 * a1 - dspi status
272 * a2 - dtfr
273 * a3 - drfr
274 * a4 - Dst addr
275 */
276 /* Enable pins for DSPI mode - chip-selects are enabled later */
277 move.l #0xFC0A4063, %a0
278 move.b #0x7F, (%a0)
279
280 /* Configure DSPI module */
281 move.l #0xFC05C000, %a0
282 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
283
284 move.l #0xFC05C00C, %a0
285 move.l #0x3E000011, (%a0)
286
287 move.l #0xFC05C034, %a2 /* dtfr */
288 move.l #0xFC05C03B, %a3 /* drfr */
289
290 move.l #(ASM_SBF_IMG_HDR + 4), %a1
291 move.l (%a1)+, %d5
292 move.l (%a1), %a4
293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]294 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
295 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]296
297 move.l #0xFC05C02C, %a1 /* dspi status */
298
299 /* Issue commands and address */
300 move.l #0x8002000B, %d2 /* Fast Read Cmd */
301 jsr asm_dspi_wr_status
302 jsr asm_dspi_rd_status
303
304 move.l #0x80020000, %d2 /* Address byte 2 */
305 jsr asm_dspi_wr_status
306 jsr asm_dspi_rd_status
307
308 move.l #0x80020000, %d2 /* Address byte 1 */
309 jsr asm_dspi_wr_status
310 jsr asm_dspi_rd_status
311
312 move.l #0x80020000, %d2 /* Address byte 0 */
313 jsr asm_dspi_wr_status
314 jsr asm_dspi_rd_status
315
316 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
317 jsr asm_dspi_wr_status
318 jsr asm_dspi_rd_status
319
320 /* Transfer serial boot header to sram */
321asm_dspi_rd_loop1:
322 move.l #0x80020000, %d2
323 jsr asm_dspi_wr_status
324 jsr asm_dspi_rd_status
325
326 move.b %d1, (%a0) /* read, copy to dst */
327
328 add.l #1, %a0 /* inc dst by 1 */
329 sub.l #1, %d4 /* dec cnt by 1 */
330 bne asm_dspi_rd_loop1
331
332 /* Transfer u-boot from serial flash to memory */
333asm_dspi_rd_loop2:
334 move.l #0x80020000, %d2
335 jsr asm_dspi_wr_status
336 jsr asm_dspi_rd_status
337
338 move.b %d1, (%a4) /* read, copy to dst */
339
340 add.l #1, %a4 /* inc dst by 1 */
341 sub.l #1, %d5 /* dec cnt by 1 */
342 bne asm_dspi_rd_loop2
343
344 move.l #0x00020000, %d2 /* Terminate */
345 jsr asm_dspi_wr_status
346 jsr asm_dspi_rd_status
347
348 /* jump to memory and execute */
349 move.l #(TEXT_BASE + 0x400), %a0
350 jmp (%a0)
351
352asm_dspi_wr_status:
353 move.l (%a1), %d0 /* status */
354 and.l #0x0000F000, %d0
355 cmp.l #0x00003000, %d0
356 bgt asm_dspi_wr_status
357
358 move.l %d2, (%a2)
359 rts
360
361asm_dspi_rd_status:
362 move.l (%a1), %d0 /* status */
363 and.l #0x000000F0, %d0
364 lsr.l #4, %d0
365 cmp.l #0, %d0
366 beq asm_dspi_rd_status
367
368 move.b (%a3), %d1
369 rts
370#endif /* CONFIG_CF_SBF */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]371
372 .text
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]373 . = 0x400
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]374 .globl _start
375_start:
376 nop
377 nop
378 move.w #0x2700,%sr /* Mask off Interrupt */
379
380 /* Set vector base register at the beginning of the Flash */
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]381#if defined(CONFIG_CF_SBF)
382 move.l #TEXT_BASE, %d0
383 movec %d0, %VBR
384#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]385 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]386 movec %d0, %VBR
387
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]388 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew225a24b2007-11-07 18:00:54 -0600[diff] [blame]389 movec %d0, %RAMBAR1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]390#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]391
392 /* initialize general use internal ram */
393 move.l #0, %d0
394 move.l #(CACR_STATUS), %a1 /* CACR */
395 move.l #(ICACHE_STATUS), %a2 /* icache */
396 move.l #(DCACHE_STATUS), %a3 /* dcache */
397 move.l %d0, (%a1)
398 move.l %d0, (%a2)
399 move.l %d0, (%a3)
400
401 /* invalidate and disable cache */
402 move.l #0x01004100, %d0 /* Invalidate cache cmd */
403 movec %d0, %CACR /* Invalidate cache */
404 move.l #0, %d0
405 movec %d0, %ACR0
406 movec %d0, %ACR1
407 movec %d0, %ACR2
408 movec %d0, %ACR3
409
410 /* set stackpointer to end of internal ram to get some stackspace for
411 the first c-code */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]412 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]413 clr.l %sp@-
414
415 move.l #__got_start, %a5 /* put relocation table address to a5 */
416
417 bsr cpu_init_f /* run low-level CPU init code (from flash) */
418 bsr board_init_f /* run low-level board init code (from flash) */
419
420 /* board_init_f() does not return */
421
422/*------------------------------------------------------------------------------*/
423
424/*
425 * void relocate_code (addr_sp, gd, addr_moni)
426 *
427 * This "function" does not return, instead it continues in RAM
428 * after relocating the monitor code.
429 *
430 * r3 = dest
431 * r4 = src
432 * r5 = length in bytes
433 * r6 = cachelinesize
434 */
435 .globl relocate_code
436relocate_code:
437 link.w %a6,#0
438 move.l 8(%a6), %sp /* set new stack pointer */
439
440 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
441 move.l 16(%a6), %a0 /* Save copy of Destination Address */
442
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]443 move.l #CONFIG_SYS_MONITOR_BASE, %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]444 move.l #__init_end, %a2
445 move.l %a0, %a3
446
447 /* copy the code to RAM */
4481:
449 move.l (%a1)+, (%a3)+
450 cmp.l %a1,%a2
451 bgt.s 1b
452
453/*
454 * We are done. Do not return, instead branch to second part of board
455 * initialization, now running from RAM.
456 */
457 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]458 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]459 jmp (%a1)
460
461in_ram:
462
463clear_bss:
464 /*
465 * Now clear BSS segment
466 */
467 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]468 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]469 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]470 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]4716:
472 clr.l (%a1)+
473 cmp.l %a1,%d1
474 bgt.s 6b
475
476 /*
477 * fix got table in RAM
478 */
479 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]480 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]481 move.l %a1,%a5 /* * fix got pointer register a5 */
482
483 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]484 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]485
4867:
487 move.l (%a1),%d1
488 sub.l #_start,%d1
489 add.l %a0,%d1
490 move.l %d1,(%a1)+
491 cmp.l %a2, %a1
492 bne 7b
493
494 /* calculate relative jump to board_init_r in ram */
495 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]496 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]497
498 /* set parameters for board_init_r */
499 move.l %a0,-(%sp) /* dest_addr */
500 move.l %d0,-(%sp) /* gd */
501 jsr (%a1)
502
503/*------------------------------------------------------------------------------*/
504/* exception code */
505 .globl _fault
506_fault:
TsiChung Liew3b1e8ac2008-06-18 19:12:13 -0500[diff] [blame]507 bra _fault
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]508 .globl _exc_handler
509
510_exc_handler:
511 SAVE_ALL
512 movel %sp,%sp@-
513 bsr exc_handler
514 addql #4,%sp
515 RESTORE_ALL
516
517 .globl _int_handler
518_int_handler:
519 SAVE_ALL
520 movel %sp,%sp@-
521 bsr int_handler
522 addql #4,%sp
523 RESTORE_ALL
524
525/*------------------------------------------------------------------------------*/
526/* cache functions */
527 .globl icache_enable
528icache_enable:
529 move.l #(CACR_STATUS), %a1 /* read CACR Status */
530 move.l (%a1), %d1
531
532 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]533 movec %d0, %CACR
534
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]535 move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]536 movec %d0, %ACR2
537
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]538 move.l #0x04088020, %d0 /* Enable bcache and icache */
539 movec %d0, %CACR
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]540
541 move.l #(ICACHE_STATUS), %a1
542 moveq #1, %d0
543 move.l %d0, (%a1)
544 rts
545
546 .globl icache_disable
547icache_disable:
548 move.l #(CACR_STATUS), %a1 /* read CACR Status */
549 move.l (%a1), %d0
550
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]551 move.l #0xFFF77BFF, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]552 or.l #0x00040100, %d0 /* Setup cache mask */
553 movec %d0, %CACR /* Invalidate icache */
554 clr.l %d0
555 movec %d0, %ACR2
556 movec %d0, %ACR3
557
558 move.l #(ICACHE_STATUS), %a1
559 moveq #0, %d0
560 move.l %d0, (%a1)
561 rts
562
563 .globl icache_status
564icache_status:
565 move.l #(ICACHE_STATUS), %a1
566 move.l (%a1), %d0
567 rts
568
569 .globl icache_invalid
570icache_invalid:
571 move.l #(CACR_STATUS), %a1 /* read CACR Status */
572 move.l (%a1), %d0
573
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]574 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]575 movec %d0, %CACR /* Enable and invalidate cache */
576 rts
577
578 .globl dcache_enable
579dcache_enable:
580 move.l #(CACR_STATUS), %a1 /* read CACR Status */
581 move.l (%a1), %d1
582
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]583 move.l #0x01040100, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]584 movec %d0, %CACR /* Invalidate dcache */
585
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]586 move.l #0x80088020, %d0 /* Enable bcache and icache */
587 movec %d0, %CACR
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]588
589 move.l #(DCACHE_STATUS), %a1
590 moveq #1, %d0
591 move.l %d0, (%a1)
592 rts
593
594 .globl dcache_disable
595dcache_disable:
596 move.l #(CACR_STATUS), %a1 /* read CACR Status */
597 move.l (%a1), %d0
598
599 and.l #0x7FFFFFFF, %d0
600 or.l #0x01000000, %d0 /* Setup cache mask */
601 movec %d0, %CACR /* Disable dcache */
602 clr.l %d0
603 movec %d0, %ACR0
604 movec %d0, %ACR1
605
606 move.l #(DCACHE_STATUS), %a1
607 moveq #0, %d0
608 move.l %d0, (%a1)
609 rts
610
611 .globl dcache_invalid
612dcache_invalid:
613 move.l #(CACR_STATUS), %a1 /* read CACR Status */
614 move.l (%a1), %d0
615
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600[diff] [blame]616 move.l #0x81088020, %d0 /* Setup cache mask */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]617 movec %d0, %CACR /* Enable and invalidate cache */
618 rts
619
620 .globl dcache_status
621dcache_status:
622 move.l #(DCACHE_STATUS), %a1
623 move.l (%a1), %d0
624 rts
625
626/*------------------------------------------------------------------------------*/
627
628 .globl version_string
629version_string:
630 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]631 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]632 .ascii CONFIG_IDENT_STRING, "\0"
TsiChung Liew9b464322008-03-28 08:47:45 -0500[diff] [blame]633 .align 4