blob: 6b9c34818b35bac94dc4535b273c2d810e6a38b9 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glasse2e947f2015-08-30 16:55:42 -06002/*
3 * (C) Copyright 2015 Google, Inc
Simon Glasse2e947f2015-08-30 16:55:42 -06004 */
5
Kever Yangb678f272019-07-22 20:02:12 +08006#include <clk.h>
Simon Glasse2e947f2015-08-30 16:55:42 -06007#include <common.h>
Kever Yangb678f272019-07-22 20:02:12 +08008#include <dm.h>
Kever Yang02219102019-07-22 20:02:11 +08009#include <asm/arch-rockchip/clock.h>
Kever Yangb678f272019-07-22 20:02:12 +080010#include <dt-bindings/clock/rk3288-cru.h>
Simon Glass61b29b82020-02-03 07:36:15 -070011#include <linux/err.h>
Kever Yangb678f272019-07-22 20:02:12 +080012#include <power/regulator.h>
Simon Glass38ffcb62016-11-13 14:22:11 -070013
14/*
15 * We should increase the DDR voltage to 1.2V using the PWM regulator.
16 * There is a U-Boot driver for this but it may need to add support for the
17 * 'voltage-table' property.
18 */
Kever Yangb678f272019-07-22 20:02:12 +080019#ifndef CONFIG_SPL_BUILD
20#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
21static int veyron_init(void)
22{
23 struct udevice *dev;
24 struct clk clk;
25 int ret;
26
27 ret = regulator_get_by_platname("vdd_arm", &dev);
28 if (ret) {
29 debug("Cannot set regulator name\n");
30 return ret;
31 }
32
33 /* Slowly raise to max CPU voltage to prevent overshoot */
34 ret = regulator_set_value(dev, 1200000);
35 if (ret)
36 return ret;
37 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
38 ret = regulator_set_value(dev, 1400000);
39 if (ret)
40 return ret;
41 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
42
43 ret = rockchip_get_clk(&clk.dev);
44 if (ret)
45 return ret;
46 clk.id = PLL_APLL;
47 ret = clk_set_rate(&clk, 1800000000);
48 if (IS_ERR_VALUE(ret))
49 return ret;
50
51 ret = regulator_get_by_platname("vcc33_sd", &dev);
52 if (ret) {
53 debug("Cannot get regulator name\n");
54 return ret;
55 }
56
57 ret = regulator_set_value(dev, 3300000);
58 if (ret)
59 return ret;
60
61 ret = regulators_enable_boot_on(false);
62 if (ret) {
63 debug("%s: Cannot enable boot on regulators\n", __func__);
64 return ret;
65 }
66
67 return 0;
68}
69#endif
Kever Yang02219102019-07-22 20:02:11 +080070
71int board_early_init_f(void)
72{
73 struct udevice *dev;
74 int ret;
75
Kever Yangb678f272019-07-22 20:02:12 +080076#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
77 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
78 ret = veyron_init();
79 if (ret)
80 return ret;
81 }
82#endif
Kever Yang02219102019-07-22 20:02:11 +080083 /*
84 * This init is done in SPL, but when chain-loading U-Boot SPL will
85 * have been skipped. Allow the clock driver to check if it needs
86 * setting up.
87 */
88 ret = rockchip_get_clk(&dev);
89 if (ret) {
90 debug("CLK init failed: %d\n", ret);
91 return ret;
92 }
93
94 return 0;
95}
Kever Yangb678f272019-07-22 20:02:12 +080096#endif