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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 71f9511803de65a3b98d2f592d418da1d1539f13 / . / include / asm-arm / arch-pxa / mmc.h
blob: 4d61adeaf62e8330df1c5e267e720bf82944aadc [file] [log] [blame]
wdenk71f95112003-06-15 22:40:42 +0000[diff] [blame^]1/*
2 * linux/drivers/mmc/mmc_pxa.h
3 *
4 * Author: Vladimir Shebordaev, Igor Oblakov
5 * Copyright: MontaVista Software Inc.
6 *
7 * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __MMC_PXA_P_H__
14#define __MMC_PXA_P_H__
15
16/* PXA-250 MMC controller registers */
17
18/* MMC_STRPCL */
19#define MMC_STRPCL_STOP_CLK (0x0001UL)
20#define MMC_STRPCL_START_CLK (0x0002UL)
21
22/* MMC_STAT */
23#define MMC_STAT_END_CMD_RES (0x0001UL << 13)
24#define MMC_STAT_PRG_DONE (0x0001UL << 12)
25#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11)
26#define MMC_STAT_CLK_EN (0x0001UL << 8)
27#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7)
28#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6)
29#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5)
30#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4)
31#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3)
32#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2)
33#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1)
34#define MMC_STAT_READ_TIME_OUT (0x0001UL)
35
36#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
37 |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
38 |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
39
40/* MMC_CLKRT */
41#define MMC_CLKRT_20MHZ (0x0000UL)
42#define MMC_CLKRT_10MHZ (0x0001UL)
43#define MMC_CLKRT_5MHZ (0x0002UL)
44#define MMC_CLKRT_2_5MHZ (0x0003UL)
45#define MMC_CLKRT_1_25MHZ (0x0004UL)
46#define MMC_CLKRT_0_625MHZ (0x0005UL)
47#define MMC_CLKRT_0_3125MHZ (0x0006UL)
48
49/* MMC_SPI */
50#define MMC_SPI_DISABLE (0x00UL)
51#define MMC_SPI_EN (0x01UL)
52#define MMC_SPI_CS_EN (0x01UL << 2)
53#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
54#define MMC_SPI_CRC_ON (0x01UL << 1)
55
56/* MMC_CMDAT */
57#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
58#define MMC_CMDAT_INIT (0x0001UL << 6)
59#define MMC_CMDAT_BUSY (0x0001UL << 5)
60#define MMC_CMDAT_STREAM (0x0001UL << 4)
61#define MMC_CMDAT_BLOCK (0x0000UL << 4)
62#define MMC_CMDAT_WRITE (0x0001UL << 3)
63#define MMC_CMDAT_READ (0x0000UL << 3)
64#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
65#define MMC_CMDAT_R1 (0x0001UL)
66#define MMC_CMDAT_R2 (0x0002UL)
67#define MMC_CMDAT_R3 (0x0003UL)
68
69/* MMC_RESTO */
70#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
71
72/* MMC_RDTO */
73#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
74
75/* MMC_BLKLEN */
76#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
77
78/* MMC_PRTBUF */
79#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
80#define MMC_PRTBUF_BUF_FULL (0x00UL )
81
82/* MMC_I_MASK */
83#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6)
84#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5)
85#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
86#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
87#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
88#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
89#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL)
90#define MMC_I_MASK_ALL (0x07fUL)
91
92
93/* MMC_I_REG */
94#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
95#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
96#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
97#define MMC_I_REG_STOP_CMD (0x01UL << 3)
98#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
99#define MMC_I_REG_PRG_DONE (0x01UL << 1)
100#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
101#define MMC_I_REG_ALL (0x007fUL)
102
103/* MMC_CMD */
104#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
105#define CMD(x) (x)
106
107#define MMC_DEFAULT_RCA 1
108
109#define MMC_BLOCK_SIZE 512
110#define MMC_CMD_RESET 0
111#define MMC_CMD_SEND_OP_COND 1
112#define MMC_CMD_ALL_SEND_CID 2
113#define MMC_CMD_SET_RCA 3
114#define MMC_CMD_SEND_CSD 9
115#define MMC_CMD_SEND_CID 10
116#define MMC_CMD_SEND_STATUS 13
117#define MMC_CMD_SET_BLOCKLEN 16
118#define MMC_CMD_READ_BLOCK 17
119#define MMC_CMD_RD_BLK_MULTI 18
120#define MMC_CMD_WRITE_BLOCK 24
121
122#define MMC_MAX_BLOCK_SIZE 512
123
124#define MMC_R1_IDLE_STATE 0x01
125#define MMC_R1_ERASE_STATE 0x02
126#define MMC_R1_ILLEGAL_CMD 0x04
127#define MMC_R1_COM_CRC_ERR 0x08
128#define MMC_R1_ERASE_SEQ_ERR 0x01
129#define MMC_R1_ADDR_ERR 0x02
130#define MMC_R1_PARAM_ERR 0x04
131
132#define MMC_R1B_WP_ERASE_SKIP 0x0002
133#define MMC_R1B_ERR 0x0004
134#define MMC_R1B_CC_ERR 0x0008
135#define MMC_R1B_CARD_ECC_ERR 0x0010
136#define MMC_R1B_WP_VIOLATION 0x0020
137#define MMC_R1B_ERASE_PARAM 0x0040
138#define MMC_R1B_OOR 0x0080
139#define MMC_R1B_IDLE_STATE 0x0100
140#define MMC_R1B_ERASE_RESET 0x0200
141#define MMC_R1B_ILLEGAL_CMD 0x0400
142#define MMC_R1B_COM_CRC_ERR 0x0800
143#define MMC_R1B_ERASE_SEQ_ERR 0x1000
144#define MMC_R1B_ADDR_ERR 0x2000
145#define MMC_R1B_PARAM_ERR 0x4000
146
147typedef struct mmc_cid
148{
149/* FIXME: BYTE_ORDER */
150 uchar year:4,
151 month:4;
152 uchar sn[3];
153 uchar fwrev:4,
154 hwrev:4;
155 uchar name[6];
156 uchar id[3];
157} mmc_cid_t;
158
159typedef struct mmc_csd
160{
161 uchar ecc:2,
162 file_format:2,
163 tmp_write_protect:1,
164 perm_write_protect:1,
165 copy:1,
166 file_format_grp:1;
167 uint64_t content_prot_app:1,
168 rsvd3:4,
169 write_bl_partial:1,
170 write_bl_len:4,
171 r2w_factor:3,
172 default_ecc:2,
173 wp_grp_enable:1,
174 wp_grp_size:5,
175 erase_grp_mult:5,
176 erase_grp_size:5,
177 c_size_mult1:3,
178 vdd_w_curr_max:3,
179 vdd_w_curr_min:3,
180 vdd_r_curr_max:3,
181 vdd_r_curr_min:3,
182 c_size:12,
183 rsvd2:2,
184 dsr_imp:1,
185 read_blk_misalign:1,
186 write_blk_misalign:1,
187 read_bl_partial:1;
188
189 ushort read_bl_len:4,
190 ccc:12;
191 uchar tran_speed;
192 uchar nsac;
193 uchar taac;
194 uchar rsvd1:2,
195 spec_vers:4,
196 csd_structure:2;
197} mmc_csd_t;
198
199
200#endif /* __MMC_PXA_P_H__ */