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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stefan Roese5bef6fd2014-11-07 13:50:31 +01002/*
3 * Designware master SPI core controller driver
4 *
5 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
6 *
Stefan Roesea72f8022014-11-16 12:47:01 +01007 * Very loosely based on the Linux driver:
8 * drivers/spi/spi-dw.c, which is:
Stefan Roese5bef6fd2014-11-07 13:50:31 +01009 * Copyright (c) 2009, Intel Corporation.
Stefan Roese5bef6fd2014-11-07 13:50:31 +010010 */
11
12#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060013#include <log.h>
Horatiu.Vultur@microchip.com1b77de42019-02-25 10:59:54 +000014#include <asm-generic/gpio.h>
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +030015#include <clk.h>
Stefan Roese5bef6fd2014-11-07 13:50:31 +010016#include <dm.h>
17#include <errno.h>
18#include <malloc.h>
19#include <spi.h>
20#include <fdtdec.h>
Ley Foon Tan6ac59092018-09-07 14:25:29 +080021#include <reset.h>
Simon Glass336d4612020-02-03 07:36:16 -070022#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060023#include <linux/bitops.h>
Stefan Roese5bef6fd2014-11-07 13:50:31 +010024#include <linux/compat.h>
Eugeniy Paltsevc6b4f032018-03-22 13:50:43 +030025#include <linux/iopoll.h>
Stefan Roese5bef6fd2014-11-07 13:50:31 +010026#include <asm/io.h>
27
Stefan Roese5bef6fd2014-11-07 13:50:31 +010028/* Register offsets */
29#define DW_SPI_CTRL0 0x00
30#define DW_SPI_CTRL1 0x04
31#define DW_SPI_SSIENR 0x08
32#define DW_SPI_MWCR 0x0c
33#define DW_SPI_SER 0x10
34#define DW_SPI_BAUDR 0x14
35#define DW_SPI_TXFLTR 0x18
36#define DW_SPI_RXFLTR 0x1c
37#define DW_SPI_TXFLR 0x20
38#define DW_SPI_RXFLR 0x24
39#define DW_SPI_SR 0x28
40#define DW_SPI_IMR 0x2c
41#define DW_SPI_ISR 0x30
42#define DW_SPI_RISR 0x34
43#define DW_SPI_TXOICR 0x38
44#define DW_SPI_RXOICR 0x3c
45#define DW_SPI_RXUICR 0x40
46#define DW_SPI_MSTICR 0x44
47#define DW_SPI_ICR 0x48
48#define DW_SPI_DMACR 0x4c
49#define DW_SPI_DMATDLR 0x50
50#define DW_SPI_DMARDLR 0x54
51#define DW_SPI_IDR 0x58
52#define DW_SPI_VERSION 0x5c
53#define DW_SPI_DR 0x60
54
55/* Bit fields in CTRLR0 */
56#define SPI_DFS_OFFSET 0
57
58#define SPI_FRF_OFFSET 4
59#define SPI_FRF_SPI 0x0
60#define SPI_FRF_SSP 0x1
61#define SPI_FRF_MICROWIRE 0x2
62#define SPI_FRF_RESV 0x3
63
64#define SPI_MODE_OFFSET 6
65#define SPI_SCPH_OFFSET 6
66#define SPI_SCOL_OFFSET 7
67
68#define SPI_TMOD_OFFSET 8
69#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
70#define SPI_TMOD_TR 0x0 /* xmit & recv */
71#define SPI_TMOD_TO 0x1 /* xmit only */
72#define SPI_TMOD_RO 0x2 /* recv only */
73#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
74
75#define SPI_SLVOE_OFFSET 10
76#define SPI_SRL_OFFSET 11
77#define SPI_CFS_OFFSET 12
78
79/* Bit fields in SR, 7 bits */
Jagan Teki95e77d92015-10-23 01:01:36 +053080#define SR_MASK GENMASK(6, 0) /* cover 7 bits */
Jagan Teki431a9f02015-10-23 01:36:23 +053081#define SR_BUSY BIT(0)
82#define SR_TF_NOT_FULL BIT(1)
83#define SR_TF_EMPT BIT(2)
84#define SR_RF_NOT_EMPT BIT(3)
85#define SR_RF_FULL BIT(4)
86#define SR_TX_ERR BIT(5)
87#define SR_DCOL BIT(6)
Stefan Roese5bef6fd2014-11-07 13:50:31 +010088
Stefan Roesea72f8022014-11-16 12:47:01 +010089#define RX_TIMEOUT 1000 /* timeout in ms */
Stefan Roese5bef6fd2014-11-07 13:50:31 +010090
91struct dw_spi_platdata {
92 s32 frequency; /* Default clock frequency, -1 for none */
93 void __iomem *regs;
94};
95
96struct dw_spi_priv {
97 void __iomem *regs;
98 unsigned int freq; /* Default frequency */
99 unsigned int mode;
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300100 struct clk clk;
101 unsigned long bus_clk_rate;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100102
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300103 struct gpio_desc cs_gpio; /* External chip-select gpio */
104
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100105 int bits_per_word;
106 u8 cs; /* chip select pin */
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100107 u8 tmode; /* TR/TO/RO/EEPROM */
108 u8 type; /* SPI/SSP/MicroWire */
109 int len;
110
111 u32 fifo_len; /* depth of the FIFO buffer */
112 void *tx;
113 void *tx_end;
114 void *rx;
115 void *rx_end;
Ley Foon Tan6ac59092018-09-07 14:25:29 +0800116
117 struct reset_ctl_bulk resets;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100118};
119
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300120static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100121{
122 return __raw_readl(priv->regs + offset);
123}
124
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300125static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100126{
127 __raw_writel(val, priv->regs + offset);
128}
129
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300130static int request_gpio_cs(struct udevice *bus)
131{
Simon Glassbcee8d62019-12-06 21:41:35 -0700132#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300133 struct dw_spi_priv *priv = dev_get_priv(bus);
134 int ret;
135
136 /* External chip select gpio line is optional */
137 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
138 if (ret == -ENOENT)
139 return 0;
140
141 if (ret < 0) {
142 printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
143 return ret;
144 }
145
146 if (dm_gpio_is_valid(&priv->cs_gpio)) {
147 dm_gpio_set_dir_flags(&priv->cs_gpio,
148 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
149 }
150
151 debug("%s: used external gpio for CS management\n", __func__);
152#endif
153 return 0;
154}
155
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100156static int dw_spi_ofdata_to_platdata(struct udevice *bus)
157{
158 struct dw_spi_platdata *plat = bus->platdata;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100159
Masahiro Yamada3c12c622020-07-17 14:36:46 +0900160 plat->regs = dev_read_addr_ptr(bus);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100161
162 /* Use 500KHz as a suitable default */
Simon Goldschmidt27c3e072019-05-09 22:11:57 +0200163 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
164 500000);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100165 debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
166 plat->frequency);
167
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300168 return request_gpio_cs(bus);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100169}
170
171static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
172{
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300173 dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100174}
175
176/* Restart the controller, disable all interrupts, clean rx fifo */
177static void spi_hw_init(struct dw_spi_priv *priv)
178{
179 spi_enable_chip(priv, 0);
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300180 dw_write(priv, DW_SPI_IMR, 0xff);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100181 spi_enable_chip(priv, 1);
182
183 /*
184 * Try to detect the FIFO depth if not set by interface driver,
185 * the depth could be from 2 to 256 from HW spec
186 */
187 if (!priv->fifo_len) {
188 u32 fifo;
189
Axel Lin52091ad2015-02-26 10:45:22 +0800190 for (fifo = 1; fifo < 256; fifo++) {
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300191 dw_write(priv, DW_SPI_TXFLTR, fifo);
192 if (fifo != dw_read(priv, DW_SPI_TXFLTR))
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100193 break;
194 }
195
Axel Lin52091ad2015-02-26 10:45:22 +0800196 priv->fifo_len = (fifo == 1) ? 0 : fifo;
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300197 dw_write(priv, DW_SPI_TXFLTR, 0);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100198 }
199 debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
200}
201
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300202/*
203 * We define dw_spi_get_clk function as 'weak' as some targets
204 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
205 * and implement dw_spi_get_clk their own way in their clock manager.
206 */
207__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
208{
209 struct dw_spi_priv *priv = dev_get_priv(bus);
210 int ret;
211
212 ret = clk_get_by_index(bus, 0, &priv->clk);
213 if (ret)
214 return ret;
215
216 ret = clk_enable(&priv->clk);
217 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
218 return ret;
219
220 *rate = clk_get_rate(&priv->clk);
221 if (!*rate)
222 goto err_rate;
223
224 debug("%s: get spi controller clk via device tree: %lu Hz\n",
225 __func__, *rate);
226
227 return 0;
228
229err_rate:
230 clk_disable(&priv->clk);
231 clk_free(&priv->clk);
232
233 return -EINVAL;
234}
235
Ley Foon Tan6ac59092018-09-07 14:25:29 +0800236static int dw_spi_reset(struct udevice *bus)
237{
238 int ret;
239 struct dw_spi_priv *priv = dev_get_priv(bus);
240
241 ret = reset_get_bulk(bus, &priv->resets);
242 if (ret) {
243 /*
244 * Return 0 if error due to !CONFIG_DM_RESET and reset
245 * DT property is not present.
246 */
247 if (ret == -ENOENT || ret == -ENOTSUPP)
248 return 0;
249
250 dev_warn(bus, "Can't get reset: %d\n", ret);
251 return ret;
252 }
253
254 ret = reset_deassert_bulk(&priv->resets);
255 if (ret) {
256 reset_release_bulk(&priv->resets);
257 dev_err(bus, "Failed to reset: %d\n", ret);
258 return ret;
259 }
260
261 return 0;
262}
263
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100264static int dw_spi_probe(struct udevice *bus)
265{
266 struct dw_spi_platdata *plat = dev_get_platdata(bus);
267 struct dw_spi_priv *priv = dev_get_priv(bus);
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300268 int ret;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100269
270 priv->regs = plat->regs;
271 priv->freq = plat->frequency;
272
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300273 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
274 if (ret)
275 return ret;
276
Ley Foon Tan6ac59092018-09-07 14:25:29 +0800277 ret = dw_spi_reset(bus);
278 if (ret)
279 return ret;
280
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100281 /* Currently only bits_per_word == 8 supported */
282 priv->bits_per_word = 8;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100283
284 priv->tmode = 0; /* Tx & Rx */
285
286 /* Basic HW init */
287 spi_hw_init(priv);
288
289 return 0;
290}
291
292/* Return the max entries we can fill into tx fifo */
293static inline u32 tx_max(struct dw_spi_priv *priv)
294{
295 u32 tx_left, tx_room, rxtx_gap;
296
Stefan Roesea72f8022014-11-16 12:47:01 +0100297 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300298 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100299
300 /*
301 * Another concern is about the tx/rx mismatch, we
Stefan Roesea72f8022014-11-16 12:47:01 +0100302 * thought about using (priv->fifo_len - rxflr - txflr) as
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100303 * one maximum value for tx, but it doesn't cover the
304 * data which is out of tx/rx fifo and inside the
305 * shift registers. So a control from sw point of
306 * view is taken.
307 */
308 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
Stefan Roesea72f8022014-11-16 12:47:01 +0100309 (priv->bits_per_word >> 3);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100310
311 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
312}
313
314/* Return the max entries we should read out of rx fifo */
315static inline u32 rx_max(struct dw_spi_priv *priv)
316{
Stefan Roesea72f8022014-11-16 12:47:01 +0100317 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100318
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300319 return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100320}
321
322static void dw_writer(struct dw_spi_priv *priv)
323{
324 u32 max = tx_max(priv);
325 u16 txw = 0;
326
327 while (max--) {
328 /* Set the tx word if the transfer's original "tx" is not null */
329 if (priv->tx_end - priv->len) {
Stefan Roesea72f8022014-11-16 12:47:01 +0100330 if (priv->bits_per_word == 8)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100331 txw = *(u8 *)(priv->tx);
332 else
333 txw = *(u16 *)(priv->tx);
334 }
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300335 dw_write(priv, DW_SPI_DR, txw);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100336 debug("%s: tx=0x%02x\n", __func__, txw);
Stefan Roesea72f8022014-11-16 12:47:01 +0100337 priv->tx += priv->bits_per_word >> 3;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100338 }
339}
340
Eugeniy Paltsevd3d8aae2018-03-22 13:50:45 +0300341static void dw_reader(struct dw_spi_priv *priv)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100342{
Eugeniy Paltsevd3d8aae2018-03-22 13:50:45 +0300343 u32 max = rx_max(priv);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100344 u16 rxw;
345
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100346 while (max--) {
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300347 rxw = dw_read(priv, DW_SPI_DR);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100348 debug("%s: rx=0x%02x\n", __func__, rxw);
Stefan Roesea72f8022014-11-16 12:47:01 +0100349
Eugeniy Paltsevd3d8aae2018-03-22 13:50:45 +0300350 /* Care about rx if the transfer's original "rx" is not null */
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100351 if (priv->rx_end - priv->len) {
Stefan Roesea72f8022014-11-16 12:47:01 +0100352 if (priv->bits_per_word == 8)
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100353 *(u8 *)(priv->rx) = rxw;
354 else
355 *(u16 *)(priv->rx) = rxw;
356 }
Stefan Roesea72f8022014-11-16 12:47:01 +0100357 priv->rx += priv->bits_per_word >> 3;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100358 }
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100359}
360
361static int poll_transfer(struct dw_spi_priv *priv)
362{
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100363 do {
364 dw_writer(priv);
Eugeniy Paltsevd3d8aae2018-03-22 13:50:45 +0300365 dw_reader(priv);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100366 } while (priv->rx_end > priv->rx);
367
368 return 0;
369}
370
Gregory CLEMENTbea91b02018-10-09 14:14:07 +0200371/*
372 * We define external_cs_manage function as 'weak' as some targets
373 * (like MSCC Ocelot) don't control the external CS pin using a GPIO
374 * controller. These SoCs use specific registers to control by
375 * software the SPI pins (and especially the CS).
376 */
377__weak void external_cs_manage(struct udevice *dev, bool on)
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300378{
Simon Glassbcee8d62019-12-06 21:41:35 -0700379#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300380 struct dw_spi_priv *priv = dev_get_priv(dev->parent);
381
382 if (!dm_gpio_is_valid(&priv->cs_gpio))
383 return;
384
385 dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
386#endif
387}
388
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100389static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
390 const void *dout, void *din, unsigned long flags)
391{
392 struct udevice *bus = dev->parent;
393 struct dw_spi_priv *priv = dev_get_priv(bus);
394 const u8 *tx = dout;
395 u8 *rx = din;
396 int ret = 0;
397 u32 cr0 = 0;
Eugeniy Paltsevc6b4f032018-03-22 13:50:43 +0300398 u32 val;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100399 u32 cs;
400
401 /* spi core configured to do 8 bit transfers */
402 if (bitlen % 8) {
403 debug("Non byte aligned SPI transfer.\n");
404 return -1;
405 }
406
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300407 /* Start the transaction if necessary. */
408 if (flags & SPI_XFER_BEGIN)
409 external_cs_manage(dev, false);
410
Stefan Roesea72f8022014-11-16 12:47:01 +0100411 cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100412 (priv->mode << SPI_MODE_OFFSET) |
413 (priv->tmode << SPI_TMOD_OFFSET);
414
415 if (rx && tx)
416 priv->tmode = SPI_TMOD_TR;
417 else if (rx)
418 priv->tmode = SPI_TMOD_RO;
419 else
Eugeniy Paltsevfc282c72018-03-22 13:50:44 +0300420 /*
421 * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
422 * any data which breaks our logic in poll_transfer() above.
423 */
424 priv->tmode = SPI_TMOD_TR;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100425
426 cr0 &= ~SPI_TMOD_MASK;
427 cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
428
Stefan Roesea72f8022014-11-16 12:47:01 +0100429 priv->len = bitlen >> 3;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100430 debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
431
432 priv->tx = (void *)tx;
433 priv->tx_end = priv->tx + priv->len;
434 priv->rx = rx;
435 priv->rx_end = priv->rx + priv->len;
436
437 /* Disable controller before writing control registers */
438 spi_enable_chip(priv, 0);
439
440 debug("%s: cr0=%08x\n", __func__, cr0);
441 /* Reprogram cr0 only if changed */
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300442 if (dw_read(priv, DW_SPI_CTRL0) != cr0)
443 dw_write(priv, DW_SPI_CTRL0, cr0);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100444
445 /*
446 * Configure the desired SS (slave select 0...3) in the controller
447 * The DW SPI controller will activate and deactivate this CS
448 * automatically. So no cs_activate() etc is needed in this driver.
449 */
450 cs = spi_chip_select(dev);
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300451 dw_write(priv, DW_SPI_SER, 1 << cs);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100452
453 /* Enable controller after writing control registers */
454 spi_enable_chip(priv, 1);
455
456 /* Start transfer in a polling loop */
457 ret = poll_transfer(priv);
458
Eugeniy Paltsevc6b4f032018-03-22 13:50:43 +0300459 /*
460 * Wait for current transmit operation to complete.
461 * Otherwise if some data still exists in Tx FIFO it can be
462 * silently flushed, i.e. dropped on disabling of the controller,
463 * which happens when writing 0 to DW_SPI_SSIENR which happens
464 * in the beginning of new transfer.
465 */
466 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
Eugeniy Paltsev9b14ac52018-04-19 17:47:41 +0300467 (val & SR_TF_EMPT) && !(val & SR_BUSY),
Eugeniy Paltsevc6b4f032018-03-22 13:50:43 +0300468 RX_TIMEOUT * 1000)) {
469 ret = -ETIMEDOUT;
470 }
471
Eugeniy Paltsevbcdcb3e2018-03-22 13:50:46 +0300472 /* Stop the transaction if necessary */
473 if (flags & SPI_XFER_END)
474 external_cs_manage(dev, true);
475
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100476 return ret;
477}
478
479static int dw_spi_set_speed(struct udevice *bus, uint speed)
480{
481 struct dw_spi_platdata *plat = bus->platdata;
482 struct dw_spi_priv *priv = dev_get_priv(bus);
483 u16 clk_div;
484
485 if (speed > plat->frequency)
486 speed = plat->frequency;
487
488 /* Disable controller before writing control registers */
489 spi_enable_chip(priv, 0);
490
491 /* clk_div doesn't support odd number */
Eugeniy Paltsev58c125b2017-12-28 15:09:03 +0300492 clk_div = priv->bus_clk_rate / speed;
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100493 clk_div = (clk_div + 1) & 0xfffe;
Eugeniy Paltsev4b5f6c52018-03-22 13:50:47 +0300494 dw_write(priv, DW_SPI_BAUDR, clk_div);
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100495
496 /* Enable controller after writing control registers */
497 spi_enable_chip(priv, 1);
498
499 priv->freq = speed;
500 debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
501 priv->freq, clk_div);
502
503 return 0;
504}
505
506static int dw_spi_set_mode(struct udevice *bus, uint mode)
507{
508 struct dw_spi_priv *priv = dev_get_priv(bus);
509
510 /*
511 * Can't set mode yet. Since this depends on if rx, tx, or
512 * rx & tx is requested. So we have to defer this to the
513 * real transfer function.
514 */
515 priv->mode = mode;
516 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
517
518 return 0;
519}
520
Ley Foon Tan6ac59092018-09-07 14:25:29 +0800521static int dw_spi_remove(struct udevice *bus)
522{
523 struct dw_spi_priv *priv = dev_get_priv(bus);
Ley Foon Tane7e05fc2018-09-19 16:27:19 +0800524 int ret;
Ley Foon Tan6ac59092018-09-07 14:25:29 +0800525
Ley Foon Tane7e05fc2018-09-19 16:27:19 +0800526 ret = reset_release_bulk(&priv->resets);
527 if (ret)
528 return ret;
529
530#if CONFIG_IS_ENABLED(CLK)
531 ret = clk_disable(&priv->clk);
532 if (ret)
533 return ret;
534
535 ret = clk_free(&priv->clk);
536 if (ret)
537 return ret;
538#endif
539 return 0;
Ley Foon Tan6ac59092018-09-07 14:25:29 +0800540}
541
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100542static const struct dm_spi_ops dw_spi_ops = {
543 .xfer = dw_spi_xfer,
544 .set_speed = dw_spi_set_speed,
545 .set_mode = dw_spi_set_mode,
546 /*
547 * cs_info is not needed, since we require all chip selects to be
548 * in the device tree explicitly
549 */
550};
551
552static const struct udevice_id dw_spi_ids[] = {
Marek Vasut74114862014-12-31 20:14:55 +0100553 { .compatible = "snps,dw-apb-ssi" },
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100554 { }
555};
556
557U_BOOT_DRIVER(dw_spi) = {
558 .name = "dw_spi",
559 .id = UCLASS_SPI,
560 .of_match = dw_spi_ids,
561 .ops = &dw_spi_ops,
562 .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
563 .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
564 .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100565 .probe = dw_spi_probe,
Ley Foon Tan6ac59092018-09-07 14:25:29 +0800566 .remove = dw_spi_remove,
Stefan Roese5bef6fd2014-11-07 13:50:31 +0100567};