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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
TsiChung Liew05316f82008-08-11 13:41:49 +00002/*
3 * Configuation settings for the Freescale MCF54451 EVB board.
4 *
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChung Liew05316f82008-08-11 13:41:49 +00007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M54451EVB_H
14#define _M54451EVB_H
15
Simon Glass1af3c7f2020-05-10 11:40:09 -060016#include <linux/stringify.h>
17
TsiChung Liew05316f82008-08-11 13:41:49 +000018/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
TsiChung Liew05316f82008-08-11 13:41:49 +000022#define CONFIG_M54451EVB /* M54451EVB board */
23
24#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew05316f82008-08-11 13:41:49 +000026
Angelo Dureghelloc74dda82017-05-14 21:42:27 +020027#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
28
TsiChung Liew05316f82008-08-11 13:41:49 +000029#undef CONFIG_WATCHDOG
30
31#define CONFIG_TIMESTAMP /* Print image info with timestamp */
32
33/*
34 * BOOTP options
35 */
36#define CONFIG_BOOTP_BOOTFILESIZE
TsiChung Liew05316f82008-08-11 13:41:49 +000037
TsiChung Liew05316f82008-08-11 13:41:49 +000038/* Network configuration */
TsiChung Liew05316f82008-08-11 13:41:49 +000039#ifdef CONFIG_MCFFEC
TsiChung Liew05316f82008-08-11 13:41:49 +000040# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041# define CONFIG_SYS_DISCOVER_PHY
42# define CONFIG_SYS_RX_ETH_BUFFER 8
43# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew05316f82008-08-11 13:41:49 +000044# define CONFIG_ETHPRIME "FEC0"
45# define CONFIG_IPADDR 192.162.1.2
46# define CONFIG_NETMASK 255.255.255.0
47# define CONFIG_SERVERIP 192.162.1.1
48# define CONFIG_GATEWAYIP 192.162.1.1
TsiChung Liew05316f82008-08-11 13:41:49 +000049
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
51# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChung Liew05316f82008-08-11 13:41:49 +000052# define FECDUPLEX FULL
53# define FECSPEED _100BASET
54# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
56# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew05316f82008-08-11 13:41:49 +000057# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChung Liew05316f82008-08-11 13:41:49 +000059#endif
60
Mario Six5bc05432018-03-28 14:38:20 +020061#define CONFIG_HOSTNAME "M54451EVB"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#ifdef CONFIG_SYS_STMICRO_BOOT
TsiChung Liew05316f82008-08-11 13:41:49 +000063/* ST Micro serial flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_LOAD_ADDR2 0x40010007
TsiChung Liew05316f82008-08-11 13:41:49 +000065#define CONFIG_EXTRA_ENV_SETTINGS \
66 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +020067 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew05316f82008-08-11 13:41:49 +000068 "loadaddr=0x40010000\0" \
69 "sbfhdr=sbfhdr.bin\0" \
70 "uboot=u-boot.bin\0" \
71 "load=tftp ${loadaddr} ${sbfhdr};" \
Marek Vasut5368c552012-09-23 17:41:24 +020072 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
TsiChung Liew05316f82008-08-11 13:41:49 +000073 "upd=run load; run prog\0" \
Jason Jin09933fb2011-08-19 10:10:40 +080074 "prog=sf probe 0:1 1000000 3;" \
TsiChung Liew05316f82008-08-11 13:41:49 +000075 "sf erase 0 30000;" \
76 "sf write ${loadaddr} 0 30000;" \
77 "save\0" \
78 ""
79#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_UBOOT_END 0x3FFFF
TsiChung Liew05316f82008-08-11 13:41:49 +000081#define CONFIG_EXTRA_ENV_SETTINGS \
82 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +020083 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew05316f82008-08-11 13:41:49 +000084 "loadaddr=40010000\0" \
85 "u-boot=u-boot.bin\0" \
86 "load=tftp ${loadaddr) ${u-boot}\0" \
87 "upd=run load; run prog\0" \
Marek Vasut5368c552012-09-23 17:41:24 +020088 "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
89 "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
TsiChung Liew05316f82008-08-11 13:41:49 +000090 "cp.b ${loadaddr} 0 ${filesize};" \
91 "save\0" \
92 ""
93#endif
94
95/* Realtime clock */
96#define CONFIG_MCFRTC
97#undef RTC_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
TsiChung Liew05316f82008-08-11 13:41:49 +000099
100/* Timer */
101#define CONFIG_MCFTMR
TsiChung Liew05316f82008-08-11 13:41:49 +0000102
103/* I2c */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200104#define CONFIG_SYS_I2C
105#define CONFIG_SYS_I2C_FSL
106#define CONFIG_SYS_FSL_I2C_SPEED 80000
107#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
108#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
TsiChung Liew709b3842009-06-11 15:39:57 +0000109#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChung Liew05316f82008-08-11 13:41:49 +0000110
111/* DSPI and Serial Flash */
112#define CONFIG_CF_DSPI
113#define CONFIG_SERIAL_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_SBFHDR_SIZE 0x7
TsiChung Liew05316f82008-08-11 13:41:49 +0000115
116/* Input, PCI, Flexbus, and VCO */
117#define CONFIG_EXTRA_CLOCK
118
TsiChung Liew709b3842009-06-11 15:39:57 +0000119#define CONFIG_PRAM 2048 /* 2048 KB */
TsiChung Liew05316f82008-08-11 13:41:49 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChung Liew05316f82008-08-11 13:41:49 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
TsiChung Liew05316f82008-08-11 13:41:49 +0000124
TsiChung Liew709b3842009-06-11 15:39:57 +0000125#define CONFIG_SYS_MBAR 0xFC000000
TsiChung Liew05316f82008-08-11 13:41:49 +0000126
127/*
128 * Low Level Configuration Settings
129 * (address mappings, register initial values, etc.)
130 * You should know what you are doing if you make changes here.
131 */
132
133/*-----------------------------------------------------------------------
134 * Definitions for initial stack pointer and data area (in DPRAM)
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200137#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200139#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk553f0982010-10-26 13:32:32 +0200141#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
TsiChung Liew05316f82008-08-11 13:41:49 +0000142
143/*-----------------------------------------------------------------------
144 * Start addresses for the final memory configuration
145 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew05316f82008-08-11 13:41:49 +0000147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_SDRAM_BASE 0x40000000
149#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
150#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
151#define CONFIG_SYS_SDRAM_CFG2 0x57670000
152#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
153#define CONFIG_SYS_SDRAM_EMOD 0x80810000
154#define CONFIG_SYS_SDRAM_MODE 0x008D0000
155#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
TsiChung Liew05316f82008-08-11 13:41:49 +0000156
TsiChung Liew05316f82008-08-11 13:41:49 +0000157#ifdef CONFIG_CF_SBF
Jason Jin09933fb2011-08-19 10:10:40 +0800158# define CONFIG_SERIAL_BOOT
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200159# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
TsiChung Liew05316f82008-08-11 13:41:49 +0000160#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liew05316f82008-08-11 13:41:49 +0000162#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
164#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChung Liew05316f82008-08-11 13:41:49 +0000165
Jason Jin09933fb2011-08-19 10:10:40 +0800166/* Reserve 256 kB for malloc() */
167#define CONFIG_SYS_MALLOC_LEN (256 << 10)
TsiChung Liew05316f82008-08-11 13:41:49 +0000168/*
169 * For booting Linux, the board info and command line data
170 * have to be in the first 8 MB of memory, since this is
171 * the maximum mapped by the Linux kernel during initialization ??
172 */
173/* Initial Memory map for Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew05316f82008-08-11 13:41:49 +0000175
176/* Configuration for environment
Jason Jin09933fb2011-08-19 10:10:40 +0800177 * Environment is not embedded in u-boot. First time runing may have env
178 * crc error warning if there is no correct environment on the flash.
TsiChung Liew05316f82008-08-11 13:41:49 +0000179 */
TsiChung Liew05316f82008-08-11 13:41:49 +0000180#undef CONFIG_ENV_OVERWRITE
TsiChung Liew05316f82008-08-11 13:41:49 +0000181
TsiChung Liewee0a8462009-06-30 14:18:29 +0000182/* FLASH organization */
183#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liew05316f82008-08-11 13:41:49 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liew05316f82008-08-11 13:41:49 +0000186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
188# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
189# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
190# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191# define CONFIG_SYS_FLASH_CHECKSUM
192# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
TsiChung Liew05316f82008-08-11 13:41:49 +0000193
194#endif
195
196/*
197 * This is setting for JFFS2 support in u-boot.
198 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
199 */
TsiChung Liew709b3842009-06-11 15:39:57 +0000200#ifdef CONFIG_CMD_JFFS2
TsiChung Liew05316f82008-08-11 13:41:49 +0000201# define CONFIG_JFFS2_DEV "nor0"
202# define CONFIG_JFFS2_PART_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
TsiChung Liew05316f82008-08-11 13:41:49 +0000204#endif
205
TsiChung Liew709b3842009-06-11 15:39:57 +0000206/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liew05316f82008-08-11 13:41:49 +0000208
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600209#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200210 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600211#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200212 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600213#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
214#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
215#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
216 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
217 CF_ACR_EN | CF_ACR_SM_ALL)
218#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
219 CF_CACR_ICINVA | CF_CACR_EUSP)
220#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
221 CF_CACR_DEC | CF_CACR_DDCM_P | \
222 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
223
TsiChung Liew05316f82008-08-11 13:41:49 +0000224/*-----------------------------------------------------------------------
225 * Memory bank definitions
226 */
227/*
TsiChung Liew709b3842009-06-11 15:39:57 +0000228 * CS0 - NOR Flash 16MB
TsiChung Liew05316f82008-08-11 13:41:49 +0000229 * CS1 - Available
230 * CS2 - Available
231 * CS3 - Available
232 * CS4 - Available
233 * CS5 - Available
234 */
235
TsiChung Liew709b3842009-06-11 15:39:57 +0000236 /* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_CS0_BASE 0x00000000
TsiChung Liew709b3842009-06-11 15:39:57 +0000238#define CONFIG_SYS_CS0_MASK 0x00FF0001
239#define CONFIG_SYS_CS0_CTRL 0x00004D80
TsiChung Liew05316f82008-08-11 13:41:49 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
TsiChung Liew05316f82008-08-11 13:41:49 +0000242
243#endif /* _M54451EVB_H */