Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Freescale Semiconductor. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <command.h> |
| 25 | #include <pci.h> |
| 26 | #include <asm/processor.h> |
| 27 | #include <asm/mmu.h> |
Kumar Gala | 7c0d4a7 | 2008-09-22 14:11:11 -0500 | [diff] [blame] | 28 | #include <asm/cache.h> |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 29 | #include <asm/immap_85xx.h> |
Kumar Gala | c851462 | 2009-04-02 13:22:48 -0500 | [diff] [blame] | 30 | #include <asm/fsl_pci.h> |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 31 | #include <asm/fsl_ddr_sdram.h> |
| 32 | #include <asm/io.h> |
| 33 | #include <spd.h> |
| 34 | #include <miiphy.h> |
| 35 | #include <libfdt.h> |
| 36 | #include <spd_sdram.h> |
| 37 | #include <fdt_support.h> |
Jason Jin | 2e26d83 | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 38 | #include <tsec.h> |
| 39 | #include <netdev.h> |
Wolfgang Denk | 54a7cc4 | 2009-01-28 09:25:31 +0100 | [diff] [blame] | 40 | #include <sata.h> |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 41 | |
| 42 | #include "../common/pixis.h" |
Jason Jin | 2e26d83 | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 43 | #include "../common/sgmii_riser.h" |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 44 | |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 45 | phys_size_t fixed_sdram(void); |
| 46 | |
Andy Fleming | 80522dc | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 47 | int board_early_init_f (void) |
| 48 | { |
| 49 | #ifdef CONFIG_MMC |
| 50 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 51 | |
| 52 | setbits_be32(&gur->pmuxcr, |
| 53 | (MPC85xx_PMUXCR_SD_DATA | |
| 54 | MPC85xx_PMUXCR_SDHC_CD | |
| 55 | MPC85xx_PMUXCR_SDHC_WP)); |
| 56 | |
| 57 | #endif |
| 58 | return 0; |
| 59 | } |
| 60 | |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 61 | int checkboard (void) |
| 62 | { |
| 63 | printf ("Board: MPC8536DS, System ID: 0x%02x, " |
| 64 | "System Version: 0x%02x, FPGA Version: 0x%02x\n", |
| 65 | in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), |
| 66 | in8(PIXIS_BASE + PIXIS_PVER)); |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | phys_size_t |
| 71 | initdram(int board_type) |
| 72 | { |
| 73 | phys_size_t dram_size = 0; |
| 74 | |
| 75 | puts("Initializing...."); |
| 76 | |
| 77 | #ifdef CONFIG_SPD_EEPROM |
| 78 | dram_size = fsl_ddr_sdram(); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 79 | #else |
| 80 | dram_size = fixed_sdram(); |
| 81 | #endif |
Dave Liu | e57f0fa | 2008-10-28 17:53:45 +0800 | [diff] [blame] | 82 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
| 83 | dram_size *= 0x100000; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 84 | |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 85 | puts(" DDR: "); |
| 86 | return dram_size; |
| 87 | } |
| 88 | |
| 89 | #if !defined(CONFIG_SPD_EEPROM) |
| 90 | /* |
| 91 | * Fixed sdram init -- doesn't use serial presence detect. |
| 92 | */ |
| 93 | |
| 94 | phys_size_t fixed_sdram (void) |
| 95 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 97 | volatile ccsr_ddr_t *ddr= &immap->im_ddr; |
| 98 | uint d_init; |
| 99 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
| 101 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 102 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 103 | ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
| 104 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
| 105 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 106 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
| 107 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; |
| 108 | ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; |
| 109 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
| 110 | ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; |
| 111 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; |
| 112 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 113 | |
| 114 | #if defined (CONFIG_DDR_ECC) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 115 | ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; |
| 116 | ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; |
| 117 | ddr->err_sbe = CONFIG_SYS_DDR_SBE; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 118 | #endif |
| 119 | asm("sync;isync"); |
| 120 | |
| 121 | udelay(500); |
| 122 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 123 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 124 | |
| 125 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 126 | d_init = 1; |
| 127 | debug("DDR - 1st controller: memory initializing\n"); |
| 128 | /* |
| 129 | * Poll until memory is initialized. |
| 130 | * 512 Meg at 400 might hit this 200 times or so. |
| 131 | */ |
| 132 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { |
| 133 | udelay(1000); |
| 134 | } |
| 135 | debug("DDR: memory initialized\n\n"); |
| 136 | asm("sync; isync"); |
| 137 | udelay(500); |
| 138 | #endif |
| 139 | |
| 140 | return 512 * 1024 * 1024; |
| 141 | } |
| 142 | |
| 143 | #endif |
| 144 | |
| 145 | #ifdef CONFIG_PCI1 |
| 146 | static struct pci_controller pci1_hose; |
| 147 | #endif |
| 148 | |
| 149 | #ifdef CONFIG_PCIE1 |
| 150 | static struct pci_controller pcie1_hose; |
| 151 | #endif |
| 152 | |
| 153 | #ifdef CONFIG_PCIE2 |
| 154 | static struct pci_controller pcie2_hose; |
| 155 | #endif |
| 156 | |
| 157 | #ifdef CONFIG_PCIE3 |
| 158 | static struct pci_controller pcie3_hose; |
| 159 | #endif |
| 160 | |
| 161 | int first_free_busno=0; |
| 162 | |
| 163 | void |
| 164 | pci_init_board(void) |
| 165 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 166 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 167 | uint devdisr = gur->devdisr; |
| 168 | uint sdrs2_io_sel = |
| 169 | (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; |
| 170 | uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; |
| 171 | uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; |
| 172 | |
| 173 | debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ |
| 174 | host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); |
| 175 | |
| 176 | if (sdrs2_io_sel == 7) |
| 177 | printf(" Serdes2 disalbed\n"); |
| 178 | else if (sdrs2_io_sel == 4) { |
| 179 | printf(" eTSEC1 is in sgmii mode.\n"); |
| 180 | printf(" eTSEC3 is in sgmii mode.\n"); |
| 181 | } else if (sdrs2_io_sel == 6) |
| 182 | printf(" eTSEC1 is in sgmii mode.\n"); |
| 183 | |
| 184 | #ifdef CONFIG_PCIE3 |
| 185 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 187 | struct pci_controller *hose = &pcie3_hose; |
| 188 | int pcie_ep = (host_agent == 1); |
| 189 | int pcie_configured = (io_sel == 7); |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 190 | struct pci_region *r = hose->regions; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 191 | |
| 192 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ |
| 193 | printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", |
| 194 | pcie_ep ? "End Point" : "Root Complex", |
| 195 | (uint)pci); |
| 196 | if (pci->pme_msg_det) { |
| 197 | pci->pme_msg_det = 0xffffffff; |
| 198 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); |
| 199 | } |
| 200 | printf ("\n"); |
| 201 | |
| 202 | /* inbound */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 203 | r += fsl_pci_setup_inbound_windows(r); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 204 | |
| 205 | /* outbound memory */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 206 | pci_set_region(r++, |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 207 | CONFIG_SYS_PCIE3_MEM_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 208 | CONFIG_SYS_PCIE3_MEM_PHYS, |
| 209 | CONFIG_SYS_PCIE3_MEM_SIZE, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 210 | PCI_REGION_MEM); |
| 211 | |
| 212 | /* outbound io */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 213 | pci_set_region(r++, |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 214 | CONFIG_SYS_PCIE3_IO_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 215 | CONFIG_SYS_PCIE3_IO_PHYS, |
| 216 | CONFIG_SYS_PCIE3_IO_SIZE, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 217 | PCI_REGION_IO); |
| 218 | |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 219 | hose->region_count = r - hose->regions; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 220 | |
| 221 | hose->first_busno=first_free_busno; |
| 222 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
| 223 | |
| 224 | fsl_pci_init(hose); |
| 225 | |
| 226 | first_free_busno=hose->last_busno+1; |
| 227 | printf (" PCIE3 on bus %02x - %02x\n", |
| 228 | hose->first_busno,hose->last_busno); |
| 229 | } else { |
| 230 | printf (" PCIE3: disabled\n"); |
| 231 | } |
| 232 | |
| 233 | } |
| 234 | #else |
| 235 | gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ |
| 236 | #endif |
| 237 | |
| 238 | #ifdef CONFIG_PCIE1 |
| 239 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 240 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 241 | struct pci_controller *hose = &pcie1_hose; |
| 242 | int pcie_ep = (host_agent == 5); |
| 243 | int pcie_configured = (io_sel == 2 || io_sel == 3 |
| 244 | || io_sel == 5 || io_sel == 7); |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 245 | struct pci_region *r = hose->regions; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 246 | |
| 247 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ |
| 248 | printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", |
| 249 | pcie_ep ? "End Point" : "Root Complex", |
| 250 | (uint)pci); |
| 251 | if (pci->pme_msg_det) { |
| 252 | pci->pme_msg_det = 0xffffffff; |
| 253 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); |
| 254 | } |
| 255 | printf ("\n"); |
| 256 | |
| 257 | /* inbound */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 258 | r += fsl_pci_setup_inbound_windows(r); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 259 | |
| 260 | /* outbound memory */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 261 | pci_set_region(r++, |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 262 | CONFIG_SYS_PCIE1_MEM_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 263 | CONFIG_SYS_PCIE1_MEM_PHYS, |
| 264 | CONFIG_SYS_PCIE1_MEM_SIZE, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 265 | PCI_REGION_MEM); |
| 266 | |
| 267 | /* outbound io */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 268 | pci_set_region(r++, |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 269 | CONFIG_SYS_PCIE1_IO_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 270 | CONFIG_SYS_PCIE1_IO_PHYS, |
| 271 | CONFIG_SYS_PCIE1_IO_SIZE, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 272 | PCI_REGION_IO); |
| 273 | |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 274 | #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 275 | /* outbound memory */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 276 | pci_set_region(r++, |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 277 | CONFIG_SYS_PCIE1_MEM_BUS2, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 278 | CONFIG_SYS_PCIE1_MEM_PHYS2, |
| 279 | CONFIG_SYS_PCIE1_MEM_SIZE2, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 280 | PCI_REGION_MEM); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 281 | #endif |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 282 | hose->region_count = r - hose->regions; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 283 | hose->first_busno=first_free_busno; |
| 284 | |
| 285 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
| 286 | |
| 287 | fsl_pci_init(hose); |
| 288 | |
| 289 | first_free_busno=hose->last_busno+1; |
| 290 | printf(" PCIE1 on bus %02x - %02x\n", |
| 291 | hose->first_busno,hose->last_busno); |
| 292 | |
| 293 | } else { |
| 294 | printf (" PCIE1: disabled\n"); |
| 295 | } |
| 296 | |
| 297 | } |
| 298 | #else |
| 299 | gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
| 300 | #endif |
| 301 | |
| 302 | #ifdef CONFIG_PCIE2 |
| 303 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 304 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 305 | struct pci_controller *hose = &pcie2_hose; |
| 306 | int pcie_ep = (host_agent == 3); |
| 307 | int pcie_configured = (io_sel == 5 || io_sel == 7); |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 308 | struct pci_region *r = hose->regions; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 309 | |
| 310 | if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ |
| 311 | printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", |
| 312 | pcie_ep ? "End Point" : "Root Complex", |
| 313 | (uint)pci); |
| 314 | if (pci->pme_msg_det) { |
| 315 | pci->pme_msg_det = 0xffffffff; |
| 316 | debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); |
| 317 | } |
| 318 | printf ("\n"); |
| 319 | |
| 320 | /* inbound */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 321 | r += fsl_pci_setup_inbound_windows(r); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 322 | |
| 323 | /* outbound memory */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 324 | pci_set_region(r++, |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 325 | CONFIG_SYS_PCIE2_MEM_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 326 | CONFIG_SYS_PCIE2_MEM_PHYS, |
| 327 | CONFIG_SYS_PCIE2_MEM_SIZE, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 328 | PCI_REGION_MEM); |
| 329 | |
| 330 | /* outbound io */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 331 | pci_set_region(r++, |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 332 | CONFIG_SYS_PCIE2_IO_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 333 | CONFIG_SYS_PCIE2_IO_PHYS, |
| 334 | CONFIG_SYS_PCIE2_IO_SIZE, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 335 | PCI_REGION_IO); |
| 336 | |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 337 | #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 338 | /* outbound memory */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 339 | pci_set_region(r++, |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 340 | CONFIG_SYS_PCIE2_MEM_BUS2, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 341 | CONFIG_SYS_PCIE2_MEM_PHYS2, |
| 342 | CONFIG_SYS_PCIE2_MEM_SIZE2, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 343 | PCI_REGION_MEM); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 344 | #endif |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 345 | hose->region_count = r - hose->regions; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 346 | hose->first_busno=first_free_busno; |
| 347 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
| 348 | |
| 349 | fsl_pci_init(hose); |
| 350 | first_free_busno=hose->last_busno+1; |
| 351 | printf (" PCIE2 on bus %02x - %02x\n", |
| 352 | hose->first_busno,hose->last_busno); |
| 353 | |
| 354 | } else { |
| 355 | printf (" PCIE2: disabled\n"); |
| 356 | } |
| 357 | |
| 358 | } |
| 359 | #else |
| 360 | gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ |
| 361 | #endif |
| 362 | |
| 363 | |
| 364 | #ifdef CONFIG_PCI1 |
| 365 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 366 | volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 367 | struct pci_controller *hose = &pci1_hose; |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 368 | struct pci_region *r = hose->regions; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 369 | |
| 370 | uint pci_agent = (host_agent == 6); |
| 371 | uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ |
| 372 | uint pci_32 = 1; |
| 373 | uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ |
| 374 | uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ |
| 375 | |
| 376 | |
| 377 | if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { |
| 378 | printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", |
| 379 | (pci_32) ? 32 : 64, |
| 380 | (pci_speed == 33333000) ? "33" : |
| 381 | (pci_speed == 66666000) ? "66" : "unknown", |
| 382 | pci_clk_sel ? "sync" : "async", |
| 383 | pci_agent ? "agent" : "host", |
| 384 | pci_arb ? "arbiter" : "external-arbiter", |
| 385 | (uint)pci |
| 386 | ); |
| 387 | |
| 388 | /* inbound */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 389 | r += fsl_pci_setup_inbound_windows(r); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 390 | |
| 391 | /* outbound memory */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 392 | pci_set_region(r++, |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 393 | CONFIG_SYS_PCI1_MEM_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 394 | CONFIG_SYS_PCI1_MEM_PHYS, |
| 395 | CONFIG_SYS_PCI1_MEM_SIZE, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 396 | PCI_REGION_MEM); |
| 397 | |
| 398 | /* outbound io */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 399 | pci_set_region(r++, |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 400 | CONFIG_SYS_PCI1_IO_BUS, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 401 | CONFIG_SYS_PCI1_IO_PHYS, |
| 402 | CONFIG_SYS_PCI1_IO_SIZE, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 403 | PCI_REGION_IO); |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 404 | |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 405 | #ifdef CONFIG_SYS_PCI1_MEM_BUS2 |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 406 | /* outbound memory */ |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 407 | pci_set_region(r++, |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 408 | CONFIG_SYS_PCI1_MEM_BUS2, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 409 | CONFIG_SYS_PCI1_MEM_PHYS2, |
| 410 | CONFIG_SYS_PCI1_MEM_SIZE2, |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 411 | PCI_REGION_MEM); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 412 | #endif |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 413 | hose->region_count = r - hose->regions; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 414 | hose->first_busno=first_free_busno; |
| 415 | pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); |
| 416 | |
| 417 | fsl_pci_init(hose); |
| 418 | first_free_busno=hose->last_busno+1; |
| 419 | printf ("PCI on bus %02x - %02x\n", |
| 420 | hose->first_busno,hose->last_busno); |
| 421 | } else { |
| 422 | printf (" PCI: disabled\n"); |
| 423 | } |
| 424 | } |
| 425 | #else |
| 426 | gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ |
| 427 | #endif |
| 428 | } |
| 429 | |
| 430 | |
| 431 | int board_early_init_r(void) |
| 432 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 433 | const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 434 | const u8 flash_esel = 1; |
| 435 | |
| 436 | /* |
| 437 | * Remap Boot flash + PROMJET region to caching-inhibited |
| 438 | * so that flash can be erased properly. |
| 439 | */ |
| 440 | |
Kumar Gala | 7c0d4a7 | 2008-09-22 14:11:11 -0500 | [diff] [blame] | 441 | /* Flush d-cache and invalidate i-cache of any FLASH data */ |
Wolfgang Denk | 3cbd823 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 442 | flush_dcache(); |
| 443 | invalidate_icache(); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 444 | |
| 445 | /* invalidate existing TLB entry for flash + promjet */ |
| 446 | disable_tlb(flash_esel); |
| 447 | |
Kumar Gala | c953ddf | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 448 | set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 449 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ |
| 450 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ |
| 451 | |
| 452 | return 0; |
| 453 | } |
| 454 | |
| 455 | #ifdef CONFIG_GET_CLK_FROM_ICS307 |
| 456 | /* decode S[0-2] to Output Divider (OD) */ |
| 457 | static unsigned char |
| 458 | ics307_S_to_OD[] = { |
| 459 | 10, 2, 8, 4, 5, 7, 3, 6 |
| 460 | }; |
| 461 | |
| 462 | /* Calculate frequency being generated by ICS307-02 clock chip based upon |
| 463 | * the control bytes being programmed into it. */ |
| 464 | /* XXX: This function should probably go into a common library */ |
| 465 | static unsigned long |
| 466 | ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) |
| 467 | { |
| 468 | const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ; |
| 469 | unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); |
| 470 | unsigned long RDW = cw2 & 0x7F; |
| 471 | unsigned long OD = ics307_S_to_OD[cw0 & 0x7]; |
| 472 | unsigned long freq; |
| 473 | |
| 474 | /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */ |
| 475 | |
| 476 | /* cw0: C1 C0 TTL F1 F0 S2 S1 S0 |
| 477 | * cw1: V8 V7 V6 V5 V4 V3 V2 V1 |
| 478 | * cw2: V0 R6 R5 R4 R3 R2 R1 R0 |
| 479 | * |
| 480 | * R6:R0 = Reference Divider Word (RDW) |
| 481 | * V8:V0 = VCO Divider Word (VDW) |
| 482 | * S2:S0 = Output Divider Select (OD) |
| 483 | * F1:F0 = Function of CLK2 Output |
| 484 | * TTL = duty cycle |
| 485 | * C1:C0 = internal load capacitance for cyrstal |
| 486 | */ |
| 487 | |
| 488 | /* Adding 1 to get a "nicely" rounded number, but this needs |
| 489 | * more tweaking to get a "properly" rounded number. */ |
| 490 | |
| 491 | freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD)); |
| 492 | |
| 493 | debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2, |
| 494 | freq); |
| 495 | return freq; |
| 496 | } |
| 497 | |
| 498 | unsigned long |
| 499 | get_board_sys_clk(ulong dummy) |
| 500 | { |
| 501 | return ics307_clk_freq ( |
| 502 | in8(PIXIS_BASE + PIXIS_VSYSCLK0), |
| 503 | in8(PIXIS_BASE + PIXIS_VSYSCLK1), |
| 504 | in8(PIXIS_BASE + PIXIS_VSYSCLK2) |
| 505 | ); |
| 506 | } |
| 507 | |
| 508 | unsigned long |
| 509 | get_board_ddr_clk(ulong dummy) |
| 510 | { |
| 511 | return ics307_clk_freq ( |
| 512 | in8(PIXIS_BASE + PIXIS_VDDRCLK0), |
| 513 | in8(PIXIS_BASE + PIXIS_VDDRCLK1), |
| 514 | in8(PIXIS_BASE + PIXIS_VDDRCLK2) |
| 515 | ); |
| 516 | } |
| 517 | #else |
| 518 | unsigned long |
| 519 | get_board_sys_clk(ulong dummy) |
| 520 | { |
| 521 | u8 i; |
| 522 | ulong val = 0; |
| 523 | |
| 524 | i = in8(PIXIS_BASE + PIXIS_SPD); |
| 525 | i &= 0x07; |
| 526 | |
| 527 | switch (i) { |
| 528 | case 0: |
| 529 | val = 33333333; |
| 530 | break; |
| 531 | case 1: |
| 532 | val = 40000000; |
| 533 | break; |
| 534 | case 2: |
| 535 | val = 50000000; |
| 536 | break; |
| 537 | case 3: |
| 538 | val = 66666666; |
| 539 | break; |
| 540 | case 4: |
| 541 | val = 83333333; |
| 542 | break; |
| 543 | case 5: |
| 544 | val = 100000000; |
| 545 | break; |
| 546 | case 6: |
| 547 | val = 133333333; |
| 548 | break; |
| 549 | case 7: |
| 550 | val = 166666666; |
| 551 | break; |
| 552 | } |
| 553 | |
| 554 | return val; |
| 555 | } |
| 556 | |
| 557 | unsigned long |
| 558 | get_board_ddr_clk(ulong dummy) |
| 559 | { |
| 560 | u8 i; |
| 561 | ulong val = 0; |
| 562 | |
| 563 | i = in8(PIXIS_BASE + PIXIS_SPD); |
| 564 | i &= 0x38; |
| 565 | i >>= 3; |
| 566 | |
| 567 | switch (i) { |
| 568 | case 0: |
| 569 | val = 33333333; |
| 570 | break; |
| 571 | case 1: |
| 572 | val = 40000000; |
| 573 | break; |
| 574 | case 2: |
| 575 | val = 50000000; |
| 576 | break; |
| 577 | case 3: |
| 578 | val = 66666666; |
| 579 | break; |
| 580 | case 4: |
| 581 | val = 83333333; |
| 582 | break; |
| 583 | case 5: |
| 584 | val = 100000000; |
| 585 | break; |
| 586 | case 6: |
| 587 | val = 133333333; |
| 588 | break; |
| 589 | case 7: |
| 590 | val = 166666666; |
| 591 | break; |
| 592 | } |
| 593 | return val; |
| 594 | } |
| 595 | #endif |
| 596 | |
Mike Frysinger | cf7e399 | 2009-01-27 16:12:21 -0500 | [diff] [blame] | 597 | int sata_initialize(void) |
Jason Jin | 0f8cbc1 | 2008-10-10 11:41:01 +0800 | [diff] [blame] | 598 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 599 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Jason Jin | 0f8cbc1 | 2008-10-10 11:41:01 +0800 | [diff] [blame] | 600 | uint sdrs2_io_sel = |
| 601 | (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; |
| 602 | if (sdrs2_io_sel & 0x04) |
Mike Frysinger | cf7e399 | 2009-01-27 16:12:21 -0500 | [diff] [blame] | 603 | return 1; |
Jason Jin | 0f8cbc1 | 2008-10-10 11:41:01 +0800 | [diff] [blame] | 604 | |
Mike Frysinger | cf7e399 | 2009-01-27 16:12:21 -0500 | [diff] [blame] | 605 | return __sata_initialize(); |
Jason Jin | 0f8cbc1 | 2008-10-10 11:41:01 +0800 | [diff] [blame] | 606 | } |
| 607 | |
Jason Jin | 2e26d83 | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 608 | int board_eth_init(bd_t *bis) |
| 609 | { |
| 610 | #ifdef CONFIG_TSEC_ENET |
| 611 | struct tsec_info_struct tsec_info[2]; |
| 612 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 613 | int num = 0; |
| 614 | uint sdrs2_io_sel = |
| 615 | (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; |
| 616 | |
| 617 | #ifdef CONFIG_TSEC1 |
| 618 | SET_STD_TSEC_INFO(tsec_info[num], 1); |
| 619 | if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { |
| 620 | tsec_info[num].phyaddr = 0; |
| 621 | tsec_info[num].flags |= TSEC_SGMII; |
| 622 | } |
| 623 | num++; |
| 624 | #endif |
| 625 | #ifdef CONFIG_TSEC3 |
| 626 | SET_STD_TSEC_INFO(tsec_info[num], 3); |
| 627 | if (sdrs2_io_sel == 4) { |
| 628 | tsec_info[num].phyaddr = 1; |
| 629 | tsec_info[num].flags |= TSEC_SGMII; |
| 630 | } |
| 631 | num++; |
| 632 | #endif |
| 633 | |
| 634 | if (!num) { |
| 635 | printf("No TSECs initialized\n"); |
| 636 | return 0; |
| 637 | } |
| 638 | |
Andy Fleming | feede8b | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 639 | #ifdef CONFIG_FSL_SGMII_RISER |
Jason Jin | 2e26d83 | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 640 | if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) |
| 641 | fsl_sgmii_riser_init(tsec_info, num); |
Andy Fleming | feede8b | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 642 | #endif |
Jason Jin | 2e26d83 | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 643 | |
| 644 | tsec_eth_init(bis, tsec_info, num); |
| 645 | #endif |
| 646 | return pci_eth_init(bis); |
| 647 | } |
| 648 | |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 649 | #if defined(CONFIG_OF_BOARD_SETUP) |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 650 | void ft_board_setup(void *blob, bd_t *bd) |
| 651 | { |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 652 | ft_cpu_setup(blob, bd); |
| 653 | |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 654 | #ifdef CONFIG_PCI1 |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 655 | ft_fsl_pci_setup(blob, "pci0", &pci1_hose); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 656 | #endif |
| 657 | #ifdef CONFIG_PCIE2 |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 658 | ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); |
| 659 | #endif |
| 660 | #ifdef CONFIG_PCIE2 |
| 661 | ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 662 | #endif |
| 663 | #ifdef CONFIG_PCIE1 |
Kumar Gala | 2dba0de | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 664 | ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 665 | #endif |
Andy Fleming | feede8b | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 666 | #ifdef CONFIG_FSL_SGMII_RISER |
| 667 | fsl_sgmii_riser_fdt_fixup(blob); |
| 668 | #endif |
Kumar Gala | 9490a7f | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 669 | } |
| 670 | #endif |