Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 72755c7137396fdd8230dfc498294760fa2aaeb4 / . / post / cache_8xx.S
blob: 2974882b89014220f6cf4604c5c6e8eb2a471120 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
24
25#ifdef CONFIG_POST
26#if defined(CONFIG_MPC823) || \
27 defined(CONFIG_MPC850) || \
28 defined(CONFIG_MPC855) || \
29 defined(CONFIG_MPC860) || \
wdenkd126bfb2003-04-10 11:18:18 +0000[diff] [blame]30 defined(CONFIG_MPC862) || \
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]31 defined(CONFIG_MPC824X)
32
33#include <post.h>
34#include <ppc_asm.tmpl>
35#include <ppc_defs.h>
36#include <asm/cache.h>
37
38#if CONFIG_POST & CFG_POST_CACHE
39
40 .text
41
42cache_post_dinvalidate:
43 lis r10, IDC_INVALL@h
44 mtspr DC_CST, r10
45 blr
46
47cache_post_iinvalidate:
48 lis r10, IDC_INVALL@h
49 mtspr IC_CST, r10
50 isync
51 blr
52
53cache_post_ddisable:
54 lis r10, IDC_DISABLE@h
55 mtspr DC_CST, r10
56 blr
57
58cache_post_dwb:
59 lis r10, IDC_ENABLE@h
60 mtspr DC_CST, r10
61 lis r10, DC_CFWT@h
62 mtspr DC_CST, r10
63 blr
64
65cache_post_dwt:
66 lis r10, IDC_ENABLE@h
67 mtspr DC_CST, r10
68 lis r10, DC_SFWT@h
69 mtspr DC_CST, r10
70 blr
71
72cache_post_idisable:
73 lis r10, IDC_DISABLE@h
74 mtspr IC_CST, r10
75 isync
76 blr
77
78cache_post_ienable:
79 lis r10, IDC_ENABLE@h
80 mtspr IC_CST, r10
81 isync
82 blr
83
84cache_post_iunlock:
85 lis r10, IDC_UNALL@h
86 mtspr IC_CST, r10
87 isync
88 blr
89
90cache_post_ilock:
91 mtspr IC_ADR, r3
92 lis r10, IDC_LDLCK@h
93 mtspr IC_CST, r10
94 isync
95 blr
96
97/*
98 * turn on the data cache
99 * switch the data cache to write-back or write-through mode
100 * invalidate the data cache
101 * write the negative pattern to a cached area
102 * read the area
103 *
104 * The negative pattern must be read at the last step
105 */
106 .global cache_post_test1
107cache_post_test1:
108 mflr r0
109 stw r0, 4(r1)
110
111 stwu r3, -4(r1)
112 stwu r4, -4(r1)
113
114 bl cache_post_dwb
115 bl cache_post_dinvalidate
116
117 /* Write the negative pattern to the test area */
118 lwz r0, 0(r1)
119 mtctr r0
120 li r0, 0xff
121 lwz r3, 4(r1)
122 subi r3, r3, 1
1231:
124 stbu r0, 1(r3)
125 bdnz 1b
126
127 /* Read the test area */
128 lwz r0, 0(r1)
129 mtctr r0
130 lwz r4, 4(r1)
131 subi r4, r4, 1
132 li r3, 0
1331:
134 lbzu r0, 1(r4)
135 cmpli cr0, r0, 0xff
136 beq 2f
137 li r3, -1
138 b 3f
1392:
140 bdnz 1b
1413:
142
143 bl cache_post_ddisable
144 bl cache_post_dinvalidate
145
146 addi r1, r1, 8
147
148 lwz r0, 4(r1)
149 mtlr r0
150 blr
151
152/*
153 * turn on the data cache
154 * switch the data cache to write-back or write-through mode
155 * invalidate the data cache
156 * write the zero pattern to a cached area
157 * turn off the data cache
158 * write the negative pattern to the area
159 * turn on the data cache
160 * read the area
161 *
162 * The negative pattern must be read at the last step
163 */
164 .global cache_post_test2
165cache_post_test2:
166 mflr r0
167 stw r0, 4(r1)
168
169 stwu r3, -4(r1)
170 stwu r4, -4(r1)
171
172 bl cache_post_dwb
173 bl cache_post_dinvalidate
174
175 /* Write the zero pattern to the test area */
176 lwz r0, 0(r1)
177 mtctr r0
178 li r0, 0
179 lwz r3, 4(r1)
180 subi r3, r3, 1
1811:
182 stbu r0, 1(r3)
183 bdnz 1b
184
185 bl cache_post_ddisable
186
187 /* Write the negative pattern to the test area */
188 lwz r0, 0(r1)
189 mtctr r0
190 li r0, 0xff
191 lwz r3, 4(r1)
192 subi r3, r3, 1
1931:
194 stbu r0, 1(r3)
195 bdnz 1b
196
197 bl cache_post_dwb
198
199 /* Read the test area */
200 lwz r0, 0(r1)
201 mtctr r0
202 lwz r4, 4(r1)
203 subi r4, r4, 1
204 li r3, 0
2051:
206 lbzu r0, 1(r4)
207 cmpli cr0, r0, 0xff
208 beq 2f
209 li r3, -1
210 b 3f
2112:
212 bdnz 1b
2133:
214
215 bl cache_post_ddisable
216 bl cache_post_dinvalidate
217
218 addi r1, r1, 8
219
220 lwz r0, 4(r1)
221 mtlr r0
222 blr
223
224/*
225 * turn on the data cache
226 * switch the data cache to write-through mode
227 * invalidate the data cache
228 * write the zero pattern to a cached area
229 * flush the data cache
230 * write the negative pattern to the area
231 * turn off the data cache
232 * read the area
233 *
234 * The negative pattern must be read at the last step
235 */
236 .global cache_post_test3
237cache_post_test3:
238 mflr r0
239 stw r0, 4(r1)
240
241 stwu r3, -4(r1)
242 stwu r4, -4(r1)
243
244 bl cache_post_ddisable
245 bl cache_post_dinvalidate
246
247 /* Write the zero pattern to the test area */
248 lwz r0, 0(r1)
249 mtctr r0
250 li r0, 0
251 lwz r3, 4(r1)
252 subi r3, r3, 1
2531:
254 stbu r0, 1(r3)
255 bdnz 1b
256
257 bl cache_post_dwt
258 bl cache_post_dinvalidate
259
260 /* Write the negative pattern to the test area */
261 lwz r0, 0(r1)
262 mtctr r0
263 li r0, 0xff
264 lwz r3, 4(r1)
265 subi r3, r3, 1
2661:
267 stbu r0, 1(r3)
268 bdnz 1b
269
270 bl cache_post_ddisable
271 bl cache_post_dinvalidate
272
273 /* Read the test area */
274 lwz r0, 0(r1)
275 mtctr r0
276 lwz r4, 4(r1)
277 subi r4, r4, 1
278 li r3, 0
2791:
280 lbzu r0, 1(r4)
281 cmpli cr0, r0, 0xff
282 beq 2f
283 li r3, -1
284 b 3f
2852:
286 bdnz 1b
2873:
288
289 addi r1, r1, 8
290
291 lwz r0, 4(r1)
292 mtlr r0
293 blr
294
295/*
296 * turn on the data cache
297 * switch the data cache to write-back mode
298 * invalidate the data cache
299 * write the negative pattern to a cached area
300 * flush the data cache
301 * write the zero pattern to the area
302 * invalidate the data cache
303 * read the area
304 *
305 * The negative pattern must be read at the last step
306 */
307 .global cache_post_test4
308cache_post_test4:
309 mflr r0
310 stw r0, 4(r1)
311
312 stwu r3, -4(r1)
313 stwu r4, -4(r1)
314
315 bl cache_post_ddisable
316 bl cache_post_dinvalidate
317
318 /* Write the negative pattern to the test area */
319 lwz r0, 0(r1)
320 mtctr r0
321 li r0, 0xff
322 lwz r3, 4(r1)
323 subi r3, r3, 1
3241:
325 stbu r0, 1(r3)
326 bdnz 1b
327
328 bl cache_post_dwb
329 bl cache_post_dinvalidate
330
331 /* Write the zero pattern to the test area */
332 lwz r0, 0(r1)
333 mtctr r0
334 li r0, 0
335 lwz r3, 4(r1)
336 subi r3, r3, 1
3371:
338 stbu r0, 1(r3)
339 bdnz 1b
340
341 bl cache_post_ddisable
342 bl cache_post_dinvalidate
343
344 /* Read the test area */
345 lwz r0, 0(r1)
346 mtctr r0
347 lwz r4, 4(r1)
348 subi r4, r4, 1
349 li r3, 0
3501:
351 lbzu r0, 1(r4)
352 cmpli cr0, r0, 0xff
353 beq 2f
354 li r3, -1
355 b 3f
3562:
357 bdnz 1b
3583:
359
360 addi r1, r1, 8
361
362 lwz r0, 4(r1)
363 mtlr r0
364 blr
365
366cache_post_test5_1:
367 li r3, 0
368cache_post_test5_2:
369 li r3, -1
370
371/*
372 * turn on the instruction cache
373 * unlock the entire instruction cache
374 * invalidate the instruction cache
375 * lock a branch instruction in the instruction cache
376 * replace the branch instruction with "nop"
377 * jump to the branch instruction
378 * check that the branch instruction was executed
379*/
380 .global cache_post_test5
381cache_post_test5:
382 mflr r0
383 stw r0, 4(r1)
384
385 bl cache_post_ienable
386 bl cache_post_iunlock
387 bl cache_post_iinvalidate
388
389 /* Compute r9 = cache_post_test5_reloc */
390 bl cache_post_test5_reloc
391cache_post_test5_reloc:
392 mflr r9
393
394 /* Copy the test instruction to cache_post_test5_data */
395 lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h
396 ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l
397 add r3, r3, r9
398 lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h
399 ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
400 add r4, r4, r9
401 lwz r0, 0(r3)
402 stw r0, 0(r4)
403
404 bl cache_post_iinvalidate
405
406 /* Lock the branch instruction */
407 lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h
408 ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l
409 add r3, r3, r9
410 bl cache_post_ilock
411
412 /* Replace the test instruction */
413 lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h
414 ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l
415 add r3, r3, r9
416 lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h
417 ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
418 add r4, r4, r9
419 lwz r0, 0(r3)
420 stw r0, 0(r4)
421
422 bl cache_post_iinvalidate
423
424 /* Execute to the test instruction */
425cache_post_test5_data:
426 nop
427
428 bl cache_post_iunlock
429
430 lwz r0, 4(r1)
431 mtlr r0
432 blr
433
434cache_post_test6_1:
435 li r3, -1
436cache_post_test6_2:
437 li r3, 0
438
439/*
440 * turn on the instruction cache
441 * unlock the entire instruction cache
442 * invalidate the instruction cache
443 * lock a branch instruction in the instruction cache
444 * replace the branch instruction with "nop"
445 * jump to the branch instruction
446 * check that the branch instruction was executed
447 */
448 .global cache_post_test6
449cache_post_test6:
450 mflr r0
451 stw r0, 4(r1)
452
453 bl cache_post_ienable
454 bl cache_post_iunlock
455 bl cache_post_iinvalidate
456
457 /* Compute r9 = cache_post_test6_reloc */
458 bl cache_post_test6_reloc
459cache_post_test6_reloc:
460 mflr r9
461
462 /* Copy the test instruction to cache_post_test6_data */
463 lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h
464 ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l
465 add r3, r3, r9
466 lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h
467 ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
468 add r4, r4, r9
469 lwz r0, 0(r3)
470 stw r0, 0(r4)
471
472 bl cache_post_iinvalidate
473
474 /* Replace the test instruction */
475 lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h
476 ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l
477 add r3, r3, r9
478 lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h
479 ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
480 add r4, r4, r9
481 lwz r0, 0(r3)
482 stw r0, 0(r4)
483
484 bl cache_post_iinvalidate
485
486 /* Execute to the test instruction */
487cache_post_test6_data:
488 nop
489
490 lwz r0, 4(r1)
491 mtlr r0
492 blr
493
494#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 || MPC824X */
495#endif /* CONFIG_POST & CFG_POST_CACHE */
496#endif /* CONFIG_POST */