blob: 67b5d5406dd84a0b047d1289b6fdb1141bc5ec72 [file] [log] [blame]
stroese1f54ce62004-12-16 18:23:14 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Stefan Roese98f4a3d2005-09-22 09:04:17 +02005 * (C) Copyright 2005
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Matthias Fuchsbd84ee42007-07-09 10:10:06 +02008 * (C) Copyright 2006-2007
Stefan Roese48a05a52006-02-07 16:51:04 +01009 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
10 *
stroese1f54ce62004-12-16 18:23:14 +000011 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
31#include <asm/processor.h>
32#include <command.h>
33#include <malloc.h>
Stefan Roese98f4a3d2005-09-22 09:04:17 +020034#include <pci.h>
35#include <sm501.h>
stroese1f54ce62004-12-16 18:23:14 +000036
Wolfgang Denkd87080b2006-03-31 18:32:53 +020037DECLARE_GLOBAL_DATA_PTR;
38
Stefan Roese98f4a3d2005-09-22 09:04:17 +020039#ifdef CONFIG_VIDEO_SM501
40
41#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
42 (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
43
44#ifdef CONFIG_VIDEO_SM501_8BPP
45#error CONFIG_VIDEO_SM501_8BPP not supported.
46#endif /* CONFIG_VIDEO_SM501_8BPP */
47
48#ifdef CONFIG_VIDEO_SM501_16BPP
49#define BPP 16
50
51/*
52 * 800x600 display B084SN03: PCLK = 40MHz
53 * => 2*PCLK = 80MHz
54 * 336/4 = 84MHz
55 * => PCLK = 84MHz
56 */
57static const SMI_REGS init_regs_800x600 [] =
58{
59#if 1 /* test-only */
60 {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
61#else
62 {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
63#endif
64 {0x00004, SWAP32(0x00000000)},
65 /* clocks for pm1... */
66 {0x00048, SWAP32(0x00021807)},
67 {0x0004C, SWAP32(0x221a0a01)},
68 {0x00054, SWAP32(0x00000001)},
69 /* clocks for pm0... */
70 {0x00040, SWAP32(0x00021807)},
71 {0x00044, SWAP32(0x221a0a01)},
72 {0x00054, SWAP32(0x00000000)},
Stefan Roese48a05a52006-02-07 16:51:04 +010073 /* GPIO */
74 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
Stefan Roese98f4a3d2005-09-22 09:04:17 +020075 /* panel control regs... */
76 {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
77 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
Stefan Roese48a05a52006-02-07 16:51:04 +010078 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
Stefan Roese98f4a3d2005-09-22 09:04:17 +020079 {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
80 {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
81 {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
82 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
83 {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
84 {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
85 {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
86 {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
87 {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
88 {0x80200, SWAP32(0x00010000)}, /* crt display control */
89 {0, 0}
90};
91
92/*
93 * 1024x768 display G150XG02: PCLK = 65MHz
94 * => 2*PCLK = 130MHz
95 * 288/2 = 144MHz
96 * => PCLK = 72MHz
97 */
98static const SMI_REGS init_regs_1024x768 [] =
99{
100 {0x00004, SWAP32(0x00000000)},
101 /* clocks for pm1... */
102 {0x00048, SWAP32(0x00021807)},
103 {0x0004C, SWAP32(0x011a0a01)},
104 {0x00054, SWAP32(0x00000001)},
105 /* clocks for pm0... */
106 {0x00040, SWAP32(0x00021807)},
107 {0x00044, SWAP32(0x011a0a01)},
108 {0x00054, SWAP32(0x00000000)},
Stefan Roese48a05a52006-02-07 16:51:04 +0100109 /* GPIO */
110 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200111 /* panel control regs... */
112 {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
113 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
Stefan Roese48a05a52006-02-07 16:51:04 +0100114 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200115 {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
116 {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
117 {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
118 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
119 {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
120 {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
121 {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
122 {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
123 {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
124 {0x80200, SWAP32(0x00010000)}, /* crt display control */
125 {0, 0}
126};
127
128#endif /* CONFIG_VIDEO_SM501_16BPP */
129
130#ifdef CONFIG_VIDEO_SM501_32BPP
131#define BPP 32
132
133/*
134 * 800x600 display B084SN03: PCLK = 40MHz
135 * => 2*PCLK = 80MHz
136 * 336/4 = 84MHz
137 * => PCLK = 84MHz
138 */
139static const SMI_REGS init_regs_800x600 [] =
140{
141#if 0 /* test-only */
142 {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
143#else
144 {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
145#endif
146 {0x00004, SWAP32(0x00000000)},
147 /* clocks for pm1... */
148 {0x00048, SWAP32(0x00021807)},
149 {0x0004C, SWAP32(0x221a0a01)},
150 {0x00054, SWAP32(0x00000001)},
151 /* clocks for pm0... */
152 {0x00040, SWAP32(0x00021807)},
153 {0x00044, SWAP32(0x221a0a01)},
154 {0x00054, SWAP32(0x00000000)},
Stefan Roese48a05a52006-02-07 16:51:04 +0100155 /* GPIO */
156 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200157 /* panel control regs... */
158 {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
159 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
Stefan Roese48a05a52006-02-07 16:51:04 +0100160 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200161 {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
162 {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
163 {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
164 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
165 {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
166 {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
167 {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
168 {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
169 {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
170 {0x80200, SWAP32(0x00010000)}, /* crt display control */
171 {0, 0}
172};
173
174/*
175 * 1024x768 display G150XG02: PCLK = 65MHz
176 * => 2*PCLK = 130MHz
177 * 288/2 = 144MHz
178 * => PCLK = 72MHz
179 */
180static const SMI_REGS init_regs_1024x768 [] =
181{
182 {0x00004, SWAP32(0x00000000)},
183 /* clocks for pm1... */
184 {0x00048, SWAP32(0x00021807)},
185 {0x0004C, SWAP32(0x011a0a01)},
186 {0x00054, SWAP32(0x00000001)},
187 /* clocks for pm0... */
188 {0x00040, SWAP32(0x00021807)},
189 {0x00044, SWAP32(0x011a0a01)},
190 {0x00054, SWAP32(0x00000000)},
Stefan Roese48a05a52006-02-07 16:51:04 +0100191 /* GPIO */
192 {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200193 /* panel control regs... */
194 {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
195 {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
Stefan Roese48a05a52006-02-07 16:51:04 +0100196 {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200197 {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
198 {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
199 {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
200 {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
201 {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
202 {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
203 {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
204 {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
205 {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
206 {0x80200, SWAP32(0x00010000)}, /* crt display control */
207 {0, 0}
208};
209
210#endif /* CONFIG_VIDEO_SM501_32BPP */
211
212#endif /* CONFIG_VIDEO_SM501 */
stroese1f54ce62004-12-16 18:23:14 +0000213
214#if 0
215#define FPGA_DEBUG
216#endif
217
218extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
219extern void lxt971_no_sleep(void);
220
221/* fpga configuration data - gzip compressed and generated by bin2c */
222const unsigned char fpgadata[] =
223{
224#include "fpgadata.c"
225};
226
227/*
228 * include common fpga code (for esd boards)
229 */
230#include "../common/fpga.c"
231
232
233/* Prototypes */
234int gunzip(void *, int, unsigned char *, unsigned long *);
235
236
237/* logo bitmap data - gzip compressed and generated by bin2c */
238unsigned char logo_bmp_320[] =
239{
240#include "logo_320_240_4bpp.c"
241};
242
243unsigned char logo_bmp_320_8bpp[] =
244{
245#include "logo_320_240_8bpp.c"
246};
247
248unsigned char logo_bmp_640[] =
249{
250#include "logo_640_480_24bpp.c"
251};
252
253unsigned char logo_bmp_1024[] =
254{
255#include "logo_1024_768_8bpp.c"
256};
257
258
259/*
260 * include common lcd code (for esd boards)
261 */
262#include "../common/lcd.c"
263
264#include "../common/s1d13704_320_240_4bpp.h"
265#include "../common/s1d13705_320_240_8bpp.h"
266#include "../common/s1d13806_640_480_16bpp.h"
267#include "../common/s1d13806_1024_768_8bpp.h"
268
269
270/*
271 * include common auto-update code (for esd boards)
272 */
273#include "../common/auto_update.h"
274
275au_image_t au_image[] = {
276 {"hh405/preinst.img", 0, -1, AU_SCRIPT},
277 {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100278 {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
stroese1f54ce62004-12-16 18:23:14 +0000279 {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
280 {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
281 {"hh405/postinst.img", 0, 0, AU_SCRIPT},
282};
283
284int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
285
286
Stefan Roese48a05a52006-02-07 16:51:04 +0100287/*
288 * Get version of HH405 board from GPIO's
289 */
stroese1f54ce62004-12-16 18:23:14 +0000290int board_revision(void)
291{
292 unsigned long osrh_reg;
293 unsigned long isr1h_reg;
294 unsigned long tcr_reg;
295 unsigned long value;
296
297 /*
stroese1f54ce62004-12-16 18:23:14 +0000298 * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
299 */
300 osrh_reg = in32(GPIO0_OSRH);
301 isr1h_reg = in32(GPIO0_ISR1H);
302 tcr_reg = in32(GPIO0_TCR);
303 out32(GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
304 out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
305 out32(GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
306
307 udelay(1000); /* wait some time before reading input */
308 value = in32(GPIO0_IR) & 0x80400000; /* get config bits */
309
310 /*
311 * Restore GPIO settings
312 */
313 out32(GPIO0_OSRH, osrh_reg); /* output select */
314 out32(GPIO0_ISR1H, isr1h_reg); /* input select */
315 out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
316
317 if (value & 0x80000000) {
318 /* Revision 1.0 or 1.1 detected */
Stefan Roese48a05a52006-02-07 16:51:04 +0100319 return 1;
stroese1f54ce62004-12-16 18:23:14 +0000320 } else {
321 if (value & 0x00400000) {
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200322 /* unused */
Stefan Roese48a05a52006-02-07 16:51:04 +0100323 return 3;
stroese1f54ce62004-12-16 18:23:14 +0000324 } else {
Stefan Roese48a05a52006-02-07 16:51:04 +0100325 return 2;
stroese1f54ce62004-12-16 18:23:14 +0000326 }
327 }
328}
329
330
331int board_early_init_f (void)
332{
333 /*
334 * IRQ 0-15 405GP internally generated; active high; level sensitive
335 * IRQ 16 405GP internally generated; active low; level sensitive
336 * IRQ 17-24 RESERVED
337 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
338 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
339 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
340 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
341 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
342 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
343 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
344 */
345 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
346 mtdcr(uicer, 0x00000000); /* disable all ints */
347 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
348 mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */
349 mtdcr(uictr, 0x10000000); /* set int trigger levels */
350 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
351 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
352
353 /*
354 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
355 */
356 mtebc (epcr, 0xa8400000); /* ebc always driven */
357
358 return 0;
359}
360
Stefan Roese48a05a52006-02-07 16:51:04 +0100361int cf_enable(void)
362{
Stefan Roese48a05a52006-02-07 16:51:04 +0100363 int i;
364
365 volatile unsigned short *fpga_ctrl =
366 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
367 volatile unsigned short *fpga_status =
368 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
369
370 if (gd->board_type >= 2) {
371 if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
372 if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
373 *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
374
375 for (i=0; i<300; i++)
376 udelay(1000);
377
378 *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
379
380 for (i=0; i<20; i++)
381 udelay(1000);
382 }
383 } else {
384 *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
385 *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
386 }
387 }
388
389 return 0;
390}
stroese1f54ce62004-12-16 18:23:14 +0000391
392int misc_init_r (void)
393{
stroese1f54ce62004-12-16 18:23:14 +0000394 volatile unsigned short *fpga_ctrl =
395 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
396 volatile unsigned short *lcd_contrast =
397 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
398 volatile unsigned short *lcd_backlight =
399 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
400 unsigned char *dst;
401 ulong len = sizeof(fpgadata);
402 int status;
403 int index;
404 int i;
405 char *str;
406 unsigned long contrast0 = 0xffffffff;
407
408 dst = malloc(CFG_FPGA_MAX_SIZE);
409 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
410 printf ("GUNZIP ERROR - must RESET board to recover\n");
411 do_reset (NULL, 0, 0, NULL);
412 }
413
414 status = fpga_boot(dst, len);
415 if (status != 0) {
416 printf("\nFPGA: Booting failed ");
417 switch (status) {
418 case ERROR_FPGA_PRG_INIT_LOW:
419 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
420 break;
421 case ERROR_FPGA_PRG_INIT_HIGH:
422 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
423 break;
424 case ERROR_FPGA_PRG_DONE:
425 printf("(Timeout: DONE not high after programming FPGA)\n ");
426 break;
427 }
428
429 /* display infos on fpgaimage */
430 index = 15;
431 for (i=0; i<4; i++) {
432 len = dst[index];
433 printf("FPGA: %s\n", &(dst[index+1]));
434 index += len+3;
435 }
436 putc ('\n');
437 /* delayed reboot */
438 for (i=20; i>0; i--) {
439 printf("Rebooting in %2d seconds \r",i);
440 for (index=0;index<1000;index++)
441 udelay(1000);
442 }
443 putc ('\n');
444 do_reset(NULL, 0, 0, NULL);
445 }
446
447 puts("FPGA: ");
448
449 /* display infos on fpgaimage */
450 index = 15;
451 for (i=0; i<4; i++) {
452 len = dst[index];
453 printf("%s ", &(dst[index+1]));
454 index += len+3;
455 }
456 putc ('\n');
457
458 free(dst);
459
460 /*
461 * Reset FPGA via FPGA_INIT pin
462 */
463 out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
464 out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
465 udelay(1000); /* wait 1ms */
466 out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
467 udelay(1000); /* wait 1ms */
468
469 /*
470 * Write Board revision into FPGA
471 */
472 *fpga_ctrl |= gd->board_type & 0x0003;
stroese1f54ce62004-12-16 18:23:14 +0000473
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200474 /*
475 * Setup and enable EEPROM write protection
476 */
477 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
478
stroese1f54ce62004-12-16 18:23:14 +0000479 /*
stroese1f54ce62004-12-16 18:23:14 +0000480 * Reset touch-screen controller
481 */
482 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
483 udelay(1000);
484 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
485
wdenkefe2a4d2004-12-16 21:44:03 +0000486 /*
487 * Enable power on PS/2 interface (with reset)
488 */
489 *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
490 for (i=0;i<500;i++)
491 udelay(1000);
492 *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
stroese1f54ce62004-12-16 18:23:14 +0000493
494 /*
495 * Get contrast value from environment variable
496 */
497 str = getenv("contrast0");
498 if (str) {
499 contrast0 = simple_strtol(str, NULL, 16);
500 if (contrast0 > 255) {
501 printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
Stefan Roese48a05a52006-02-07 16:51:04 +0100502 contrast0 = 0xffffffff;
stroese1f54ce62004-12-16 18:23:14 +0000503 }
504 }
505
506 /*
507 * Init lcd interface and display logo
508 */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200509
stroese1f54ce62004-12-16 18:23:14 +0000510 str = getenv("bd_type");
511 if (strcmp(str, "ppc230") == 0) {
512 /*
513 * Switch backlight on
514 */
515 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL;
516 *lcd_backlight = 0x0000;
517
518 lcd_setup(1, 0);
519 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
520 regs_13806_1024_768_8bpp,
521 sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
522 logo_bmp_1024, sizeof(logo_bmp_1024));
523 } else if (strcmp(str, "ppc220") == 0) {
524 /*
525 * Switch backlight on
526 */
527 *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL;
528 *lcd_backlight = 0x0000;
529
530 lcd_setup(1, 0);
531 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
532 regs_13806_640_480_16bpp,
533 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
534 logo_bmp_640, sizeof(logo_bmp_640));
535 } else if (strcmp(str, "ppc215") == 0) {
536 /*
537 * Set default display contrast voltage
538 */
539 if (contrast0 == 0xffffffff) {
540 *lcd_contrast = 0x0082;
541 } else {
542 *lcd_contrast = contrast0;
543 }
544 *lcd_backlight = 0xffff;
545 /*
546 * Switch backlight on
547 */
548 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
549 /*
550 * Set lcd clock (small epson)
551 */
552 *fpga_ctrl |= LCD_CLK_06250;
553 udelay(100); /* wait for 100 us */
554
555 lcd_setup(0, 1);
556 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
557 regs_13705_320_240_8bpp,
558 sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
559 logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
560 } else if (strcmp(str, "ppc210") == 0) {
561 /*
562 * Set default display contrast voltage
563 */
564 if (contrast0 == 0xffffffff) {
565 *lcd_contrast = 0x0060;
566 } else {
567 *lcd_contrast = contrast0;
568 }
569 *lcd_backlight = 0xffff;
570 /*
571 * Switch backlight on
572 */
573 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
574 /*
Stefan Roese48a05a52006-02-07 16:51:04 +0100575 * Set lcd clock (small epson), enable 1-wire interface
stroese1f54ce62004-12-16 18:23:14 +0000576 */
Stefan Roese48a05a52006-02-07 16:51:04 +0100577 *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
stroese1f54ce62004-12-16 18:23:14 +0000578
579 lcd_setup(0, 1);
580 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
581 regs_13704_320_240_4bpp,
582 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
583 logo_bmp_320, sizeof(logo_bmp_320));
Stefan Roese2c7b2ab2005-09-30 16:41:12 +0200584#ifdef CONFIG_VIDEO_SM501
stroese1f54ce62004-12-16 18:23:14 +0000585 } else {
Stefan Roese2c7b2ab2005-09-30 16:41:12 +0200586 pci_dev_t devbusfn;
587
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200588 /*
589 * Is SM501 connected (ppc221/ppc231)?
590 */
591 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
592 if (devbusfn != -1) {
593 puts("VGA: SM501 with 8 MB ");
594 if (strcmp(str, "ppc221") == 0) {
595 printf("(800*600, %dbpp)\n", BPP);
Stefan Roese48a05a52006-02-07 16:51:04 +0100596 *lcd_backlight = 0x002d; /* max. allowed brightness */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200597 } else if (strcmp(str, "ppc231") == 0) {
598 printf("(1024*768, %dbpp)\n", BPP);
Stefan Roese48a05a52006-02-07 16:51:04 +0100599 *lcd_backlight = 0x0000;
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200600 } else {
601 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
602 return 0;
603 }
604 } else {
605 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
606 return 0;
607 }
Stefan Roese2c7b2ab2005-09-30 16:41:12 +0200608#endif /* CONFIG_VIDEO_SM501 */
stroese1f54ce62004-12-16 18:23:14 +0000609 }
610
Stefan Roese48a05a52006-02-07 16:51:04 +0100611 cf_enable();
612
stroese1f54ce62004-12-16 18:23:14 +0000613 return (0);
614}
615
616
617/*
618 * Check Board Identity:
619 */
620
621int checkboard (void)
622{
Stefan Roese18c5e642006-01-18 20:06:44 +0100623 char str[64];
stroese1f54ce62004-12-16 18:23:14 +0000624 int i = getenv_r ("serial#", str, sizeof(str));
625
626 puts ("Board: ");
627
628 if (i == -1) {
629 puts ("### No HW ID - assuming HH405");
630 } else {
631 puts(str);
632 }
633
634 if (getenv_r("bd_type", str, sizeof(str)) != -1) {
635 printf(" (%s", str);
636 } else {
637 puts(" (Missing bd_type!");
638 }
639
640 gd->board_type = board_revision();
Stefan Roese48a05a52006-02-07 16:51:04 +0100641 printf(", Rev %ld.x)\n", gd->board_type);
stroese1f54ce62004-12-16 18:23:14 +0000642
643 return 0;
644}
645
stroese1f54ce62004-12-16 18:23:14 +0000646
647long int initdram (int board_type)
648{
649 unsigned long val;
650
651 mtdcr(memcfga, mem_mb0cf);
652 val = mfdcr(memcfgd);
653
654#if 0
655 printf("\nmb0cf=%x\n", val); /* test-only */
656 printf("strap=%x\n", mfdcr(strap)); /* test-only */
657#endif
658
659 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
660}
661
stroese1f54ce62004-12-16 18:23:14 +0000662
stroese1f54ce62004-12-16 18:23:14 +0000663#ifdef CONFIG_IDE_RESET
664void ide_set_reset(int on)
665{
666 volatile unsigned short *fpga_mode =
667 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
Stefan Roese48a05a52006-02-07 16:51:04 +0100668 volatile unsigned short *fpga_status =
669 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
stroese1f54ce62004-12-16 18:23:14 +0000670
Stefan Roese48a05a52006-02-07 16:51:04 +0100671 if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
672 (gd->board_type < 2)) {
673 /*
674 * Assert or deassert CompactFlash Reset Pin
675 */
676 if (on) { /* assert RESET */
677 cf_enable();
678 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
679 } else { /* release RESET */
680 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
681 }
stroese1f54ce62004-12-16 18:23:14 +0000682 }
683}
684#endif /* CONFIG_IDE_RESET */
685
686
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200687#if defined(CFG_EEPROM_WREN)
688/* Input: <dev_addr> I2C address of EEPROM device to enable.
689 * <state> -1: deliver current state
690 * 0: disable write
691 * 1: enable write
692 * Returns: -1: wrong device address
693 * 0: dis-/en- able done
694 * 0/1: current state if <state> was -1.
695 */
696int eeprom_write_enable (unsigned dev_addr, int state)
697{
698 if (CFG_I2C_EEPROM_ADDR != dev_addr) {
699 return -1;
700 } else {
701 switch (state) {
702 case 1:
703 /* Enable write access, clear bit GPIO_SINT2. */
704 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
705 state = 0;
706 break;
707 case 0:
708 /* Disable write access, set bit GPIO_SINT2. */
709 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
710 state = 0;
711 break;
712 default:
713 /* Read current status back. */
714 state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
715 break;
716 }
717 }
718 return state;
719}
720
721int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
722{
723 int query = argc == 1;
724 int state = 0;
725
726 if (query) {
727 /* Query write access state. */
728 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
729 if (state < 0) {
730 puts ("Query of write access state failed.\n");
731 } else {
732 printf ("Write access for device 0x%0x is %sabled.\n",
733 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
734 state = 0;
735 }
736 } else {
737 if ('0' == argv[1][0]) {
738 /* Disable write access. */
739 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
740 } else {
741 /* Enable write access. */
742 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
743 }
744 if (state < 0) {
745 puts ("Setup of write access state failed.\n");
746 }
747 }
748
749 return state;
750}
751
752U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
753 "eepwren - Enable / disable / query EEPROM write access\n",
754 NULL);
755#endif /* #if defined(CFG_EEPROM_WREN) */
756
757
758#ifdef CONFIG_VIDEO_SM501
759#ifdef CONFIG_CONSOLE_EXTRA_INFO
760/*
761 * Return text to be printed besides the logo.
762 */
763void video_get_info_str (int line_number, char *info)
764{
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200765 char str[64];
766 char str2[64];
767 int i = getenv_r("serial#", str2, sizeof(str));
768
769 if (line_number == 1) {
770 sprintf(str, " Board: ");
771
772 if (i == -1) {
773 strcat(str, "### No HW ID - assuming HH405");
774 } else {
775 strcat(str, str2);
776 }
777
778 if (getenv_r("bd_type", str2, sizeof(str2)) != -1) {
779 strcat(str, " (");
780 strcat(str, str2);
781 } else {
782 strcat(str, " (Missing bd_type!");
783 }
784
Stefan Roese48a05a52006-02-07 16:51:04 +0100785 sprintf(str2, ", Rev %ld.x)", gd->board_type);
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200786 strcat(str, str2);
787 strcpy(info, str);
788 } else {
789 info [0] = '\0';
790 }
791}
792#endif /* CONFIG_CONSOLE_EXTRA_INFO */
793
794/*
795 * Returns SM501 register base address. First thing called in the driver.
796 */
797unsigned int board_video_init (void)
798{
799 pci_dev_t devbusfn;
800 u32 addr;
801
802 /*
803 * Is SM501 connected (ppc221/ppc231)?
804 */
805 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
806 if (devbusfn != -1) {
807 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
808 return (addr & 0xfffffffe);
809 }
810
811 return 0;
812}
813
814/*
815 * Returns SM501 framebuffer address
816 */
817unsigned int board_video_get_fb (void)
818{
819 pci_dev_t devbusfn;
820 u32 addr;
821
822 /*
823 * Is SM501 connected (ppc221/ppc231)?
824 */
825 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
826 if (devbusfn != -1) {
827 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
Stefan Roese48a05a52006-02-07 16:51:04 +0100828 addr &= 0xfffffffe;
829#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
830 addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
831#endif
832 return addr;
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200833 }
834
835 return 0;
836}
837
838/*
839 * Called after initializing the SM501 and before clearing the screen.
840 */
841void board_validate_screen (unsigned int base)
842{
843}
844
845/*
846 * Return a pointer to the initialization sequence.
847 */
848const SMI_REGS *board_get_regs (void)
849{
850 char *str;
851
852 str = getenv("bd_type");
853 if (strcmp(str, "ppc221") == 0) {
854 return init_regs_800x600;
855 } else {
856 return init_regs_1024x768;
857 }
858}
859
860int board_get_width (void)
861{
862 char *str;
863
864 str = getenv("bd_type");
865 if (strcmp(str, "ppc221") == 0) {
866 return 800;
867 } else {
868 return 1024;
869 }
870}
871
872int board_get_height (void)
873{
874 char *str;
875
876 str = getenv("bd_type");
877 if (strcmp(str, "ppc221") == 0) {
878 return 600;
879 } else {
880 return 768;
881 }
882}
883
884#endif /* CONFIG_VIDEO_SM501 */
Stefan Roese48a05a52006-02-07 16:51:04 +0100885
886
887void reset_phy(void)
888{
889#ifdef CONFIG_LXT971_NO_SLEEP
890
891 /*
892 * Disable sleep mode in LXT971
893 */
894 lxt971_no_sleep();
895#endif
896}