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wdenk0157ced2002-10-21 17:04:47 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __ASM_GBL_DATA_H
25#define __ASM_GBL_DATA_H
Eran Libertyf046ccd2005-07-28 10:08:46 -050026
27#include "asm/types.h"
28
wdenk0157ced2002-10-21 17:04:47 +000029/*
30 * The following data structure is placed in some memory wich is
31 * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
32 * some locked parts of the data cache) to allow for a minimum set of
33 * global variables during system initialization (until we have set
34 * up the memory controller so that we can use RAM).
35 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
wdenk0157ced2002-10-21 17:04:47 +000037 */
38
39typedef struct global_data {
40 bd_t *bd;
41 unsigned long flags;
42 unsigned long baudrate;
Bryan O'Donoghue77ff7b72008-02-17 22:57:47 +000043 unsigned long cpu_clk; /* CPU clock in Hz! */
wdenk0157ced2002-10-21 17:04:47 +000044 unsigned long bus_clk;
Bryan O'Donoghue77ff7b72008-02-17 22:57:47 +000045#if defined(CONFIG_8xx)
46 unsigned long brg_clk;
47#endif
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050048#if defined(CONFIG_CPM2)
wdenk0157ced2002-10-21 17:04:47 +000049 /* There are many clocks on the MPC8260 - see page 9-5 */
50 unsigned long vco_out;
51 unsigned long cpm_clk;
52 unsigned long scc_clk;
53 unsigned long brg_clk;
Stefan Roesef2302d42008-08-06 14:05:38 +020054#ifdef CONFIG_PCI
55 unsigned long pci_clk;
56#endif
wdenk0157ced2002-10-21 17:04:47 +000057#endif
roy zang4c527832006-11-02 18:49:51 +080058 unsigned long mem_clk;
Peter Tyser0f898602009-05-22 17:23:24 -050059#if defined(CONFIG_MPC83xx)
Eran Libertyf046ccd2005-07-28 10:08:46 -050060 /* There are other clocks in the MPC83XX */
61 u32 csb_clk;
Peter Tyser2c7920a2009-05-22 17:23:25 -050062#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
Eran Libertyf046ccd2005-07-28 10:08:46 -050063 u32 tsec1_clk;
64 u32 tsec2_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -050065 u32 usbdr_clk;
Scott Wood0f253282007-04-16 14:34:18 -050066#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -050067#if defined (CONFIG_MPC834x)
Scott Wood0f253282007-04-16 14:34:18 -050068 u32 usbmph_clk;
Peter Tyser2c7920a2009-05-22 17:23:25 -050069#endif /* CONFIG_MPC834x */
Dave Liuc86ef2c2008-01-10 23:04:13 +080070#if defined(CONFIG_MPC8315)
Dave Liu555da612007-09-18 12:36:58 +080071 u32 tdm_clk;
72#endif
Dave Liu5f820432006-11-03 19:33:44 -060073 u32 core_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -050074 u32 enc_clk;
75 u32 lbiu_clk;
76 u32 lclk_clk;
Rafal Jaworowski6902df52005-10-17 02:39:53 +020077 u32 pci_clk;
Peter Tyser2c7920a2009-05-22 17:23:25 -050078#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
Dave Liu03051c32007-09-18 12:36:11 +080079 u32 pciexp1_clk;
80 u32 pciexp2_clk;
Dave Liu555da612007-09-18 12:36:58 +080081#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -050082#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
Dave Liu03051c32007-09-18 12:36:11 +080083 u32 sata_clk;
84#endif
Andy Flemingda9d4612007-08-14 00:14:25 -050085#if defined(CONFIG_MPC8360)
Kim Phillips35cf1552008-03-28 10:18:40 -050086 u32 mem_sec_clk;
Andy Flemingda9d4612007-08-14 00:14:25 -050087#endif /* CONFIG_MPC8360 */
88#endif
Peter Tyser2c7920a2009-05-22 17:23:25 -050089#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8536)
Kumar Galaef50d6c2008-08-12 11:14:19 -050090 u32 sdhc_clk;
91#endif
Trent Piephoada591d2008-12-03 15:16:37 -080092#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
93 u32 lbc_clk;
Poonam Aggrwal0e870982009-07-31 12:08:14 +053094 void *cpu;
Trent Piephoada591d2008-12-03 15:16:37 -080095#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
Peter Tyser0f898602009-05-22 17:23:24 -050096#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
Timur Tabi943afa22008-01-09 14:35:26 -060097 u32 i2c1_clk;
98 u32 i2c2_clk;
99#endif
Dave Liu5f820432006-11-03 19:33:44 -0600100#if defined(CONFIG_QE)
101 u32 qe_clk;
102 u32 brg_clk;
Dave Liu7737d5c2006-11-03 12:11:15 -0600103 uint mp_alloc_base;
104 uint mp_alloc_top;
Dave Liu5f820432006-11-03 19:33:44 -0600105#endif /* CONFIG_QE */
Kumar Galaf0600542008-06-11 00:44:10 -0500106#if defined(CONFIG_FSL_LAW)
107 u32 used_laws;
108#endif
wdenkcbd8a352004-02-24 02:00:03 +0000109#if defined(CONFIG_MPC5xxx)
wdenk945af8d2003-07-16 21:53:01 +0000110 unsigned long ipb_clk;
111 unsigned long pci_clk;
112#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200113#if defined(CONFIG_MPC512X)
Grzegorz Bernacki5d49e0e2008-01-11 12:03:43 +0100114 u32 ips_clk;
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200115 u32 csb_clk;
John Rigby5f91db72008-02-26 09:38:14 -0700116 u32 pci_clk;
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200117#endif /* CONFIG_MPC512X */
wdenk983fda82004-10-28 00:09:35 +0000118#if defined(CONFIG_MPC8220)
119 unsigned long bExtUart;
120 unsigned long inp_clk;
121 unsigned long pci_clk;
122 unsigned long vco_clk;
123 unsigned long pev_clk;
124 unsigned long flb_clk;
125#endif
Becky Bruceb57ca3e2008-06-09 20:37:16 -0500126 phys_size_t ram_size; /* RAM size */
wdenk0157ced2002-10-21 17:04:47 +0000127 unsigned long reloc_off; /* Relocation Offset */
128 unsigned long reset_status; /* reset status register at boot */
Peter Tyser0f898602009-05-22 17:23:24 -0500129#if defined(CONFIG_MPC83xx)
Nick Spence46497052008-08-28 14:09:19 -0700130 unsigned long arbiter_event_attributes;
131 unsigned long arbiter_event_address;
132#endif
wdenk0157ced2002-10-21 17:04:47 +0000133 unsigned long env_addr; /* Address of Environment struct */
134 unsigned long env_valid; /* Checksum of Environment valid? */
135 unsigned long have_console; /* serial_init() was called */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
wdenk0157ced2002-10-21 17:04:47 +0000137 unsigned int dp_alloc_base;
138 unsigned int dp_alloc_top;
139#endif
Stefan Roesef10493c2007-10-23 11:31:05 +0200140#if defined(CONFIG_4xx)
141 u32 uart_clk;
142#endif /* CONFIG_4xx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#if defined(CONFIG_SYS_GT_6426x)
wdenk0157ced2002-10-21 17:04:47 +0000144 unsigned int mirror_hack[16];
145#endif
wdenk756f5862005-04-03 15:51:42 +0000146#if defined(CONFIG_A3000) || \
147 defined(CONFIG_HIDDEN_DRAGON) || \
148 defined(CONFIG_MUSENKI) || \
149 defined(CONFIG_SANDPOINT)
wdenk0157ced2002-10-21 17:04:47 +0000150 void * console_addr;
151#endif
wdenkc7de8292002-11-19 11:04:11 +0000152#ifdef CONFIG_AMIGAONEG3SE
153 unsigned long relocaddr; /* Start address of U-Boot in RAM */
154#endif
wdenk0157ced2002-10-21 17:04:47 +0000155#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
156 unsigned long fb_base; /* Base address of framebuffer memory */
157#endif
wdenk667122a2003-07-15 21:50:34 +0000158#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
wdenk228f29a2002-12-08 09:53:23 +0000159 unsigned long post_log_word; /* Record POST activities */
wdenk4532cb62003-04-27 22:52:51 +0000160 unsigned long post_init_f_time; /* When post_init_f started */
wdenk228f29a2002-12-08 09:53:23 +0000161#endif
wdenk0157ced2002-10-21 17:04:47 +0000162#ifdef CONFIG_BOARD_TYPES
163 unsigned long board_type;
164#endif
wdenk4532cb62003-04-27 22:52:51 +0000165#ifdef CONFIG_MODEM_SUPPORT
166 unsigned long do_mdm_init;
167 unsigned long be_quiet;
168#endif
Stefan Roese3ad63872007-08-21 16:27:57 +0200169#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
wdenk4532cb62003-04-27 22:52:51 +0000170 unsigned long kbd_status;
wdenk8bde7f72003-06-27 21:31:46 +0000171#endif
Yuri Tikhonovd32a8742008-04-06 19:19:14 +0200172#if defined(CONFIG_WD_MAX_RATE)
173 unsigned long long wdt_last; /* trace watch-dog triggering rate */
174#endif
wdenk27b207f2003-07-24 23:38:38 +0000175 void **jt; /* jump table */
wdenk0157ced2002-10-21 17:04:47 +0000176} gd_t;
177
178/*
179 * Global Data Flags
180 */
181#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
182#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
wdenkf72da342003-10-10 10:05:42 +0000183#define GD_FLG_SILENT 0x00004 /* Silent mode */
Yuri Tikhonovb428f6a2008-02-04 14:11:03 +0100184#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
Yuri Tikhonov28a38502008-05-08 15:45:26 +0200185#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
Yuri Tikhonov0e15ddd2008-05-08 15:46:42 +0200186#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
Mark Jacksonf5c3ba72008-08-25 19:21:30 +0100187#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
wdenk0157ced2002-10-21 17:04:47 +0000188
189#if 1
Wolfgang Denke7670f62008-02-14 22:43:22 +0100190#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
wdenk0157ced2002-10-21 17:04:47 +0000191#else /* We could use plain global data, but the resulting code is bigger */
192#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
193#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
194 gd_t *gd
195#endif
196
197#endif /* __ASM_GBL_DATA_H */