blob: ec78cee7147a571aa38935dc5eed2405a09da9a0 [file] [log] [blame]
Wolfgang Denk72a087e2006-10-24 14:27:35 +02001/*
2 * Register definitions for Static Memory Controller
3 */
4#ifndef __CPU_AT32AP_HSMC3_H__
5#define __CPU_AT32AP_HSMC3_H__
6
7/* HSMC3 register offsets */
8#define HSMC3_SETUP0 0x0000
9#define HSMC3_PULSE0 0x0004
10#define HSMC3_CYCLE0 0x0008
11#define HSMC3_MODE0 0x000c
12#define HSMC3_SETUP1 0x0010
13#define HSMC3_PULSE1 0x0014
14#define HSMC3_CYCLE1 0x0018
15#define HSMC3_MODE1 0x001c
16#define HSMC3_SETUP2 0x0020
17#define HSMC3_PULSE2 0x0024
18#define HSMC3_CYCLE2 0x0028
19#define HSMC3_MODE2 0x002c
20#define HSMC3_SETUP3 0x0030
21#define HSMC3_PULSE3 0x0034
22#define HSMC3_CYCLE3 0x0038
23#define HSMC3_MODE3 0x003c
24#define HSMC3_SETUP4 0x0040
25#define HSMC3_PULSE4 0x0044
26#define HSMC3_CYCLE4 0x0048
27#define HSMC3_MODE4 0x004c
28#define HSMC3_SETUP5 0x0050
29#define HSMC3_PULSE5 0x0054
30#define HSMC3_CYCLE5 0x0058
31#define HSMC3_MODE5 0x005c
32
33/* Bitfields in SETUP0 */
34#define HSMC3_NWE_SETUP_OFFSET 0
35#define HSMC3_NWE_SETUP_SIZE 6
36#define HSMC3_NCS_WR_SETUP_OFFSET 8
37#define HSMC3_NCS_WR_SETUP_SIZE 6
38#define HSMC3_NRD_SETUP_OFFSET 16
39#define HSMC3_NRD_SETUP_SIZE 6
40#define HSMC3_NCS_RD_SETUP_OFFSET 24
41#define HSMC3_NCS_RD_SETUP_SIZE 6
42
43/* Bitfields in PULSE0 */
44#define HSMC3_NWE_PULSE_OFFSET 0
45#define HSMC3_NWE_PULSE_SIZE 7
46#define HSMC3_NCS_WR_PULSE_OFFSET 8
47#define HSMC3_NCS_WR_PULSE_SIZE 7
48#define HSMC3_NRD_PULSE_OFFSET 16
49#define HSMC3_NRD_PULSE_SIZE 7
50#define HSMC3_NCS_RD_PULSE_OFFSET 24
51#define HSMC3_NCS_RD_PULSE_SIZE 7
52
53/* Bitfields in CYCLE0 */
54#define HSMC3_NWE_CYCLE_OFFSET 0
55#define HSMC3_NWE_CYCLE_SIZE 9
56#define HSMC3_NRD_CYCLE_OFFSET 16
57#define HSMC3_NRD_CYCLE_SIZE 9
58
59/* Bitfields in MODE0 */
60#define HSMC3_READ_MODE_OFFSET 0
61#define HSMC3_READ_MODE_SIZE 1
62#define HSMC3_WRITE_MODE_OFFSET 1
63#define HSMC3_WRITE_MODE_SIZE 1
64#define HSMC3_EXNW_MODE_OFFSET 4
65#define HSMC3_EXNW_MODE_SIZE 2
66#define HSMC3_BAT_OFFSET 8
67#define HSMC3_BAT_SIZE 1
68#define HSMC3_DBW_OFFSET 12
69#define HSMC3_DBW_SIZE 2
70#define HSMC3_TDF_CYCLES_OFFSET 16
71#define HSMC3_TDF_CYCLES_SIZE 4
72#define HSMC3_TDF_MODE_OFFSET 20
73#define HSMC3_TDF_MODE_SIZE 1
74#define HSMC3_PMEN_OFFSET 24
75#define HSMC3_PMEN_SIZE 1
76#define HSMC3_PS_OFFSET 28
77#define HSMC3_PS_SIZE 2
78
79/* Bitfields in MODE1 */
80#define HSMC3_PD_OFFSET 28
81#define HSMC3_PD_SIZE 2
82
83/* Constants for READ_MODE */
84#define HSMC3_READ_MODE_NCS_CONTROLLED 0
85#define HSMC3_READ_MODE_NRD_CONTROLLED 1
86
87/* Constants for WRITE_MODE */
88#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0
89#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1
90
91/* Constants for EXNW_MODE */
92#define HSMC3_EXNW_MODE_DISABLED 0
93#define HSMC3_EXNW_MODE_RESERVED 1
94#define HSMC3_EXNW_MODE_FROZEN 2
95#define HSMC3_EXNW_MODE_READY 3
96
97/* Constants for BAT */
98#define HSMC3_BAT_BYTE_SELECT 0
99#define HSMC3_BAT_BYTE_WRITE 1
100
101/* Constants for DBW */
102#define HSMC3_DBW_8_BITS 0
103#define HSMC3_DBW_16_BITS 1
104#define HSMC3_DBW_32_BITS 2
105
106/* Bit manipulation macros */
107#define HSMC3_BIT(name) \
108 (1 << HSMC3_##name##_OFFSET)
109#define HSMC3_BF(name,value) \
110 (((value) & ((1 << HSMC3_##name##_SIZE) - 1)) \
111 << HSMC3_##name##_OFFSET)
112#define HSMC3_BFEXT(name,value) \
113 (((value) >> HSMC3_##name##_OFFSET) \
114 & ((1 << HSMC3_##name##_SIZE) - 1))
115#define HSMC3_BFINS(name,value,old)\
116 (((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) \
117 << HSMC3_##name##_OFFSET)) \
118 | HSMC3_BF(name,value))
119
120/* Register access macros */
121#define hsmc3_readl(port,reg) \
122 readl((port)->regs + HSMC3_##reg)
123#define hsmc3_writel(port,reg,value) \
124 writel((value), (port)->regs + HSMC3_##reg)
125
126#endif /* __CPU_AT32AP_HSMC3_H__ */