blob: ea4367d61d227a0c2e90f44c3a206ec5ee257c90 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001
2/******************************************************************************/
3/* */
4/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
5/* Corporation. */
6/* All rights reserved. */
7/* */
8/* This program is free software; you can redistribute it and/or modify */
9/* it under the terms of the GNU General Public License as published by */
10/* the Free Software Foundation, located in the file LICENSE. */
11/* */
12/* History: */
13/* */
14/******************************************************************************/
15
16#ifndef TIGON3_H
17#define TIGON3_H
18
19#include "bcm570x_lm.h"
20#if INCLUDE_TBI_SUPPORT
21#include "bcm570x_autoneg.h"
22#endif
23
24
25/* io defines */
26#if !defined(BIG_ENDIAN_HOST)
27#define readl(addr) \
wdenk8bde7f72003-06-27 21:31:46 +000028 (LONGSWAP((*(volatile unsigned int *)(addr))))
wdenkc6097192002-11-03 00:24:07 +000029#define writel(b,addr) \
wdenk8bde7f72003-06-27 21:31:46 +000030 ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
wdenkc6097192002-11-03 00:24:07 +000031#else
32#if 0 /* !defined(PPC603) */
33#define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr)))
34#define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b))
35#else
36#if 1
37#define readl(addr) (*(volatile unsigned int*)(addr))
38#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
39#else
40extern int sprintf(char* buf, const char* f, ...);
41static __inline unsigned int readl(void* addr){
42 char buf[128];
43 unsigned int tmp = (*(volatile unsigned int*)(addr));
44 sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0);
45 sysSerialPrintString(buf);
46 return tmp;
47}
48static __inline void writel(unsigned int b, unsigned int addr){
49 char buf[128];
50 ((*(volatile unsigned int *) (addr)) = (b));
51 sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0);
52 sysSerialPrintString(buf);
53}
54#endif
55#endif /* PPC603 */
56#endif
57
58
wdenkc6097192002-11-03 00:24:07 +000059/******************************************************************************/
60/* Constants. */
61/******************************************************************************/
62
63/* Maxim number of packet descriptors used for sending packets. */
64#define MAX_TX_PACKET_DESC_COUNT 600
65#define DEFAULT_TX_PACKET_DESC_COUNT 2
66
67/* Maximum number of packet descriptors used for receiving packets. */
68#if T3_JUMBO_RCB_ENTRY_COUNT
69#define MAX_RX_PACKET_DESC_COUNT \
70 (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT)
71#else
72#define MAX_RX_PACKET_DESC_COUNT 800
73#endif
74#define DEFAULT_RX_PACKET_DESC_COUNT 2
75
76/* Threshhold for double copying small tx packets. 0 will disable double */
77/* copying of small Tx packets. */
78#define DEFAULT_TX_COPY_BUFFER_SIZE 0
79#define MIN_TX_COPY_BUFFER_SIZE 64
80#define MAX_TX_COPY_BUFFER_SIZE 512
81
82/* Cache line. */
83#define COMMON_CACHE_LINE_SIZE 0x20
84#define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1)
85
86/* Maximum number of fragment we can handle. */
87#ifndef MAX_FRAGMENT_COUNT
88#define MAX_FRAGMENT_COUNT 32
89#endif
90
91/* B0 bug. */
92#define BCM5700_BX_MIN_FRAG_SIZE 10
93#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */
94#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
95#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
wdenk8bde7f72003-06-27 21:31:46 +000096 MAX_FRAGMENT_COUNT)
wdenkc6097192002-11-03 00:24:07 +000097
98/* MAGIC number. */
99/* #define T3_MAGIC_NUM 'KevT' */
100#define T3_FIRMWARE_MAILBOX 0x0b50
101#define T3_MAGIC_NUM 0x4B657654
102#define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b
103
104#define T3_NIC_DATA_SIG_ADDR 0x0b54
105#define T3_NIC_DATA_SIG 0x4b657654
106
107#define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58
108#define T3_NIC_CFG_LED_MODE_UNKNOWN BIT_NONE
109#define T3_NIC_CFG_LED_MODE_TRIPLE_SPEED BIT_2
110#define T3_NIC_CFG_LED_MODE_LINK_SPEED BIT_3
111#define T3_NIC_CFG_LED_MODE_OPEN_DRAIN BIT_2
112#define T3_NIC_CFG_LED_MODE_OUTPUT BIT_3
113#define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3)
114#define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE
115#define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4
116#define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5
117#define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5)
118#define T3_NIC_CFG_ENABLE_WOL BIT_6
119#define T3_NIC_CFG_ENABLE_ASF BIT_7
120#define T3_NIC_EEPROM_WP BIT_8
121
122#define T3_NIC_DATA_PHY_ID_ADDR 0x0b74
123#define T3_NIC_PHY_ID1_MASK 0xffff0000
124#define T3_NIC_PHY_ID2_MASK 0x0000ffff
125
126#define T3_CMD_MAILBOX 0x0b78
127#define T3_CMD_NICDRV_ALIVE 0x01
128#define T3_CMD_NICDRV_PAUSE_FW 0x02
129#define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03
130#define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04
131#define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05
132#define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06
133
134#define T3_CMD_LENGTH_MAILBOX 0x0b7c
135#define T3_CMD_DATA_MAILBOX 0x0b80
136
137#define T3_ASF_FW_STATUS_MAILBOX 0x0c00
138
139#define T3_DRV_STATE_MAILBOX 0x0c04
140#define T3_DRV_STATE_START 0x01
141#define T3_DRV_STATE_UNLOAD 0x02
142#define T3_DRV_STATE_WOL 0x03
143#define T3_DRV_STATE_SUSPEND 0x04
144
145#define T3_FW_RESET_TYPE_MAILBOX 0x0c08
146
147#define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14
148#define T3_MAC_ADDR_LOW_MAILBOX 0x0c18
149
150/******************************************************************************/
151/* Hardware constants. */
152/******************************************************************************/
153
154/* Number of entries in the send ring: must be 512. */
155#define T3_SEND_RCB_ENTRY_COUNT 512
156#define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1)
157
158/* Number of send RCBs. May be 1-16 but for now, only support one. */
159#define T3_MAX_SEND_RCB_COUNT 16
160
161/* Number of entries in the Standard Receive RCB. Must be 512 entries. */
162#define T3_STD_RCV_RCB_ENTRY_COUNT 512
163#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1)
164#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */
165#define MAX_STD_RCV_BUFFER_SIZE 0x600
166
167/* Number of entries in the Mini Receive RCB. This value can either be */
168/* 0, 1024. Currently Mini Receive RCB is disabled. */
169#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT
170#define T3_MINI_RCV_RCB_ENTRY_COUNT 0
171#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
172#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1)
173#define MAX_MINI_RCV_BUFFER_SIZE 512
174#define DEFAULT_MINI_RCV_BUFFER_SIZE 64
175#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */
176
177/* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */
178/* Currently, Jumbo Receive RCB is disabled. */
179#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT
180#define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0
181#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
182#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1)
183
184#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */
185#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */
186#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */
187
188#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */
189#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */
190
191/* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */
192#define T3_MAX_RCV_RETURN_RCB_COUNT 16
193
194/* Number of entries in a Receive Return ring. This value is either 1024 */
195/* or 2048. */
196#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT
197#define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024
198#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
199#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)
200
201
202/* Default coalescing parameters. */
203#define DEFAULT_RX_COALESCING_TICKS 100
204#define MAX_RX_COALESCING_TICKS 500
205#define DEFAULT_TX_COALESCING_TICKS 400
206#define MAX_TX_COALESCING_TICKS 500
207#define DEFAULT_RX_MAX_COALESCED_FRAMES 10
208#define MAX_RX_MAX_COALESCED_FRAMES 100
209#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5
210#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 42
211#define ADAPTIVE_LO_RX_COALESCING_TICKS 50
212#define ADAPTIVE_HI_RX_COALESCING_TICKS 300
213#define ADAPTIVE_LO_PKT_THRESH 30000
214#define ADAPTIVE_HI_PKT_THRESH 74000
215#define DEFAULT_TX_MAX_COALESCED_FRAMES 40
216#define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 25
217#define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75
218#define MAX_TX_MAX_COALESCED_FRAMES 100
219
220#define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25
221#define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25
222#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 5
223#define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5
224
225#define BAD_DEFAULT_VALUE 0xffffffff
226
227#define DEFAULT_STATS_COALESCING_TICKS 1000000
228#define MAX_STATS_COALESCING_TICKS 3600000000U
229
230
231/* Receive BD Replenish thresholds. */
232#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4
233#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4
234
235#define SPLIT_MODE_DISABLE 0
236#define SPLIT_MODE_ENABLE 1
237
238#define SPLIT_MODE_5704_MAX_REQ 3
239
240/* Maximum physical fragment size. */
241#define MAX_FRAGMENT_SIZE (64 * 1024)
242
243
244/* Standard view. */
245#define T3_STD_VIEW_SIZE (64 * 1024)
246#define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024)
247
248
249/* Buffer descriptor base address on the NIC's memory. */
250
251#define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000
252#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000
253#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000
254
255#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000
256#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000
257#define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000
258
259#define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \
wdenk8bde7f72003-06-27 21:31:46 +0000260 sizeof(T3_SND_BD) / 4)
wdenkc6097192002-11-03 00:24:07 +0000261
262#define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \
wdenk8bde7f72003-06-27 21:31:46 +0000263 sizeof(T3_RCV_BD) / 4)
wdenkc6097192002-11-03 00:24:07 +0000264
265#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
wdenk8bde7f72003-06-27 21:31:46 +0000266 sizeof(T3_EXT_RCV_BD) / 4)
wdenkc6097192002-11-03 00:24:07 +0000267
268
269/* MBUF pool. */
270#define T3_NIC_MBUF_POOL_ADDR 0x8000
271/* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */
272#define T3_NIC_MBUF_POOL_SIZE96 0x18000
273#define T3_NIC_MBUF_POOL_SIZE64 0x10000
274
275
276#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000
277
278/* DMA descriptor pool */
279#define T3_NIC_DMA_DESC_POOL_ADDR 0x2000
280#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */
281
282#define T3_DEF_DMA_MBUF_LOW_WMARK 0x40
283#define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20
284#define T3_DEF_MBUF_HIGH_WMARK 0x60
285
286#define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304
287#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152
288#define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380
289
290#define T3_DEF_DMA_DESC_LOW_WMARK 5
291#define T3_DEF_DMA_DESC_HIGH_WMARK 10
292
293/* Maximum size of giant TCP packet can be sent */
294#define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000
295#define T3_TCP_SEG_MIN_NUM_SEG 20
296
297#define T3_RX_CPU_ID 0x1
298#define T3_TX_CPU_ID 0x2
299#define T3_RX_CPU_SPAD_ADDR 0x30000
300#define T3_RX_CPU_SPAD_SIZE 0x4000
301#define T3_TX_CPU_SPAD_ADDR 0x34000
302#define T3_TX_CPU_SPAD_SIZE 0x4000
303
304typedef struct T3_DIR_ENTRY
305{
306 PLM_UINT8 Buffer;
307 LM_UINT32 Offset;
308 LM_UINT32 Length;
309} T3_DIR_ENTRY,*PT3_DIR_ENTRY;
310
311typedef struct T3_FWIMG_INFO
312{
313 LM_UINT32 StartAddress;
314 T3_DIR_ENTRY Text;
315 T3_DIR_ENTRY ROnlyData;
316 T3_DIR_ENTRY Data;
317 T3_DIR_ENTRY Sbss;
318 T3_DIR_ENTRY Bss;
319} T3_FWIMG_INFO, *PT3_FWIMG_INFO;
320
321
wdenkc6097192002-11-03 00:24:07 +0000322/******************************************************************************/
323/* Tigon3 PCI Registers. */
324/******************************************************************************/
325#define T3_PCI_ID_BCM5700 0x164414e4
326#define T3_PCI_ID_BCM5701 0x164514e4
327#define T3_PCI_ID_BCM5702 0x164614e4
328#define T3_PCI_ID_BCM5702x 0x16A614e4
329#define T3_PCI_ID_BCM5703 0x164714e4
330#define T3_PCI_ID_BCM5703x 0x16A714e4
331#define T3_PCI_ID_BCM5702FE 0x164D14e4
332#define T3_PCI_ID_BCM5704 0x164814e4
333
334#define T3_PCI_VENDOR_ID (T3_PCI_ID & 0xffff)
335#define T3_PCI_DEVICE_ID (T3_PCI_ID >> 16)
336
337#define T3_PCI_MISC_HOST_CTRL_REG 0x68
338
339/* The most significant 16bit of register 0x68. */
340/* ChipId:4, ChipRev:4, MetalRev:8 */
341#define T3_CHIP_ID_5700_A0 0x7000
342#define T3_CHIP_ID_5700_A1 0x7001
343#define T3_CHIP_ID_5700_B0 0x7100
344#define T3_CHIP_ID_5700_B1 0x7101
345#define T3_CHIP_ID_5700_C0 0x7200
346
347#define T3_CHIP_ID_5701_A0 0x0000
348#define T3_CHIP_ID_5701_B0 0x0100
349#define T3_CHIP_ID_5701_B2 0x0102
350#define T3_CHIP_ID_5701_B5 0x0105
351
352#define T3_CHIP_ID_5703_A0 0x1000
353#define T3_CHIP_ID_5703_A1 0x1001
354#define T3_CHIP_ID_5703_A2 0x1002
355
356#define T3_CHIP_ID_5704_A0 0x2000
357
358/* Chip Id. */
359#define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12)
360#define T3_ASIC_REV_5700 0x07
361#define T3_ASIC_REV_5701 0x00
362#define T3_ASIC_REV_5703 0x01
363#define T3_ASIC_REV_5704 0x02
364
365
366/* Chip id and revision. */
367#define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8)
368#define T3_CHIP_REV_5700_AX 0x70
369#define T3_CHIP_REV_5700_BX 0x71
370#define T3_CHIP_REV_5700_CX 0x72
371#define T3_CHIP_REV_5701_AX 0x00
372
373/* Metal revision. */
374#define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff)
375#define T3_METAL_REV_A0 0x00
376#define T3_METAL_REV_A1 0x01
377#define T3_METAL_REV_B0 0x00
378#define T3_METAL_REV_B1 0x01
379#define T3_METAL_REV_B2 0x02
380
381#define T3_PCI_REG_CLOCK_CTRL 0x74
382
383#define T3_PCI_DISABLE_RX_CLOCK BIT_10
384#define T3_PCI_DISABLE_TX_CLOCK BIT_11
385#define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12
386#define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15
387#define T3_PCI_44MHZ_CORE_CLOCK BIT_18
388
389
390#define T3_PCI_REG_ADDR_REG 0x78
391#define T3_PCI_REG_DATA_REG 0x80
392
393#define T3_PCI_MEM_WIN_ADDR_REG 0x7c
394#define T3_PCI_MEM_WIN_DATA_REG 0x84
395
396#define T3_PCI_PM_CAP_REG 0x48
397
398#define T3_PCI_PM_CAP_PME_D3COLD BIT_31
399#define T3_PCI_PM_CAP_PME_D3HOT BIT_30
400
401#define T3_PCI_PM_STATUS_CTRL_REG 0x4c
402
403#define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1)
404#define T3_PM_POWER_STATE_D0 BIT_NONE
405#define T3_PM_POWER_STATE_D1 BIT_0
406#define T3_PM_POWER_STATE_D2 BIT_1
407#define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1)
408
409#define T3_PM_PME_ENABLE BIT_8
410#define T3_PM_PME_ASSERTED BIT_15
411
412
413/* PCI state register. */
414#define T3_PCI_STATE_REG 0x70
415
416#define T3_PCI_STATE_FORCE_RESET BIT_0
417#define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1
418#define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2
419#define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3
420#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
421
422
423/* Broadcom subsystem/subvendor IDs. */
424#define T3_SVID_BROADCOM 0x14e4
425
426#define T3_SSID_BROADCOM_BCM95700A6 0x1644
427#define T3_SSID_BROADCOM_BCM95701A5 0x0001
428#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */
429#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */
430#define T3_SSID_BROADCOM_BCM95701T1 0x0005
431#define T3_SSID_BROADCOM_BCM95701T8 0x0006
432#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */
433#define T3_SSID_BROADCOM_BCM95701A10 0x0008
434#define T3_SSID_BROADCOM_BCM95701A12 0x8008
435#define T3_SSID_BROADCOM_BCM95703Ax1 0x0009
436#define T3_SSID_BROADCOM_BCM95703Ax2 0x8009
437
438/* 3COM subsystem/subvendor IDs. */
439#define T3_SVID_3COM 0x10b7
440
441#define T3_SSID_3COM_3C996T 0x1000
442#define T3_SSID_3COM_3C996BT 0x1006
443#define T3_SSID_3COM_3C996CT 0x1002
444#define T3_SSID_3COM_3C997T 0x1003
445#define T3_SSID_3COM_3C1000T 0x1007
446#define T3_SSID_3COM_3C940BR01 0x1008
447
448/* Fiber boards. */
449#define T3_SSID_3COM_3C996SX 0x1004
450#define T3_SSID_3COM_3C997SX 0x1005
451
452
453/* Dell subsystem/subvendor IDs. */
454
455#define T3_SVID_DELL 0x1028
456
457#define T3_SSID_DELL_VIPER 0x00d1
458#define T3_SSID_DELL_JAGUAR 0x0106
459#define T3_SSID_DELL_MERLOT 0x0109
460#define T3_SSID_DELL_SLIM_MERLOT 0x010a
461
462/* Compaq subsystem/subvendor IDs */
463
464#define T3_SVID_COMPAQ 0x0e11
465
466#define T3_SSID_COMPAQ_BANSHEE 0x007c
467#define T3_SSID_COMPAQ_BANSHEE_2 0x009a
468#define T3_SSID_COMPAQ_CHANGELING 0x007d
469#define T3_SSID_COMPAQ_NC7780 0x0085
470#define T3_SSID_COMPAQ_NC7780_2 0x0099
471
472
473/******************************************************************************/
474/* MII registers. */
475/******************************************************************************/
476
477/* Control register. */
478#define PHY_CTRL_REG 0x00
479
480#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13)
481#define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE
482#define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13
483#define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6
484#define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7
485#define PHY_CTRL_FULL_DUPLEX_MODE BIT_8
486#define PHY_CTRL_RESTART_AUTO_NEG BIT_9
487#define PHY_CTRL_ISOLATE_PHY BIT_10
488#define PHY_CTRL_LOWER_POWER_MODE BIT_11
489#define PHY_CTRL_AUTO_NEG_ENABLE BIT_12
490#define PHY_CTRL_LOOPBACK_MODE BIT_14
491#define PHY_CTRL_PHY_RESET BIT_15
492
493
494/* Status register. */
495#define PHY_STATUS_REG 0x01
496
497#define PHY_STATUS_LINK_PASS BIT_2
498#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5
499
500
501/* Phy Id registers. */
502#define PHY_ID1_REG 0x02
503#define PHY_ID1_OUI_MASK 0xffff
504
505#define PHY_ID2_REG 0x03
506#define PHY_ID2_REV_MASK 0x000f
507#define PHY_ID2_MODEL_MASK 0x03f0
508#define PHY_ID2_OUI_MASK 0xfc00
509
510
511/* Auto-negotiation advertisement register. */
512#define PHY_AN_AD_REG 0x04
513
514#define PHY_AN_AD_ASYM_PAUSE BIT_11
515#define PHY_AN_AD_PAUSE_CAPABLE BIT_10
516#define PHY_AN_AD_10BASET_HALF BIT_5
517#define PHY_AN_AD_10BASET_FULL BIT_6
518#define PHY_AN_AD_100BASETX_HALF BIT_7
519#define PHY_AN_AD_100BASETX_FULL BIT_8
520#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01
521
522
523/* Auto-negotiation Link Partner Ability register. */
524#define PHY_LINK_PARTNER_ABILITY_REG 0x05
525
526#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11
527#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10
528
529
530/* Auto-negotiation expansion register. */
531#define PHY_AN_EXPANSION_REG 0x06
532
533
wdenkc6097192002-11-03 00:24:07 +0000534/******************************************************************************/
535/* BCM5400 and BCM5401 phy info. */
536/******************************************************************************/
537
538#define PHY_DEVICE_ID 1
539
540/* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */
541#define PHY_UNKNOWN_PHY 0x00000000
542#define PHY_BCM5400_PHY_ID 0x60008040
543#define PHY_BCM5401_PHY_ID 0x60008050
544#define PHY_BCM5411_PHY_ID 0x60008070
545#define PHY_BCM5701_PHY_ID 0x60008110
546#define PHY_BCM5703_PHY_ID 0x60008160
547#define PHY_BCM5704_PHY_ID 0x60008190
548#define PHY_BCM8002_PHY_ID 0x60010140
549
550#define PHY_BCM5401_B0_REV 0x1
551#define PHY_BCM5401_B2_REV 0x3
552#define PHY_BCM5401_C0_REV 0x6
553
554#define PHY_ID_OUI_MASK 0xfffffc00
555#define PHY_ID_MODEL_MASK 0x000003f0
556#define PHY_ID_REV_MASK 0x0000000f
557#define PHY_ID_MASK (PHY_ID_OUI_MASK | \
wdenk8bde7f72003-06-27 21:31:46 +0000558 PHY_ID_MODEL_MASK)
wdenkc6097192002-11-03 00:24:07 +0000559
560
561#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
wdenk8bde7f72003-06-27 21:31:46 +0000562 (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
563 (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
564 (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \
565 (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \
566 (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
567 (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
wdenkc6097192002-11-03 00:24:07 +0000568
569
570/* 1000Base-T control register. */
571#define BCM540X_1000BASET_CTRL_REG 0x09
572
573#define BCM540X_AN_AD_1000BASET_HALF BIT_8
574#define BCM540X_AN_AD_1000BASET_FULL BIT_9
575#define BCM540X_CONFIG_AS_MASTER BIT_11
576#define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12
577
578
579/* Extended control register. */
580#define BCM540X_EXT_CTRL_REG 0x10
581
582#define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1
583#define BCM540X_EXT_CTRL_TBI BIT_15
584
585/* PHY extended status register. */
586#define BCM540X_EXT_STATUS_REG 0x11
587
588#define BCM540X_EXT_STATUS_LINK_PASS BIT_8
589
590
591/* DSP Coefficient Read/Write Port. */
592#define BCM540X_DSP_RW_PORT 0x15
593
594
595/* DSP Coeficient Address Register. */
596#define BCM540X_DSP_ADDRESS_REG 0x17
597
598#define BCM540X_DSP_TAP_NUMBER_MASK 0x00
599#define BCM540X_DSP_AGC_A 0x00
600#define BCM540X_DSP_AGC_B 0x01
601#define BCM540X_DSP_MSE_PAIR_STATUS 0x02
602#define BCM540X_DSP_SOFT_DECISION 0x03
603#define BCM540X_DSP_PHASE_REG 0x04
604#define BCM540X_DSP_SKEW 0x05
605#define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06
606#define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07
607#define BCM540X_DSP_LAST_ECHO 0x08
608#define BCM540X_DSP_FREQUENCY 0x09
609#define BCM540X_DSP_PLL_BANDWIDTH 0x0a
610#define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b
611
612#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11)
613#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11)
614#define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11)
615#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11)
616#define BCM540X_DSP_FILTER_FEXT0 BIT_11
617#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10)
618#define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10)
619#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10)
620#define BCM540X_DSP_FILTER_NEXT0 BIT_10
621#define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9)
622#define BCM540X_DSP_FILTER_DFE BIT_9
623#define BCM540X_DSP_FILTER_FFE BIT_8
624
625#define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12
626
627#define BCM540X_DSP_SEL_CH_0 BIT_NONE
628#define BCM540X_DSP_SEL_CH_1 BIT_13
629#define BCM540X_DSP_SEL_CH_2 BIT_14
630#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14)
631
632#define BCM540X_CONTROL_ALL_CHANNELS BIT_15
633
634
635/* Auxilliary Control Register (Shadow Register) */
636#define BCM5401_AUX_CTRL 0x18
637
638#define BCM5401_SHADOW_SEL_MASK 0x7
639#define BCM5401_SHADOW_SEL_NORMAL 0x00
640#define BCM5401_SHADOW_SEL_10BASET 0x01
641#define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02
642#define BCM5401_SHADOW_SEL_IP_PHONE 0x03
643#define BCM5401_SHADOW_SEL_MISC_TEST1 0x04
644#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05
645#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06
646
647
648/* Shadow register selector == '000' */
649#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3
650#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4
651#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5
652#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6
653#define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7
654#define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE
655#define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8
656#define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9
657#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9)
658#define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10
659#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11
660#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE
661#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12
662#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13
663#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13)
664#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14
665#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15
666
667
668/* Auxilliary status summary. */
669#define BCM540X_AUX_STATUS_REG 0x19
670
671#define BCM540X_AUX_LINK_PASS BIT_2
672#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10)
673#define BCM540X_AUX_10BASET_HD BIT_8
674#define BCM540X_AUX_10BASET_FD BIT_9
675#define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9)
676#define BCM540X_AUX_100BASET4 BIT_10
677#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10)
678#define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10)
679#define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10)
680
681
682/* Interrupt status. */
683#define BCM540X_INT_STATUS_REG 0x1a
684
685#define BCM540X_INT_LINK_CHANGE BIT_1
686#define BCM540X_INT_SPEED_CHANGE BIT_2
687#define BCM540X_INT_DUPLEX_CHANGE BIT_3
688#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10
689
690
691/* Interrupt mask register. */
692#define BCM540X_INT_MASK_REG 0x1b
693
694
wdenkc6097192002-11-03 00:24:07 +0000695/******************************************************************************/
696/* Register definitions. */
697/******************************************************************************/
698
699typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER;
700typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER;
701typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;
702
703typedef struct {
704 /* Big endian format. */
705 T3_32BIT_REGISTER High;
706 T3_32BIT_REGISTER Low;
707} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER;
708
709typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
710
711#define T3_NUM_OF_DMA_DESC 256
712#define T3_NUM_OF_MBUF 768
713
714typedef struct
715{
716 T3_64BIT_REGISTER host_addr;
717 T3_32BIT_REGISTER nic_mbuf;
718 T3_16BIT_REGISTER len;
719 T3_16BIT_REGISTER cqid_sqid;
720 T3_32BIT_REGISTER flags;
721 T3_32BIT_REGISTER opaque1;
722 T3_32BIT_REGISTER opaque2;
723 T3_32BIT_REGISTER opaque3;
724}T3_DMA_DESC, *PT3_DMA_DESC;
725
726
wdenkc6097192002-11-03 00:24:07 +0000727/******************************************************************************/
728/* Ring control block. */
729/******************************************************************************/
730
731typedef struct {
732 T3_64BIT_REGISTER HostRingAddr;
733
734 union {
wdenk8bde7f72003-06-27 21:31:46 +0000735 struct {
wdenkc6097192002-11-03 00:24:07 +0000736#ifdef BIG_ENDIAN_HOST
wdenk8bde7f72003-06-27 21:31:46 +0000737 T3_16BIT_REGISTER MaxLen;
738 T3_16BIT_REGISTER Flags;
wdenkc6097192002-11-03 00:24:07 +0000739#else /* BIG_ENDIAN_HOST */
wdenk8bde7f72003-06-27 21:31:46 +0000740 T3_16BIT_REGISTER Flags;
741 T3_16BIT_REGISTER MaxLen;
wdenkc6097192002-11-03 00:24:07 +0000742#endif
wdenk8bde7f72003-06-27 21:31:46 +0000743 } s;
wdenkc6097192002-11-03 00:24:07 +0000744
wdenk8bde7f72003-06-27 21:31:46 +0000745 T3_32BIT_REGISTER MaxLen_Flags;
wdenkc6097192002-11-03 00:24:07 +0000746 } u;
747
748 T3_32BIT_REGISTER NicRingAddr;
749} T3_RCB, *PT3_RCB;
750
751#define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0
752#define T3_RCB_FLAG_RING_DISABLED BIT_1
753
754
wdenkc6097192002-11-03 00:24:07 +0000755/******************************************************************************/
756/* Status block. */
757/******************************************************************************/
758
759/*
760 * Size of status block is actually 0x50 bytes. Use 0x80 bytes for
761 * cache line alignment.
762 */
763#define T3_STATUS_BLOCK_SIZE 0x80
764
765typedef struct {
766 volatile LM_UINT32 Status;
767 #define STATUS_BLOCK_UPDATED BIT_0
768 #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1
769 #define STATUS_BLOCK_ERROR BIT_2
770
771 volatile LM_UINT32 StatusTag;
772
773#ifdef BIG_ENDIAN_HOST
774 volatile LM_UINT16 RcvStdConIdx;
775 volatile LM_UINT16 RcvJumboConIdx;
776
777 volatile LM_UINT16 Reserved2;
778 volatile LM_UINT16 RcvMiniConIdx;
779
780 struct {
wdenk8bde7f72003-06-27 21:31:46 +0000781 volatile LM_UINT16 SendConIdx; /* Send consumer index. */
782 volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
wdenkc6097192002-11-03 00:24:07 +0000783 } Idx[16];
784#else /* BIG_ENDIAN_HOST */
785 volatile LM_UINT16 RcvJumboConIdx;
786 volatile LM_UINT16 RcvStdConIdx;
787
788 volatile LM_UINT16 RcvMiniConIdx;
789 volatile LM_UINT16 Reserved2;
790
791 struct {
wdenk8bde7f72003-06-27 21:31:46 +0000792 volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */
793 volatile LM_UINT16 SendConIdx; /* Send consumer index. */
wdenkc6097192002-11-03 00:24:07 +0000794 } Idx[16];
795#endif
796} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
797
798
wdenkc6097192002-11-03 00:24:07 +0000799/******************************************************************************/
800/* Receive buffer descriptors. */
801/******************************************************************************/
802
803typedef struct {
804 T3_64BIT_HOST_ADDR HostAddr;
805
806#ifdef BIG_ENDIAN_HOST
807 volatile LM_UINT16 Index;
808 volatile LM_UINT16 Len;
809
810 volatile LM_UINT16 Type;
811 volatile LM_UINT16 Flags;
812
813 volatile LM_UINT16 IpCksum;
814 volatile LM_UINT16 TcpUdpCksum;
815
816 volatile LM_UINT16 ErrorFlag;
817 volatile LM_UINT16 VlanTag;
818#else /* BIG_ENDIAN_HOST */
819 volatile LM_UINT16 Len;
820 volatile LM_UINT16 Index;
821
822 volatile LM_UINT16 Flags;
823 volatile LM_UINT16 Type;
824
825 volatile LM_UINT16 TcpUdpCksum;
826 volatile LM_UINT16 IpCksum;
827
828 volatile LM_UINT16 VlanTag;
829 volatile LM_UINT16 ErrorFlag;
830#endif
831
832 volatile LM_UINT32 Reserved;
833 volatile LM_UINT32 Opaque;
834} T3_RCV_BD, *PT3_RCV_BD;
835
836
837typedef struct {
838 T3_64BIT_HOST_ADDR HostAddr[3];
839
840#ifdef BIG_ENDIAN_HOST
841 LM_UINT16 Len1;
842 LM_UINT16 Len2;
843
844 LM_UINT16 Len3;
845 LM_UINT16 Reserved1;
846#else /* BIG_ENDIAN_HOST */
847 LM_UINT16 Len2;
848 LM_UINT16 Len1;
849
850 LM_UINT16 Reserved1;
851 LM_UINT16 Len3;
852#endif
853
854 T3_RCV_BD StdRcvBd;
855} T3_EXT_RCV_BD, *PT3_EXT_RCV_BD;
856
857
858/* Error flags. */
859#define RCV_BD_ERR_BAD_CRC 0x0001
860#define RCV_BD_ERR_COLL_DETECT 0x0002
861#define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004
862#define RCV_BD_ERR_PHY_DECODE_ERR 0x0008
863#define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010
864#define RCV_BD_ERR_MAC_ABORT 0x0020
865#define RCV_BD_ERR_LEN_LT_64 0x0040
866#define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080
867#define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100
868
869
870/* Buffer descriptor flags. */
871#define RCV_BD_FLAG_END 0x0004
872#define RCV_BD_FLAG_JUMBO_RING 0x0020
873#define RCV_BD_FLAG_VLAN_TAG 0x0040
874#define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400
875#define RCV_BD_FLAG_MINI_RING 0x0800
876#define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000
877#define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000
878#define RCV_BD_FLAG_TCP_PACKET 0x4000
879
880
wdenkc6097192002-11-03 00:24:07 +0000881/******************************************************************************/
882/* Send buffer descriptor. */
883/******************************************************************************/
884
885typedef struct {
886 T3_64BIT_HOST_ADDR HostAddr;
887
888 union {
wdenk8bde7f72003-06-27 21:31:46 +0000889 struct {
wdenkc6097192002-11-03 00:24:07 +0000890#ifdef BIG_ENDIAN_HOST
wdenk8bde7f72003-06-27 21:31:46 +0000891 LM_UINT16 Len;
892 LM_UINT16 Flags;
wdenkc6097192002-11-03 00:24:07 +0000893#else /* BIG_ENDIAN_HOST */
wdenk8bde7f72003-06-27 21:31:46 +0000894 LM_UINT16 Flags;
895 LM_UINT16 Len;
wdenkc6097192002-11-03 00:24:07 +0000896#endif
wdenk8bde7f72003-06-27 21:31:46 +0000897 } s1;
wdenkc6097192002-11-03 00:24:07 +0000898
wdenk8bde7f72003-06-27 21:31:46 +0000899 LM_UINT32 Len_Flags;
wdenkc6097192002-11-03 00:24:07 +0000900 } u1;
901
902 union {
wdenk8bde7f72003-06-27 21:31:46 +0000903 struct {
wdenkc6097192002-11-03 00:24:07 +0000904#ifdef BIG_ENDIAN_HOST
wdenk8bde7f72003-06-27 21:31:46 +0000905 LM_UINT16 Reserved;
906 LM_UINT16 VlanTag;
wdenkc6097192002-11-03 00:24:07 +0000907#else /* BIG_ENDIAN_HOST */
wdenk8bde7f72003-06-27 21:31:46 +0000908 LM_UINT16 VlanTag;
909 LM_UINT16 Reserved;
wdenkc6097192002-11-03 00:24:07 +0000910#endif
wdenk8bde7f72003-06-27 21:31:46 +0000911 } s2;
wdenkc6097192002-11-03 00:24:07 +0000912
wdenk8bde7f72003-06-27 21:31:46 +0000913 LM_UINT32 VlanTag;
wdenkc6097192002-11-03 00:24:07 +0000914 } u2;
915} T3_SND_BD, *PT3_SND_BD;
916
917
918/* Send buffer descriptor flags. */
919#define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001
920#define SND_BD_FLAG_IP_CKSUM 0x0002
921#define SND_BD_FLAG_END 0x0004
922#define SND_BD_FLAG_IP_FRAG 0x0008
923#define SND_BD_FLAG_IP_FRAG_END 0x0010
924#define SND_BD_FLAG_VLAN_TAG 0x0040
925#define SND_BD_FLAG_COAL_NOW 0x0080
926#define SND_BD_FLAG_CPU_PRE_DMA 0x0100
927#define SND_BD_FLAG_CPU_POST_DMA 0x0200
928#define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000
929#define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000
930#define SND_BD_FLAG_DONT_GEN_CRC 0x8000
931
932/* MBUFs */
933typedef struct T3_MBUF_FRAME_DESC {
934#ifdef BIG_ENDIAN_HOST
935 LM_UINT32 status_control;
936 union {
937 struct {
938 LM_UINT8 cqid;
939 LM_UINT8 reserved1;
940 LM_UINT16 length;
941 }s1;
942 LM_UINT32 word;
943 }u1;
944 union {
945 struct
946 {
947 LM_UINT16 ip_hdr_start;
948 LM_UINT16 tcp_udp_hdr_start;
949 }s2;
950
951 LM_UINT32 word;
952 }u2;
953
954 union {
955 struct {
956 LM_UINT16 data_start;
957 LM_UINT16 vlan_id;
958 }s3;
959
960 LM_UINT32 word;
961 }u3;
962
963 union {
964 struct {
965 LM_UINT16 ip_checksum;
966 LM_UINT16 tcp_udp_checksum;
967 }s4;
968
969 LM_UINT32 word;
970 }u4;
971
972 union {
973 struct {
974 LM_UINT16 pseudo_checksum;
975 LM_UINT16 checksum_status;
976 }s5;
977
978 LM_UINT32 word;
979 }u5;
980
981 union {
982 struct {
983 LM_UINT16 rule_match;
984 LM_UINT8 class;
985 LM_UINT8 rupt;
986 }s6;
987
988 LM_UINT32 word;
989 }u6;
990
991 union {
992 struct {
993 LM_UINT16 reserved2;
994 LM_UINT16 mbuf_num;
995 }s7;
996
997 LM_UINT32 word;
998 }u7;
999
1000 LM_UINT32 reserved3;
1001 LM_UINT32 reserved4;
1002#else
1003 LM_UINT32 status_control;
1004 union {
1005 struct {
1006 LM_UINT16 length;
1007 LM_UINT8 reserved1;
1008 LM_UINT8 cqid;
1009 }s1;
1010 LM_UINT32 word;
1011 }u1;
1012 union {
1013 struct
1014 {
1015 LM_UINT16 tcp_udp_hdr_start;
1016 LM_UINT16 ip_hdr_start;
1017 }s2;
1018
1019 LM_UINT32 word;
1020 }u2;
1021
1022 union {
1023 struct {
1024 LM_UINT16 vlan_id;
1025 LM_UINT16 data_start;
1026 }s3;
1027
1028 LM_UINT32 word;
1029 }u3;
1030
1031 union {
1032 struct {
1033 LM_UINT16 tcp_udp_checksum;
1034 LM_UINT16 ip_checksum;
1035 }s4;
1036
1037 LM_UINT32 word;
1038 }u4;
1039
1040 union {
1041 struct {
1042 LM_UINT16 checksum_status;
1043 LM_UINT16 pseudo_checksum;
1044 }s5;
1045
1046 LM_UINT32 word;
1047 }u5;
1048
1049 union {
1050 struct {
1051 LM_UINT8 rupt;
1052 LM_UINT8 class;
1053 LM_UINT16 rule_match;
1054 }s6;
1055
1056 LM_UINT32 word;
1057 }u6;
1058
1059 union {
1060 struct {
1061 LM_UINT16 mbuf_num;
1062 LM_UINT16 reserved2;
1063 }s7;
1064
1065 LM_UINT32 word;
1066 }u7;
1067
1068 LM_UINT32 reserved3;
1069 LM_UINT32 reserved4;
1070#endif
1071}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC;
1072
1073typedef struct T3_MBUF_HDR {
1074 union {
1075 struct {
1076 unsigned int C:1;
1077 unsigned int F:1;
1078 unsigned int reserved1:7;
1079 unsigned int next_mbuf:16;
1080 unsigned int length:7;
1081 }s1;
1082
1083 LM_UINT32 word;
1084 }u1;
1085
1086 LM_UINT32 next_frame_ptr;
1087}T3_MBUF_HDR, *PT3_MBUF_HDR;
1088
1089typedef struct T3_MBUF
1090{
1091 T3_MBUF_HDR hdr;
1092 union
1093 {
1094 struct {
1095 T3_MBUF_FRAME_DESC frame_hdr;
1096 LM_UINT32 data[20];
1097 }s1;
1098
1099 struct {
1100 LM_UINT32 data[30];
1101 }s2;
1102 }body;
1103}T3_MBUF, *PT3_MBUF;
1104
1105#define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7)
1106#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
1107
1108
wdenkc6097192002-11-03 00:24:07 +00001109/******************************************************************************/
1110/* Statistics block. */
1111/******************************************************************************/
1112
1113typedef struct {
1114 LM_UINT8 Reserved0[0x400-0x300];
1115
1116 /* Statistics maintained by Receive MAC. */
1117 T3_64BIT_REGISTER ifHCInOctets;
1118 T3_64BIT_REGISTER Reserved1;
1119 T3_64BIT_REGISTER etherStatsFragments;
1120 T3_64BIT_REGISTER ifHCInUcastPkts;
1121 T3_64BIT_REGISTER ifHCInMulticastPkts;
1122 T3_64BIT_REGISTER ifHCInBroadcastPkts;
1123 T3_64BIT_REGISTER dot3StatsFCSErrors;
1124 T3_64BIT_REGISTER dot3StatsAlignmentErrors;
1125 T3_64BIT_REGISTER xonPauseFramesReceived;
1126 T3_64BIT_REGISTER xoffPauseFramesReceived;
1127 T3_64BIT_REGISTER macControlFramesReceived;
1128 T3_64BIT_REGISTER xoffStateEntered;
1129 T3_64BIT_REGISTER dot3StatsFramesTooLong;
1130 T3_64BIT_REGISTER etherStatsJabbers;
1131 T3_64BIT_REGISTER etherStatsUndersizePkts;
1132 T3_64BIT_REGISTER inRangeLengthError;
1133 T3_64BIT_REGISTER outRangeLengthError;
1134 T3_64BIT_REGISTER etherStatsPkts64Octets;
1135 T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
1136 T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
1137 T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
1138 T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
1139 T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
1140 T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
1141 T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
1142 T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
1143 T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
1144
1145 T3_64BIT_REGISTER Unused1[37];
1146
1147 /* Statistics maintained by Transmit MAC. */
1148 T3_64BIT_REGISTER ifHCOutOctets;
1149 T3_64BIT_REGISTER Reserved2;
1150 T3_64BIT_REGISTER etherStatsCollisions;
1151 T3_64BIT_REGISTER outXonSent;
1152 T3_64BIT_REGISTER outXoffSent;
1153 T3_64BIT_REGISTER flowControlDone;
1154 T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
1155 T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
1156 T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
1157 T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
1158 T3_64BIT_REGISTER Reserved3;
1159 T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
1160 T3_64BIT_REGISTER dot3StatsLateCollisions;
1161 T3_64BIT_REGISTER dot3Collided2Times;
1162 T3_64BIT_REGISTER dot3Collided3Times;
1163 T3_64BIT_REGISTER dot3Collided4Times;
1164 T3_64BIT_REGISTER dot3Collided5Times;
1165 T3_64BIT_REGISTER dot3Collided6Times;
1166 T3_64BIT_REGISTER dot3Collided7Times;
1167 T3_64BIT_REGISTER dot3Collided8Times;
1168 T3_64BIT_REGISTER dot3Collided9Times;
1169 T3_64BIT_REGISTER dot3Collided10Times;
1170 T3_64BIT_REGISTER dot3Collided11Times;
1171 T3_64BIT_REGISTER dot3Collided12Times;
1172 T3_64BIT_REGISTER dot3Collided13Times;
1173 T3_64BIT_REGISTER dot3Collided14Times;
1174 T3_64BIT_REGISTER dot3Collided15Times;
1175 T3_64BIT_REGISTER ifHCOutUcastPkts;
1176 T3_64BIT_REGISTER ifHCOutMulticastPkts;
1177 T3_64BIT_REGISTER ifHCOutBroadcastPkts;
1178 T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
1179 T3_64BIT_REGISTER ifOutDiscards;
1180 T3_64BIT_REGISTER ifOutErrors;
1181
1182 T3_64BIT_REGISTER Unused2[31];
1183
1184 /* Statistics maintained by Receive List Placement. */
1185 T3_64BIT_REGISTER COSIfHCInPkts[16];
1186 T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
1187 T3_64BIT_REGISTER nicDmaWriteQueueFull;
1188 T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
1189 T3_64BIT_REGISTER nicNoMoreRxBDs;
1190 T3_64BIT_REGISTER ifInDiscards;
1191 T3_64BIT_REGISTER ifInErrors;
1192 T3_64BIT_REGISTER nicRecvThresholdHit;
1193
1194 T3_64BIT_REGISTER Unused3[9];
1195
1196 /* Statistics maintained by Send Data Initiator. */
1197 T3_64BIT_REGISTER COSIfHCOutPkts[16];
1198 T3_64BIT_REGISTER nicDmaReadQueueFull;
1199 T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
1200 T3_64BIT_REGISTER nicSendDataCompQueueFull;
1201
1202 /* Statistics maintained by Host Coalescing. */
1203 T3_64BIT_REGISTER nicRingSetSendProdIndex;
1204 T3_64BIT_REGISTER nicRingStatusUpdate;
1205 T3_64BIT_REGISTER nicInterrupts;
1206 T3_64BIT_REGISTER nicAvoidedInterrupts;
1207 T3_64BIT_REGISTER nicSendThresholdHit;
1208
1209 LM_UINT8 Reserved4[0xb00-0x9c0];
1210} T3_STATS_BLOCK, *PT3_STATS_BLOCK;
1211
1212
wdenkc6097192002-11-03 00:24:07 +00001213/******************************************************************************/
1214/* PCI configuration registers. */
1215/******************************************************************************/
1216
1217typedef struct {
1218 T3_16BIT_REGISTER VendorId;
1219 T3_16BIT_REGISTER DeviceId;
1220
1221 T3_16BIT_REGISTER Command;
1222 T3_16BIT_REGISTER Status;
1223
1224 T3_32BIT_REGISTER ClassCodeRevId;
1225
1226 T3_8BIT_REGISTER CacheLineSize;
1227 T3_8BIT_REGISTER LatencyTimer;
1228 T3_8BIT_REGISTER HeaderType;
1229 T3_8BIT_REGISTER Bist;
1230
1231 T3_32BIT_REGISTER MemBaseAddrLow;
1232 T3_32BIT_REGISTER MemBaseAddrHigh;
1233
1234 LM_UINT8 Unused1[20];
1235
1236 T3_16BIT_REGISTER SubsystemVendorId;
1237 T3_16BIT_REGISTER SubsystemId;
1238
1239 T3_32BIT_REGISTER RomBaseAddr;
1240
1241 T3_8BIT_REGISTER PciXCapiblityPtr;
1242 LM_UINT8 Unused2[7];
1243
1244 T3_8BIT_REGISTER IntLine;
1245 T3_8BIT_REGISTER IntPin;
1246 T3_8BIT_REGISTER MinGnt;
1247 T3_8BIT_REGISTER MaxLat;
1248
1249 T3_8BIT_REGISTER PciXCapabilities;
1250 T3_8BIT_REGISTER PmCapabilityPtr;
1251 T3_16BIT_REGISTER PciXCommand;
1252
1253 T3_32BIT_REGISTER PciXStatus;
1254
1255 T3_8BIT_REGISTER PmCapabilityId;
1256 T3_8BIT_REGISTER VpdCapabilityPtr;
1257 T3_16BIT_REGISTER PmCapabilities;
1258
1259 T3_16BIT_REGISTER PmCtrlStatus;
1260 #define PM_CTRL_PME_STATUS BIT_15
1261 #define PM_CTRL_PME_ENABLE BIT_8
1262 #define PM_CTRL_PME_POWER_STATE_D0 0
1263 #define PM_CTRL_PME_POWER_STATE_D1 1
1264 #define PM_CTRL_PME_POWER_STATE_D2 2
1265 #define PM_CTRL_PME_POWER_STATE_D3H 3
1266
1267 T3_8BIT_REGISTER BridgeSupportExt;
1268 T3_8BIT_REGISTER PmData;
1269
1270 T3_8BIT_REGISTER VpdCapabilityId;
1271 T3_8BIT_REGISTER MsiCapabilityPtr;
1272 T3_16BIT_REGISTER VpdAddrFlag;
1273 #define VPD_FLAG_WRITE (1 << 15)
1274 #define VPD_FLAG_RW_MASK (1 << 15)
1275 #define VPD_FLAG_READ 0
1276
1277
1278 T3_32BIT_REGISTER VpdData;
1279
1280 T3_8BIT_REGISTER MsiCapabilityId;
1281 T3_8BIT_REGISTER NextCapabilityPtr;
1282 T3_16BIT_REGISTER MsiCtrl;
1283 #define MSI_CTRL_64BIT_CAP (1 << 7)
1284 #define MSI_CTRL_MSG_ENABLE(x) (x << 4)
1285 #define MSI_CTRL_MSG_CAP(x) (x << 1)
1286 #define MSI_CTRL_ENABLE (1 << 0)
1287
1288
1289 T3_32BIT_REGISTER MsiAddrLow;
1290 T3_32BIT_REGISTER MsiAddrHigh;
1291
1292 T3_16BIT_REGISTER MsiData;
1293 T3_16BIT_REGISTER Unused3;
1294
1295 T3_32BIT_REGISTER MiscHostCtrl;
1296 #define MISC_HOST_CTRL_CLEAR_INT BIT_0
1297 #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1
1298 #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2
1299 #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3
1300 #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4
1301 #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5
1302 #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6
1303 #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7
1304 #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8
1305 #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9
1306
1307 T3_32BIT_REGISTER DmaReadWriteCtrl;
1308 #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13)
1309 #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0
1310 #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11
1311 #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12
1312 #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11)
1313 #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13
1314 #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11)
1315 #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12)
1316 #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11)
1317 #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14
1318
1319
1320 T3_32BIT_REGISTER PciState;
1321 #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0
1322 #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1
1323 #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2
1324 #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3
1325 #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4
1326 #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5
1327 #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6
1328 #define T3_PCI_STATE_FLAT_VIEW BIT_8
1329 #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13
1330
1331 T3_32BIT_REGISTER ClockCtrl;
1332 #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11
1333 #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10
1334 #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9
1335
1336 T3_32BIT_REGISTER RegBaseAddr;
1337
1338 T3_32BIT_REGISTER MemWindowBaseAddr;
1339
1340#ifdef NIC_CPU_VIEW
1341 /* These registers are ONLY visible to NIC CPU */
1342 T3_32BIT_REGISTER PowerConsumed;
1343 T3_32BIT_REGISTER PowerDissipated;
1344#else /* NIC_CPU_VIEW */
1345 T3_32BIT_REGISTER RegData;
1346 T3_32BIT_REGISTER MemWindowData;
1347#endif /* !NIC_CPU_VIEW */
1348
1349 T3_32BIT_REGISTER ModeCtrl;
1350
1351 T3_32BIT_REGISTER MiscCfg;
1352
1353 T3_32BIT_REGISTER MiscLocalCtrl;
1354
1355 T3_32BIT_REGISTER Unused4;
1356
1357 /* NOTE: Big/Little-endian clarification needed. Are these register */
1358 /* in big or little endian formate. */
1359 T3_64BIT_REGISTER StdRingProdIdx;
1360 T3_64BIT_REGISTER RcvRetRingConIdx;
1361 T3_64BIT_REGISTER SndProdIdx;
1362
1363 LM_UINT8 Unused5[80];
1364} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION;
1365
1366#define PCIX_CMD_MAX_SPLIT_MASK 0x0070
1367#define PCIX_CMD_MAX_SPLIT_SHL 4
1368#define PCIX_CMD_MAX_BURST_MASK 0x000c
1369#define PCIX_CMD_MAX_BURST_SHL 2
1370#define PCIX_CMD_MAX_BURST_CPIOB 2
1371
1372/******************************************************************************/
1373/* Mac control registers. */
1374/******************************************************************************/
1375
1376typedef struct {
1377 /* MAC mode control. */
1378 T3_32BIT_REGISTER Mode;
1379 #define MAC_MODE_GLOBAL_RESET BIT_0
1380 #define MAC_MODE_HALF_DUPLEX BIT_1
1381 #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3)
1382 #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3)
1383 #define MAC_MODE_PORT_MODE_GMII BIT_3
1384 #define MAC_MODE_PORT_MODE_MII BIT_2
1385 #define MAC_MODE_PORT_MODE_NONE BIT_NONE
1386 #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4
1387 #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7
1388 #define MAC_MODE_TX_BURSTING BIT_8
1389 #define MAC_MODE_MAX_DEFER BIT_9
1390 #define MAC_MODE_LINK_POLARITY BIT_10
1391 #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11
1392 #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12
1393 #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13
1394 #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14
1395 #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15
1396 #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16
1397 #define MAC_MODE_SEND_CONFIGS BIT_17
1398 #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18
1399 #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19
1400 #define MAC_MODE_ENABLE_MIP BIT_20
1401 #define MAC_MODE_ENABLE_TDE BIT_21
1402 #define MAC_MODE_ENABLE_RDE BIT_22
1403 #define MAC_MODE_ENABLE_FHDE BIT_23
1404
1405 /* MAC status */
1406 T3_32BIT_REGISTER Status;
1407 #define MAC_STATUS_PCS_SYNCED BIT_0
1408 #define MAC_STATUS_SIGNAL_DETECTED BIT_1
1409 #define MAC_STATUS_RECEIVING_CFG BIT_2
1410 #define MAC_STATUS_CFG_CHANGED BIT_3
1411 #define MAC_STATUS_SYNC_CHANGED BIT_4
1412 #define MAC_STATUS_PORT_DECODE_ERROR BIT_10
1413 #define MAC_STATUS_LINK_STATE_CHANGED BIT_12
1414 #define MAC_STATUS_MI_COMPLETION BIT_22
1415 #define MAC_STATUS_MI_INTERRUPT BIT_23
1416 #define MAC_STATUS_AP_ERROR BIT_24
1417 #define MAC_STATUS_ODI_ERROR BIT_25
1418 #define MAC_STATUS_RX_STATS_OVERRUN BIT_26
1419 #define MAC_STATUS_TX_STATS_OVERRUN BIT_27
1420
1421 /* Event Enable */
1422 T3_32BIT_REGISTER MacEvent;
1423 #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10
1424 #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12
1425 #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22
1426 #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23
1427 #define MAC_EVENT_ENABLE_AP_ERROR BIT_24
1428 #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25
1429 #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26
1430 #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27
1431
1432 /* Led control. */
1433 T3_32BIT_REGISTER LedCtrl;
1434 #define LED_CTRL_OVERRIDE_LINK_LED BIT_0
1435 #define LED_CTRL_1000MBPS_LED_ON BIT_1
1436 #define LED_CTRL_100MBPS_LED_ON BIT_2
1437 #define LED_CTRL_10MBPS_LED_ON BIT_3
1438 #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4
1439 #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5
1440 #define LED_CTRL_TRAFFIC_LED BIT_6
1441 #define LED_CTRL_1000MBPS_LED_STATUS BIT_7
1442 #define LED_CTRL_100MBPS_LED_STATUS BIT_8
1443 #define LED_CTRL_10MBPS_LED_STATUS BIT_9
1444 #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10
1445 #define LED_CTRL_MAC_MODE BIT_NONE
1446 #define LED_CTRL_PHY_MODE_1 BIT_11
1447 #define LED_CTRL_PHY_MODE_2 BIT_12
1448 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
1449 #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19
1450 #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31
1451
1452 /* MAC addresses. */
1453 struct {
wdenk8bde7f72003-06-27 21:31:46 +00001454 T3_32BIT_REGISTER High; /* Upper 2 bytes. */
1455 T3_32BIT_REGISTER Low; /* Lower 4 bytes. */
wdenkc6097192002-11-03 00:24:07 +00001456 } MacAddr[4];
1457
1458 /* ACPI Mbuf pointer. */
1459 T3_32BIT_REGISTER AcpiMbufPtr;
1460
1461 /* ACPI Length and Offset. */
1462 T3_32BIT_REGISTER AcpiLengthOffset;
1463 #define ACPI_LENGTH_MASK 0xffff
1464 #define ACPI_OFFSET_MASK 0x0fff0000
1465 #define ACPI_LENGTH(x) x
1466 #define ACPI_OFFSET(x) ((x) << 16)
1467
1468 /* Transmit random backoff. */
1469 T3_32BIT_REGISTER TxBackoffSeed;
1470 #define MAC_TX_BACKOFF_SEED_MASK 0x3ff
1471
1472 /* Receive MTU */
1473 T3_32BIT_REGISTER MtuSize;
1474 #define MAC_RX_MTU_MASK 0xffff
1475
1476 /* Gigabit PCS Test. */
1477 T3_32BIT_REGISTER PcsTest;
1478 #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff
1479 #define MAC_PCS_TEST_ENABLE BIT_20
1480
1481 /* Transmit Gigabit Auto-Negotiation. */
1482 T3_32BIT_REGISTER TxAutoNeg;
1483 #define MAC_AN_TX_AN_DATA_MASK 0xffff
1484
1485 /* Receive Gigabit Auto-Negotiation. */
1486 T3_32BIT_REGISTER RxAutoNeg;
1487 #define MAC_AN_RX_AN_DATA_MASK 0xffff
1488
1489 /* MI Communication. */
1490 T3_32BIT_REGISTER MiCom;
1491 #define MI_COM_CMD_MASK (BIT_26 | BIT_27)
1492 #define MI_COM_CMD_WRITE BIT_26
1493 #define MI_COM_CMD_READ BIT_27
1494 #define MI_COM_READ_FAILED BIT_28
1495 #define MI_COM_START BIT_29
1496 #define MI_COM_BUSY BIT_29
1497
1498 #define MI_COM_PHY_ADDR_MASK 0x1f
1499 #define MI_COM_FIRST_PHY_ADDR_BIT 21
1500
1501 #define MI_COM_PHY_REG_ADDR_MASK 0x1f
1502 #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16
1503
1504 #define MI_COM_PHY_DATA_MASK 0xffff
1505
1506 /* MI Status. */
1507 T3_32BIT_REGISTER MiStatus;
1508 #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0
1509
1510 /* MI Mode. */
1511 T3_32BIT_REGISTER MiMode;
1512 #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0
1513 #define MI_MODE_USE_SHORT_PREAMBLE BIT_1
1514 #define MI_MODE_AUTO_POLLING_ENABLE BIT_4
1515 #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15
1516
1517 /* Auto-polling status. */
1518 T3_32BIT_REGISTER AutoPollStatus;
1519 #define AUTO_POLL_ERROR BIT_0
1520
1521 /* Transmit MAC mode. */
1522 T3_32BIT_REGISTER TxMode;
1523 #define TX_MODE_RESET BIT_0
1524 #define TX_MODE_ENABLE BIT_1
1525 #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4
1526 #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5
1527 #define TX_MODE_ENABLE_LONG_PAUSE BIT_6
1528
1529 /* Transmit MAC status. */
1530 T3_32BIT_REGISTER TxStatus;
1531 #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0
1532 #define TX_STATUS_SENT_XOFF BIT_1
1533 #define TX_STATUS_SENT_XON BIT_2
1534 #define TX_STATUS_LINK_UP BIT_3
1535 #define TX_STATUS_ODI_UNDERRUN BIT_4
1536 #define TX_STATUS_ODI_OVERRUN BIT_5
1537
1538 /* Transmit MAC length. */
1539 T3_32BIT_REGISTER TxLengths;
1540 #define TX_LEN_SLOT_TIME_MASK 0xff
1541 #define TX_LEN_IPG_MASK 0x0f00
1542 #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13)
1543
1544 /* Receive MAC mode. */
1545 T3_32BIT_REGISTER RxMode;
1546 #define RX_MODE_RESET BIT_0
1547 #define RX_MODE_ENABLE BIT_1
1548 #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2
1549 #define RX_MODE_KEEP_MAC_CONTROL BIT_3
1550 #define RX_MODE_KEEP_PAUSE BIT_4
1551 #define RX_MODE_ACCEPT_OVERSIZED BIT_5
1552 #define RX_MODE_ACCEPT_RUNTS BIT_6
1553 #define RX_MODE_LENGTH_CHECK BIT_7
1554 #define RX_MODE_PROMISCUOUS_MODE BIT_8
1555 #define RX_MODE_NO_CRC_CHECK BIT_9
1556 #define RX_MODE_KEEP_VLAN_TAG BIT_10
1557
1558 /* Receive MAC status. */
1559 T3_32BIT_REGISTER RxStatus;
1560 #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0
1561 #define RX_STATUS_XOFF_RECEIVED BIT_1
1562 #define RX_STATUS_XON_RECEIVED BIT_2
1563
1564 /* Hash registers. */
1565 T3_32BIT_REGISTER HashReg[4];
1566
1567 /* Receive placement rules registers. */
1568 struct {
wdenk8bde7f72003-06-27 21:31:46 +00001569 T3_32BIT_REGISTER Rule;
1570 T3_32BIT_REGISTER Value;
wdenkc6097192002-11-03 00:24:07 +00001571 } RcvRules[16];
1572
1573 #define RCV_DISABLE_RULE_MASK 0x7fffffff
1574
1575 #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00
1576 #define REJECT_BROADCAST_RULE1_RULE 0xc2000000
1577 #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff
1578
1579 #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01
1580 #define REJECT_BROADCAST_RULE2_RULE 0x86000004
1581 #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff
1582
1583#if INCLUDE_5701_AX_FIX
1584 #define RCV_LAST_RULE_IDX 0x04
1585#else
1586 #define RCV_LAST_RULE_IDX 0x02
1587#endif
1588
1589 T3_32BIT_REGISTER RcvRuleCfg;
1590 #define RX_RULE_DEFAULT_CLASS (1 << 3)
1591
1592 LM_UINT8 Reserved1[140];
1593
1594 T3_32BIT_REGISTER SerdesCfg;
1595 T3_32BIT_REGISTER SerdesStatus;
1596
1597 LM_UINT8 Reserved2[104];
1598
1599 volatile LM_UINT8 TxMacState[16];
1600 volatile LM_UINT8 RxMacState[20];
1601
1602 LM_UINT8 Reserved3[476];
1603
1604 T3_32BIT_REGISTER RxStats[26];
1605
1606 LM_UINT8 Reserved4[24];
1607
1608 T3_32BIT_REGISTER TxStats[28];
1609
1610 LM_UINT8 Reserved5[784];
1611} T3_MAC_CONTROL, *PT3_MAC_CONTROL;
1612
1613
wdenkc6097192002-11-03 00:24:07 +00001614/******************************************************************************/
1615/* Send data initiator control registers. */
1616/******************************************************************************/
1617
1618typedef struct {
1619 T3_32BIT_REGISTER Mode;
1620 #define T3_SND_DATA_IN_MODE_RESET BIT_0
1621 #define T3_SND_DATA_IN_MODE_ENABLE BIT_1
1622 #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2
1623
1624 T3_32BIT_REGISTER Status;
1625 #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2
1626
1627 T3_32BIT_REGISTER StatsCtrl;
1628 #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0
1629 #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1
1630 #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2
1631 #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3
1632 #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4
1633
1634 T3_32BIT_REGISTER StatsEnableMask;
1635 T3_32BIT_REGISTER StatsIncMask;
1636
1637 LM_UINT8 Reserved[108];
1638
1639 T3_32BIT_REGISTER ClassOfServCnt[16];
1640 T3_32BIT_REGISTER DmaReadQFullCnt;
1641 T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
1642 T3_32BIT_REGISTER SdcQFullCnt;
1643
1644 T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
1645 T3_32BIT_REGISTER StatusUpdatedCnt;
1646 T3_32BIT_REGISTER InterruptsCnt;
1647 T3_32BIT_REGISTER AvoidInterruptsCnt;
1648 T3_32BIT_REGISTER SendThresholdHitCnt;
1649
1650 /* Unused space. */
1651 LM_UINT8 Unused[800];
1652} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
1653
1654
wdenkc6097192002-11-03 00:24:07 +00001655/******************************************************************************/
1656/* Send data completion control registers. */
1657/******************************************************************************/
1658
1659typedef struct {
1660 T3_32BIT_REGISTER Mode;
1661 #define SND_DATA_COMP_MODE_RESET BIT_0
1662 #define SND_DATA_COMP_MODE_ENABLE BIT_1
1663
1664 /* Unused space. */
1665 LM_UINT8 Unused[1020];
1666} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
1667
1668
wdenkc6097192002-11-03 00:24:07 +00001669/******************************************************************************/
1670/* Send BD Ring Selector Control Registers. */
1671/******************************************************************************/
1672
1673typedef struct {
1674 T3_32BIT_REGISTER Mode;
1675 #define SND_BD_SEL_MODE_RESET BIT_0
1676 #define SND_BD_SEL_MODE_ENABLE BIT_1
1677 #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2
1678
1679 T3_32BIT_REGISTER Status;
1680 #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2
1681
1682 T3_32BIT_REGISTER HwDiag;
1683
1684 /* Unused space. */
1685 LM_UINT8 Unused1[52];
1686
1687 /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
1688 T3_32BIT_REGISTER NicSendBdSelConIdx[16];
1689
1690 /* Unused space. */
1691 LM_UINT8 Unused2[896];
1692} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
1693
1694
wdenkc6097192002-11-03 00:24:07 +00001695/******************************************************************************/
1696/* Send BD initiator control registers. */
1697/******************************************************************************/
1698
1699typedef struct {
1700 T3_32BIT_REGISTER Mode;
1701 #define SND_BD_IN_MODE_RESET BIT_0
1702 #define SND_BD_IN_MODE_ENABLE BIT_1
1703 #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2
1704
1705 T3_32BIT_REGISTER Status;
1706 #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2
1707
1708 /* Send BD initiator local NIC send BD producer index. */
1709 T3_32BIT_REGISTER NicSendBdInProdIdx[16];
1710
1711 /* Unused space. */
1712 LM_UINT8 Unused2[952];
1713} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
1714
1715
wdenkc6097192002-11-03 00:24:07 +00001716/******************************************************************************/
1717/* Send BD Completion Control. */
1718/******************************************************************************/
1719
1720typedef struct {
1721 T3_32BIT_REGISTER Mode;
1722 #define SND_BD_COMP_MODE_RESET BIT_0
1723 #define SND_BD_COMP_MODE_ENABLE BIT_1
1724 #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2
1725
1726 /* Unused space. */
1727 LM_UINT8 Unused2[1020];
1728} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
1729
1730
wdenkc6097192002-11-03 00:24:07 +00001731/******************************************************************************/
1732/* Receive list placement control registers. */
1733/******************************************************************************/
1734
1735typedef struct {
1736 /* Mode. */
1737 T3_32BIT_REGISTER Mode;
1738 #define RCV_LIST_PLMT_MODE_RESET BIT_0
1739 #define RCV_LIST_PLMT_MODE_ENABLE BIT_1
1740 #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2
1741 #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3
1742 #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4
1743
1744 /* Status. */
1745 T3_32BIT_REGISTER Status;
1746 #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2
1747 #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3
1748 #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4
1749
1750 /* Receive selector list lock register. */
1751 T3_32BIT_REGISTER Lock;
1752 #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff
1753 #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000
1754
1755 /* Selector non-empty bits. */
1756 T3_32BIT_REGISTER NonEmptyBits;
1757 #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff
1758
1759 /* Receive list placement configuration register. */
1760 T3_32BIT_REGISTER Config;
1761
1762 /* Receive List Placement statistics Control. */
1763 T3_32BIT_REGISTER StatsCtrl;
1764#define RCV_LIST_STATS_ENABLE BIT_0
1765#define RCV_LIST_STATS_FAST_UPDATE BIT_1
1766
1767 /* Receive List Placement statistics Enable Mask. */
1768 T3_32BIT_REGISTER StatsEnableMask;
1769
1770 /* Receive List Placement statistics Increment Mask. */
1771 T3_32BIT_REGISTER StatsIncMask;
1772
1773 /* Unused space. */
1774 LM_UINT8 Unused1[224];
1775
1776 struct {
wdenk8bde7f72003-06-27 21:31:46 +00001777 T3_32BIT_REGISTER Head;
1778 T3_32BIT_REGISTER Tail;
1779 T3_32BIT_REGISTER Count;
wdenkc6097192002-11-03 00:24:07 +00001780
wdenk8bde7f72003-06-27 21:31:46 +00001781 /* Unused space. */
1782 LM_UINT8 Unused[4];
wdenkc6097192002-11-03 00:24:07 +00001783 } RcvSelectorList[16];
1784
1785 /* Local statistics counter. */
1786 T3_32BIT_REGISTER ClassOfServCnt[16];
1787
1788 T3_32BIT_REGISTER DropDueToFilterCnt;
1789 T3_32BIT_REGISTER DmaWriteQFullCnt;
1790 T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
1791 T3_32BIT_REGISTER NoMoreReceiveBdCnt;
1792 T3_32BIT_REGISTER IfInDiscardsCnt;
1793 T3_32BIT_REGISTER IfInErrorsCnt;
1794 T3_32BIT_REGISTER RcvThresholdHitCnt;
1795
1796 /* Another unused space. */
1797 LM_UINT8 Unused2[420];
1798} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
1799
1800
wdenkc6097192002-11-03 00:24:07 +00001801/******************************************************************************/
1802/* Receive Data and Receive BD Initiator Control. */
1803/******************************************************************************/
1804
1805typedef struct {
1806 /* Mode. */
1807 T3_32BIT_REGISTER Mode;
1808 #define RCV_DATA_BD_IN_MODE_RESET BIT_0
1809 #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1
1810 #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2
1811 #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3
1812 #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4
1813
1814 /* Status. */
1815 T3_32BIT_REGISTER Status;
1816 #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2
1817 #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3
1818 #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4
1819
1820 /* Split frame minium size. */
1821 T3_32BIT_REGISTER SplitFrameMinSize;
1822
1823 /* Unused space. */
1824 LM_UINT8 Unused1[0x2440-0x240c];
1825
1826 /* Receive RCBs. */
1827 T3_RCB JumboRcvRcb;
1828 T3_RCB StdRcvRcb;
1829 T3_RCB MiniRcvRcb;
1830
1831 /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
1832 /* BD Consumber Index. */
1833 T3_32BIT_REGISTER NicJumboConIdx;
1834 T3_32BIT_REGISTER NicStdConIdx;
1835 T3_32BIT_REGISTER NicMiniConIdx;
1836
1837 /* Unused space. */
1838 LM_UINT8 Unused2[4];
1839
1840 /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
1841 T3_32BIT_REGISTER RcvDataBdProdIdx[16];
1842
1843 /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
1844 T3_32BIT_REGISTER HwDiag;
1845
1846 /* Unused space. */
1847 LM_UINT8 Unused3[828];
1848} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
1849
1850
wdenkc6097192002-11-03 00:24:07 +00001851/******************************************************************************/
1852/* Receive Data Completion Control Registes. */
1853/******************************************************************************/
1854
1855typedef struct {
1856 T3_32BIT_REGISTER Mode;
1857 #define RCV_DATA_COMP_MODE_RESET BIT_0
1858 #define RCV_DATA_COMP_MODE_ENABLE BIT_1
1859 #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2
1860
1861 /* Unused spaced. */
1862 LM_UINT8 Unused[1020];
1863} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
1864
1865
wdenkc6097192002-11-03 00:24:07 +00001866/******************************************************************************/
1867/* Receive BD Initiator Control. */
1868/******************************************************************************/
1869
1870typedef struct {
1871 T3_32BIT_REGISTER Mode;
1872 #define RCV_BD_IN_MODE_RESET BIT_0
1873 #define RCV_BD_IN_MODE_ENABLE BIT_1
1874 #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2
1875
1876 T3_32BIT_REGISTER Status;
1877 #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2
1878
1879 T3_32BIT_REGISTER NicJumboRcvProdIdx;
1880 T3_32BIT_REGISTER NicStdRcvProdIdx;
1881 T3_32BIT_REGISTER NicMiniRcvProdIdx;
1882
1883 T3_32BIT_REGISTER MiniRcvThreshold;
1884 T3_32BIT_REGISTER StdRcvThreshold;
1885 T3_32BIT_REGISTER JumboRcvThreshold;
1886
1887 /* Unused space. */
1888 LM_UINT8 Unused[992];
1889} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
1890
1891
wdenkc6097192002-11-03 00:24:07 +00001892/******************************************************************************/
1893/* Receive BD Completion Control Registers. */
1894/******************************************************************************/
1895
1896typedef struct {
1897 T3_32BIT_REGISTER Mode;
1898 #define RCV_BD_COMP_MODE_RESET BIT_0
1899 #define RCV_BD_COMP_MODE_ENABLE BIT_1
1900 #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2
1901
1902 T3_32BIT_REGISTER Status;
1903 #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2
1904
1905 T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
1906 T3_32BIT_REGISTER NicStdRcvBdProdIdx;
1907 T3_32BIT_REGISTER NicMiniRcvBdProdIdx;
1908
1909 /* Unused space. */
1910 LM_UINT8 Unused[1004];
1911} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
1912
1913
wdenkc6097192002-11-03 00:24:07 +00001914/******************************************************************************/
1915/* Receive list selector control register. */
1916/******************************************************************************/
1917
1918typedef struct {
1919 T3_32BIT_REGISTER Mode;
1920 #define RCV_LIST_SEL_MODE_RESET BIT_0
1921 #define RCV_LIST_SEL_MODE_ENABLE BIT_1
1922 #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2
1923
1924 T3_32BIT_REGISTER Status;
1925 #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2
1926
1927 /* Unused space. */
1928 LM_UINT8 Unused[1016];
1929} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
1930
1931
wdenkc6097192002-11-03 00:24:07 +00001932/******************************************************************************/
1933/* Mbuf cluster free registers. */
1934/******************************************************************************/
1935
1936typedef struct {
1937 T3_32BIT_REGISTER Mode;
1938#define MBUF_CLUSTER_FREE_MODE_RESET BIT_0
1939#define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1
1940
1941 T3_32BIT_REGISTER Status;
1942
1943 /* Unused space. */
1944 LM_UINT8 Unused[1016];
1945} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
1946
1947
wdenkc6097192002-11-03 00:24:07 +00001948/******************************************************************************/
1949/* Host coalescing control registers. */
1950/******************************************************************************/
1951
1952typedef struct {
1953 /* Mode. */
1954 T3_32BIT_REGISTER Mode;
1955 #define HOST_COALESCE_RESET BIT_0
1956 #define HOST_COALESCE_ENABLE BIT_1
1957 #define HOST_COALESCE_ATTN BIT_2
1958 #define HOST_COALESCE_NOW BIT_3
1959 #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE
1960 #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7
1961 #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8
1962 #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9
1963 #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10
1964 #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11
1965 #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12
1966
1967 /* Status. */
1968 T3_32BIT_REGISTER Status;
1969 #define HOST_COALESCE_ERROR_ATTN BIT_2
1970
1971 /* Receive coalescing ticks. */
1972 T3_32BIT_REGISTER RxCoalescingTicks;
1973
1974 /* Send coalescing ticks. */
1975 T3_32BIT_REGISTER TxCoalescingTicks;
1976
1977 /* Receive max coalesced frames. */
1978 T3_32BIT_REGISTER RxMaxCoalescedFrames;
1979
1980 /* Send max coalesced frames. */
1981 T3_32BIT_REGISTER TxMaxCoalescedFrames;
1982
1983 /* Receive coalescing ticks during interrupt. */
1984 T3_32BIT_REGISTER RxCoalescedTickDuringInt;
1985
1986 /* Send coalescing ticks during interrupt. */
1987 T3_32BIT_REGISTER TxCoalescedTickDuringInt;
1988
1989 /* Receive max coalesced frames during interrupt. */
1990 T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;
1991
1992 /* Send max coalesced frames during interrupt. */
1993 T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;
1994
1995 /* Statistics tick. */
1996 T3_32BIT_REGISTER StatsCoalescingTicks;
1997
1998 /* Unused space. */
1999 LM_UINT8 Unused2[4];
2000
2001 /* Statistics host address. */
2002 T3_64BIT_REGISTER StatsBlkHostAddr;
2003
2004 /* Status block host address.*/
2005 T3_64BIT_REGISTER StatusBlkHostAddr;
2006
2007 /* Statistics NIC address. */
2008 T3_32BIT_REGISTER StatsBlkNicAddr;
2009
2010 /* Statust block NIC address. */
2011 T3_32BIT_REGISTER StatusBlkNicAddr;
2012
2013 /* Flow attention registers. */
2014 T3_32BIT_REGISTER FlowAttn;
2015
2016 /* Unused space. */
2017 LM_UINT8 Unused3[4];
2018
2019 T3_32BIT_REGISTER NicJumboRcvBdConIdx;
2020 T3_32BIT_REGISTER NicStdRcvBdConIdx;
2021 T3_32BIT_REGISTER NicMiniRcvBdConIdx;
2022
2023 /* Unused space. */
2024 LM_UINT8 Unused4[36];
2025
2026 T3_32BIT_REGISTER NicRetProdIdx[16];
2027 T3_32BIT_REGISTER NicSndBdConIdx[16];
2028
2029 /* Unused space. */
2030 LM_UINT8 Unused5[768];
2031} T3_HOST_COALESCING, *PT3_HOST_COALESCING;
2032
2033
wdenkc6097192002-11-03 00:24:07 +00002034/******************************************************************************/
2035/* Memory arbiter registers. */
2036/******************************************************************************/
2037
2038typedef struct {
2039 T3_32BIT_REGISTER Mode;
2040#define T3_MEM_ARBITER_MODE_RESET BIT_0
2041#define T3_MEM_ARBITER_MODE_ENABLE BIT_1
2042
2043 T3_32BIT_REGISTER Status;
2044
2045 T3_32BIT_REGISTER ArbTrapAddrLow;
2046 T3_32BIT_REGISTER ArbTrapAddrHigh;
2047
2048 /* Unused space. */
2049 LM_UINT8 Unused[1008];
2050} T3_MEM_ARBITER, *PT3_MEM_ARBITER;
2051
2052
wdenkc6097192002-11-03 00:24:07 +00002053/******************************************************************************/
2054/* Buffer manager control register. */
2055/******************************************************************************/
2056
2057typedef struct {
2058 T3_32BIT_REGISTER Mode;
2059 #define BUFMGR_MODE_RESET BIT_0
2060 #define BUFMGR_MODE_ENABLE BIT_1
2061 #define BUFMGR_MODE_ATTN_ENABLE BIT_2
2062 #define BUFMGR_MODE_BM_TEST BIT_3
2063 #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4
2064
2065 T3_32BIT_REGISTER Status;
2066 #define BUFMGR_STATUS_ERROR BIT_2
2067 #define BUFMGR_STATUS_MBUF_LOW BIT_4
2068
2069 T3_32BIT_REGISTER MbufPoolAddr;
2070 T3_32BIT_REGISTER MbufPoolSize;
2071 T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
2072 T3_32BIT_REGISTER MbufMacRxLowWaterMark;
2073 T3_32BIT_REGISTER MbufHighWaterMark;
2074
2075 T3_32BIT_REGISTER RxCpuMbufAllocReq;
2076 #define BUFMGR_MBUF_ALLOC_BIT BIT_31
2077 T3_32BIT_REGISTER RxCpuMbufAllocResp;
2078 T3_32BIT_REGISTER TxCpuMbufAllocReq;
2079 T3_32BIT_REGISTER TxCpuMbufAllocResp;
2080
2081 T3_32BIT_REGISTER DmaDescPoolAddr;
2082 T3_32BIT_REGISTER DmaDescPoolSize;
2083 T3_32BIT_REGISTER DmaLowWaterMark;
2084 T3_32BIT_REGISTER DmaHighWaterMark;
2085
2086 T3_32BIT_REGISTER RxCpuDmaAllocReq;
2087 T3_32BIT_REGISTER RxCpuDmaAllocResp;
2088 T3_32BIT_REGISTER TxCpuDmaAllocReq;
2089 T3_32BIT_REGISTER TxCpuDmaAllocResp;
2090
2091 T3_32BIT_REGISTER Hwdiag[3];
2092
2093 /* Unused space. */
2094 LM_UINT8 Unused[936];
2095} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
2096
2097
wdenkc6097192002-11-03 00:24:07 +00002098/******************************************************************************/
2099/* Read DMA control registers. */
2100/******************************************************************************/
2101
2102typedef struct {
2103 T3_32BIT_REGISTER Mode;
2104 #define DMA_READ_MODE_RESET BIT_0
2105 #define DMA_READ_MODE_ENABLE BIT_1
2106 #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
2107 #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
2108 #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
2109 #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
2110 #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
2111 #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
2112 #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
2113 #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9
2114 #define DMA_READ_MODE_SPLIT_ENABLE BIT_11
2115 #define DMA_READ_MODE_SPLIT_RESET BIT_12
2116
2117 T3_32BIT_REGISTER Status;
2118 #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2
2119 #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3
2120 #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4
2121 #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5
2122 #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6
2123 #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7
2124 #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8
2125 #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9
2126
2127 /* Unused space. */
2128 LM_UINT8 Unused[1016];
2129} T3_DMA_READ, *PT3_DMA_READ;
2130
2131typedef union T3_CPU
2132{
2133 struct
2134 {
2135 T3_32BIT_REGISTER mode;
2136 #define CPU_MODE_HALT BIT_10
2137 #define CPU_MODE_RESET BIT_0
2138 T3_32BIT_REGISTER state;
2139 T3_32BIT_REGISTER EventMask;
2140 T3_32BIT_REGISTER reserved1[4];
2141 T3_32BIT_REGISTER PC;
2142 T3_32BIT_REGISTER Instruction;
2143 T3_32BIT_REGISTER SpadUnderflow;
2144 T3_32BIT_REGISTER WatchdogClear;
2145 T3_32BIT_REGISTER WatchdogVector;
2146 T3_32BIT_REGISTER WatchdogSavedPC;
2147 T3_32BIT_REGISTER HardwareBp;
2148 T3_32BIT_REGISTER reserved2[3];
2149 T3_32BIT_REGISTER WatchdogSavedState;
2150 T3_32BIT_REGISTER LastBrchAddr;
2151 T3_32BIT_REGISTER SpadUnderflowSet;
2152 T3_32BIT_REGISTER reserved3[(0x200-0x50)/4];
2153 T3_32BIT_REGISTER Regs[32];
2154 T3_32BIT_REGISTER reserved4[(0x400-0x280)/4];
2155 }reg;
2156}T3_CPU, *PT3_CPU;
2157
2158/******************************************************************************/
2159/* Write DMA control registers. */
2160/******************************************************************************/
2161
2162typedef struct {
2163 T3_32BIT_REGISTER Mode;
2164 #define DMA_WRITE_MODE_RESET BIT_0
2165 #define DMA_WRITE_MODE_ENABLE BIT_1
2166 #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2
2167 #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3
2168 #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4
2169 #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5
2170 #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6
2171 #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7
2172 #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8
2173 #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9
2174
2175 T3_32BIT_REGISTER Status;
2176 #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2
2177 #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3
2178 #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4
2179 #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5
2180 #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6
2181 #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7
2182 #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8
2183 #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9
2184
2185 /* Unused space. */
2186 LM_UINT8 Unused[1016];
2187} T3_DMA_WRITE, *PT3_DMA_WRITE;
2188
2189
wdenkc6097192002-11-03 00:24:07 +00002190/******************************************************************************/
2191/* Mailbox registers. */
2192/******************************************************************************/
2193
2194typedef struct {
2195 /* Interrupt mailbox registers. */
2196 T3_64BIT_REGISTER Interrupt[4];
2197
2198 /* General mailbox registers. */
2199 T3_64BIT_REGISTER General[8];
2200
2201 /* Reload statistics mailbox. */
2202 T3_64BIT_REGISTER ReloadStat;
2203
2204 /* Receive BD ring producer index registers. */
2205 T3_64BIT_REGISTER RcvStdProdIdx;
2206 T3_64BIT_REGISTER RcvJumboProdIdx;
2207 T3_64BIT_REGISTER RcvMiniProdIdx;
2208
2209 /* Receive return ring consumer index registers. */
2210 T3_64BIT_REGISTER RcvRetConIdx[16];
2211
2212 /* Send BD ring host producer index registers. */
2213 T3_64BIT_REGISTER SendHostProdIdx[16];
2214
2215 /* Send BD ring nic producer index registers. */
2216 T3_64BIT_REGISTER SendNicProdIdx[16];
2217}T3_MAILBOX, *PT3_MAILBOX;
2218
2219typedef struct {
2220 T3_MAILBOX Mailbox;
2221
2222 /* Priority mailbox registers. */
2223 T3_32BIT_REGISTER HighPriorityEventVector;
2224 T3_32BIT_REGISTER HighPriorityEventMask;
2225 T3_32BIT_REGISTER LowPriorityEventVector;
2226 T3_32BIT_REGISTER LowPriorityEventMask;
2227
2228 /* Unused space. */
2229 LM_UINT8 Unused[496];
2230} T3_GRC_MAILBOX, *PT3_GRC_MAILBOX;
2231
2232
2233/******************************************************************************/
2234/* Flow through queues. */
2235/******************************************************************************/
2236
2237typedef struct {
2238 T3_32BIT_REGISTER Reset;
2239
2240 LM_UINT8 Unused[12];
2241
2242 T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
2243 T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
2244 T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
2245 T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
2246
2247 T3_32BIT_REGISTER DmaHighReadFtqCtrl;
2248 T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
2249 T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
2250 T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
2251
2252 T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
2253 T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
2254 T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
2255 T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
2256
2257 T3_32BIT_REGISTER SendBdCompFtqCtrl;
2258 T3_32BIT_REGISTER SendBdCompFtqFullCnt;
2259 T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
2260 T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
2261
2262 T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
2263 T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
2264 T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
2265 T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
2266
2267 T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
2268 T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
2269 T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
2270 T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
2271
2272 T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
2273 T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
2274 T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
2275 T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
2276
2277 T3_32BIT_REGISTER SwType1FtqCtrl;
2278 T3_32BIT_REGISTER SwType1FtqFullCnt;
2279 T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
2280 T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
2281
2282 T3_32BIT_REGISTER SendDataCompFtqCtrl;
2283 T3_32BIT_REGISTER SendDataCompFtqFullCnt;
2284 T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
2285 T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
2286
2287 T3_32BIT_REGISTER HostCoalesceFtqCtrl;
2288 T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
2289 T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
2290 T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
2291
2292 T3_32BIT_REGISTER MacTxFtqCtrl;
2293 T3_32BIT_REGISTER MacTxFtqFullCnt;
2294 T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
2295 T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
2296
2297 T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
2298 T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
2299 T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
2300 T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
2301
2302 T3_32BIT_REGISTER RcvBdCompFtqCtrl;
2303 T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
2304 T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
2305 T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
2306
2307 T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
2308 T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
2309 T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
2310 T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
2311
2312 T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
2313 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
2314 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
2315 T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
2316
2317 T3_32BIT_REGISTER RcvDataCompFtqCtrl;
2318 T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
2319 T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
2320 T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
2321
2322 T3_32BIT_REGISTER SwType2FtqCtrl;
2323 T3_32BIT_REGISTER SwType2FtqFullCnt;
2324 T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
2325 T3_32BIT_REGISTER SwType2FtqFifoWritePeek;
2326
2327 /* Unused space. */
2328 LM_UINT8 Unused2[736];
2329} T3_FTQ, *PT3_FTQ;
2330
2331
wdenkc6097192002-11-03 00:24:07 +00002332/******************************************************************************/
2333/* Message signaled interrupt registers. */
2334/******************************************************************************/
2335
2336typedef struct {
2337 T3_32BIT_REGISTER Mode;
2338#define MSI_MODE_RESET BIT_0
2339#define MSI_MODE_ENABLE BIT_1
2340 T3_32BIT_REGISTER Status;
2341
2342 T3_32BIT_REGISTER MsiFifoAccess;
2343
2344 /* Unused space. */
2345 LM_UINT8 Unused[1012];
2346} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
2347
2348
wdenkc6097192002-11-03 00:24:07 +00002349/******************************************************************************/
2350/* DMA Completion registes. */
2351/******************************************************************************/
2352
2353typedef struct {
2354 T3_32BIT_REGISTER Mode;
2355 #define DMA_COMP_MODE_RESET BIT_0
2356 #define DMA_COMP_MODE_ENABLE BIT_1
2357
2358 /* Unused space. */
2359 LM_UINT8 Unused[1020];
2360} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
2361
2362
wdenkc6097192002-11-03 00:24:07 +00002363/******************************************************************************/
2364/* GRC registers. */
2365/******************************************************************************/
2366
2367typedef struct {
2368 /* Mode control register. */
2369 T3_32BIT_REGISTER Mode;
2370 #define GRC_MODE_UPDATE_ON_COALESCING BIT_0
2371 #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1
2372 #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2
2373 #define GRC_MODE_BYTE_SWAP_DATA BIT_4
2374 #define GRC_MODE_WORD_SWAP_DATA BIT_5
2375 #define GRC_MODE_SPLIT_HEADER_MODE BIT_8
2376 #define GRC_MODE_NO_FRAME_CRACKING BIT_9
2377 #define GRC_MODE_INCLUDE_CRC BIT_10
2378 #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11
2379 #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13
2380 #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14
2381 #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15
2382 #define GRC_MODE_HOST_STACK_UP BIT_16
2383 #define GRC_MODE_HOST_SEND_BDS BIT_17
2384 #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20
2385 #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23
2386 #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24
2387 #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25
2388 #define GRC_MODE_INT_ON_MAC_ATTN BIT_26
2389 #define GRC_MODE_INT_ON_DMA_ATTN BIT_27
2390 #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28
2391 #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29
2392 #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30
2393
2394 /* Misc configuration register. */
2395 T3_32BIT_REGISTER MiscCfg;
2396 #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0
2397 #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe
2398 #define GRC_MISC_BD_ID_MASK 0x0001e000
2399 #define GRC_MISC_BD_ID_5700 0x0001e000
2400 #define GRC_MISC_BD_ID_5701 0x00000000
2401 #define GRC_MISC_BD_ID_5703 0x00000000
2402 #define GRC_MISC_BD_ID_5703S 0x00002000
2403 #define GRC_MISC_BD_ID_5702FE 0x00004000
2404 #define GRC_MISC_BD_ID_5704 0x00000000
2405 #define GRC_MISC_BD_ID_5704CIOBE 0x00004000
2406
2407 /* Miscellaneous local control register. */
2408 T3_32BIT_REGISTER LocalCtrl;
2409 #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0
2410 #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1
2411 #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2
2412 #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3
2413 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8
2414 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9
2415 #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10
2416 #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11
2417 #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12
2418 #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13
2419 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14
2420 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15
2421 #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16
2422 #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17
2423 #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21
2424 #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22
2425
2426 #define GRC_MISC_MEMSIZE_256K 0
2427 #define GRC_MISC_MEMSIZE_512K (1 << 18)
2428 #define GRC_MISC_MEMSIZE_1024K (2 << 18)
2429 #define GRC_MISC_MEMSIZE_2048K (3 << 18)
2430 #define GRC_MISC_MEMSIZE_4096K (4 << 18)
2431 #define GRC_MISC_MEMSIZE_8192K (5 << 18)
2432 #define GRC_MISC_MEMSIZE_16M (6 << 18)
2433 #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24
2434
2435
2436 T3_32BIT_REGISTER Timer;
2437
2438 T3_32BIT_REGISTER RxCpuEvent;
2439 T3_32BIT_REGISTER RxTimerRef;
2440 T3_32BIT_REGISTER RxCpuSemaphore;
2441 T3_32BIT_REGISTER RemoteRxCpuAttn;
2442
2443 T3_32BIT_REGISTER TxCpuEvent;
2444 T3_32BIT_REGISTER TxTimerRef;
2445 T3_32BIT_REGISTER TxCpuSemaphore;
2446 T3_32BIT_REGISTER RemoteTxCpuAttn;
2447
2448 T3_64BIT_REGISTER MemoryPowerUp;
2449
2450 T3_32BIT_REGISTER EepromAddr;
2451 #define SEEPROM_ADDR_WRITE 0
2452 #define SEEPROM_ADDR_READ (1 << 31)
2453 #define SEEPROM_ADDR_RW_MASK 0x80000000
2454 #define SEEPROM_ADDR_COMPLETE (1 << 30)
2455 #define SEEPROM_ADDR_FSM_RESET (1 << 29)
2456 #define SEEPROM_ADDR_DEV_ID(x) (x << 26)
2457 #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
2458 #define SEEPROM_ADDR_START (1 << 25)
2459 #define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
2460 #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc)
2461 #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
2462
2463 #define SEEPROM_CLOCK_PERIOD 60
2464 #define SEEPROM_CHIP_SIZE (64 * 1024)
2465
2466 T3_32BIT_REGISTER EepromData;
2467 T3_32BIT_REGISTER EepromCtrl;
2468
2469 T3_32BIT_REGISTER MdiCtrl;
2470 T3_32BIT_REGISTER SepromDelay;
2471
2472 /* Unused space. */
2473 LM_UINT8 Unused[948];
2474} T3_GRC, *PT3_GRC;
2475
2476
2477/******************************************************************************/
2478/* NVRAM control registers. */
2479/******************************************************************************/
2480
2481typedef struct
2482{
2483 T3_32BIT_REGISTER Cmd;
2484 #define NVRAM_CMD_RESET BIT_0
2485 #define NVRAM_CMD_DONE BIT_3
2486 #define NVRAM_CMD_DO_IT BIT_4
2487 #define NVRAM_CMD_WR BIT_5
2488 #define NVRAM_CMD_RD BIT_NONE
2489 #define NVRAM_CMD_ERASE BIT_6
2490 #define NVRAM_CMD_FIRST BIT_7
2491 #define NVRAM_CMD_LAST BIT_8
2492
2493 T3_32BIT_REGISTER Status;
2494 T3_32BIT_REGISTER WriteData;
2495
2496 T3_32BIT_REGISTER Addr;
2497 #define NVRAM_ADDRESS_MASK 0xffffff
2498
2499 T3_32BIT_REGISTER ReadData;
2500
2501 /* Flash config 1 register. */
2502 T3_32BIT_REGISTER Config1;
2503 #define FLASH_INTERFACE_ENABLE BIT_0
2504 #define FLASH_SSRAM_BUFFERRED_MODE BIT_1
2505 #define FLASH_PASS_THRU_MODE BIT_2
2506 #define FLASH_BIT_BANG_MODE BIT_3
2507 #define FLASH_COMPAT_BYPASS BIT_31
2508
2509 /* Buffered flash (Atmel: AT45DB011B) specific information */
2510 #define BUFFERED_FLASH_PAGE_POS 9
2511 #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
2512 #define BUFFERED_FLASH_PAGE_SIZE 264
2513 #define BUFFERED_FLASH_PHY_PAGE_SIZE 512
2514
2515 T3_32BIT_REGISTER Config2;
2516 T3_32BIT_REGISTER Config3;
2517 T3_32BIT_REGISTER SwArb;
2518 #define SW_ARB_REQ_SET0 BIT_0
2519 #define SW_ARB_REQ_SET1 BIT_1
2520 #define SW_ARB_REQ_SET2 BIT_2
2521 #define SW_ARB_REQ_SET3 BIT_3
2522 #define SW_ARB_REQ_CLR0 BIT_4
2523 #define SW_ARB_REQ_CLR1 BIT_5
2524 #define SW_ARB_REQ_CLR2 BIT_6
2525 #define SW_ARB_REQ_CLR3 BIT_7
2526 #define SW_ARB_GNT0 BIT_8
2527 #define SW_ARB_GNT1 BIT_9
2528 #define SW_ARB_GNT2 BIT_10
2529 #define SW_ARB_GNT3 BIT_11
2530 #define SW_ARB_REQ0 BIT_12
2531 #define SW_ARB_REQ1 BIT_13
2532 #define SW_ARB_REQ2 BIT_14
2533 #define SW_ARB_REQ3 BIT_15
2534
2535 /* Unused space. */
2536 LM_UINT8 Unused[988];
2537} T3_NVRAM, *PT3_NVRAM;
2538
2539
2540/******************************************************************************/
2541/* NIC's internal memory. */
2542/******************************************************************************/
2543
2544typedef struct {
2545 /* Page zero for the internal CPUs. */
2546 LM_UINT8 PageZero[0x100]; /* 0x0000 */
2547
2548 /* Send RCBs. */
2549 T3_RCB SendRcb[16]; /* 0x0100 */
2550
2551 /* Receive Return RCBs. */
2552 T3_RCB RcvRetRcb[16]; /* 0x0200 */
2553
2554 /* Statistics block. */
2555 T3_STATS_BLOCK StatsBlk; /* 0x0300 */
2556
2557 /* Status block. */
2558 T3_STATUS_BLOCK StatusBlk; /* 0x0b00 */
2559
2560 /* Reserved for software. */
2561 LM_UINT8 Reserved[1200]; /* 0x0b50 */
2562
2563 /* Unmapped region. */
2564 LM_UINT8 Unmapped[4096]; /* 0x1000 */
2565
2566 /* DMA descriptors. */
2567 LM_UINT8 DmaDesc[8192]; /* 0x2000 */
2568
2569 /* Buffer descriptors. */
2570 LM_UINT8 BufferDesc[16384]; /* 0x4000 */
2571} T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
2572
2573
wdenkc6097192002-11-03 00:24:07 +00002574/******************************************************************************/
2575/* Memory layout. */
2576/******************************************************************************/
2577
2578typedef struct {
2579 /* PCI configuration registers. */
2580 T3_PCI_CONFIGURATION PciCfg;
2581
2582 /* Unused. */
2583 LM_UINT8 Unused1[0x100]; /* 0x0100 */
2584
2585 /* Mailbox . */
2586 T3_MAILBOX Mailbox; /* 0x0200 */
2587
2588 /* MAC control registers. */
2589 T3_MAC_CONTROL MacCtrl; /* 0x0400 */
2590
2591 /* Send data initiator control registers. */
2592 T3_SEND_DATA_INITIATOR SndDataIn; /* 0x0c00 */
2593
2594 /* Send data completion Control registers. */
2595 T3_SEND_DATA_COMPLETION SndDataComp; /* 0x1000 */
2596
2597 /* Send BD ring selector. */
2598 T3_SEND_BD_SELECTOR SndBdSel; /* 0x1400 */
2599
2600 /* Send BD initiator control registers. */
2601 T3_SEND_BD_INITIATOR SndBdIn; /* 0x1800 */
2602
2603 /* Send BD completion control registers. */
2604 T3_SEND_BD_COMPLETION SndBdComp; /* 0x1c00 */
2605
2606 /* Receive list placement control registers. */
2607 T3_RCV_LIST_PLACEMENT RcvListPlmt; /* 0x2000 */
2608
2609 /* Receive Data and Receive BD Initiator Control. */
2610 T3_RCV_DATA_BD_INITIATOR RcvDataBdIn; /* 0x2400 */
2611
2612 /* Receive Data Completion Control */
2613 T3_RCV_DATA_COMPLETION RcvDataComp; /* 0x2800 */
2614
2615 /* Receive BD Initiator Control Registers. */
2616 T3_RCV_BD_INITIATOR RcvBdIn; /* 0x2c00 */
2617
2618 /* Receive BD Completion Control Registers. */
2619 T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */
2620
2621 /* Receive list selector control registers. */
2622 T3_RCV_LIST_SELECTOR RcvListSel; /* 0x3400 */
2623
2624 /* Mbuf cluster free registers. */
2625 T3_MBUF_CLUSTER_FREE MbufClusterFree; /* 0x3800 */
2626
2627 /* Host coalescing control registers. */
2628 T3_HOST_COALESCING HostCoalesce; /* 0x3c00 */
2629
2630 /* Memory arbiter control registers. */
2631 T3_MEM_ARBITER MemArbiter; /* 0x4000 */
2632
2633 /* Buffer manger control registers. */
2634 T3_BUFFER_MANAGER BufMgr; /* 0x4400 */
2635
2636 /* Read DMA control registers. */
2637 T3_DMA_READ DmaRead; /* 0x4800 */
2638
2639 /* Write DMA control registers. */
2640 T3_DMA_WRITE DmaWrite; /* 0x4c00 */
2641
2642 T3_CPU rxCpu; /* 0x5000 */
2643 T3_CPU txCpu; /* 0x5400 */
2644
2645 /* Mailboxes. */
2646 T3_GRC_MAILBOX GrcMailbox; /* 0x5800 */
2647
2648 /* Flow Through queues. */
2649 T3_FTQ Ftq; /* 0x5c00 */
2650
2651 /* Message signaled interrupt registes. */
2652 T3_MSG_SIGNALED_INT Msi; /* 0x6000 */
2653
2654 /* DMA completion registers. */
2655 T3_DMA_COMPLETION DmaComp; /* 0x6400 */
2656
2657 /* GRC registers. */
2658 T3_GRC Grc; /* 0x6800 */
2659
2660 /* Unused space. */
2661 LM_UINT8 Unused2[1024]; /* 0x6c00 */
2662
2663 /* NVRAM registers. */
2664 T3_NVRAM Nvram; /* 0x7000 */
2665
2666 /* Unused space. */
2667 LM_UINT8 Unused3[3072]; /* 0x7400 */
2668
2669 /* The 32k memory window into the NIC's */
2670 /* internal memory. The memory window is */
2671 /* controlled by the Memory Window Base */
2672 /* Address register. This register is located */
2673 /* in the PCI configuration space. */
2674 union { /* 0x8000 */
wdenk8bde7f72003-06-27 21:31:46 +00002675 T3_FIRST_32K_SRAM First32k;
wdenkc6097192002-11-03 00:24:07 +00002676
wdenk8bde7f72003-06-27 21:31:46 +00002677 /* Use the memory window base address register to determine the */
2678 /* MBUF segment. */
2679 LM_UINT32 Mbuf[32768/4];
2680 LM_UINT32 MemBlock32K[32768/4];
wdenkc6097192002-11-03 00:24:07 +00002681 } uIntMem;
2682} T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
2683
2684
2685/******************************************************************************/
2686/* Adapter info. */
2687/******************************************************************************/
2688
2689typedef struct
2690{
2691 LM_UINT16 Svid;
2692 LM_UINT16 Ssid;
2693 LM_UINT32 PhyId;
2694 LM_UINT32 Serdes; /* 0 = copper PHY, 1 = Serdes */
2695} LM_ADAPTER_INFO, *PLM_ADAPTER_INFO;
2696
2697
2698/******************************************************************************/
2699/* Packet queues. */
2700/******************************************************************************/
2701
2702DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
2703DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
2704
2705
wdenkc6097192002-11-03 00:24:07 +00002706/******************************************************************************/
2707/* Tx counters. */
2708/******************************************************************************/
2709
2710typedef struct {
2711 LM_COUNTER TxPacketGoodCnt;
2712 LM_COUNTER TxBytesGoodCnt;
2713 LM_COUNTER TxPacketAbortedCnt;
2714 LM_COUNTER NoSendBdLeftCnt;
2715 LM_COUNTER NoMapRegisterLeftCnt;
2716 LM_COUNTER TooManyFragmentsCnt;
2717 LM_COUNTER NoTxPacketDescCnt;
2718} LM_TX_COUNTERS, *PLM_TX_COUNTERS;
2719
2720
wdenkc6097192002-11-03 00:24:07 +00002721/******************************************************************************/
2722/* Rx counters. */
2723/******************************************************************************/
2724
2725typedef struct {
2726 LM_COUNTER RxPacketGoodCnt;
2727 LM_COUNTER RxBytesGoodCnt;
2728 LM_COUNTER RxPacketErrCnt;
2729 LM_COUNTER RxErrCrcCnt;
2730 LM_COUNTER RxErrCollCnt;
2731 LM_COUNTER RxErrLinkLostCnt;
2732 LM_COUNTER RxErrPhyDecodeCnt;
2733 LM_COUNTER RxErrOddNibbleCnt;
2734 LM_COUNTER RxErrMacAbortCnt;
2735 LM_COUNTER RxErrShortPacketCnt;
2736 LM_COUNTER RxErrNoResourceCnt;
2737 LM_COUNTER RxErrLargePacketCnt;
2738} LM_RX_COUNTERS, *PLM_RX_COUNTERS;
2739
2740
wdenkc6097192002-11-03 00:24:07 +00002741/******************************************************************************/
2742/* Receive producer rings. */
2743/******************************************************************************/
2744
2745typedef enum {
2746 T3_UNKNOWN_RCV_PROD_RING = 0,
2747 T3_STD_RCV_PROD_RING = 1,
2748 T3_MINI_RCV_PROD_RING = 2,
2749 T3_JUMBO_RCV_PROD_RING = 3
2750} T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
2751
2752
wdenkc6097192002-11-03 00:24:07 +00002753/******************************************************************************/
2754/* Packet descriptor. */
2755/******************************************************************************/
2756
2757#define LM_PACKET_SIGNATURE_TX 0x6861766b
2758#define LM_PACKET_SIGNATURE_RX 0x6b766168
2759
2760typedef struct _LM_PACKET {
2761 /* Set in LM. */
2762 LM_STATUS PacketStatus;
2763
2764 /* Set in LM for Rx, in UM for Tx. */
2765 LM_UINT32 PacketSize;
2766
2767 LM_UINT16 Flags;
2768
2769 LM_UINT16 VlanTag;
2770
2771 union {
wdenk8bde7f72003-06-27 21:31:46 +00002772 /* Send info. */
2773 struct {
2774 /* Set up by UM. */
2775 LM_UINT32 FragCount;
wdenkc6097192002-11-03 00:24:07 +00002776
wdenk8bde7f72003-06-27 21:31:46 +00002777 } Tx;
wdenkc6097192002-11-03 00:24:07 +00002778
wdenk8bde7f72003-06-27 21:31:46 +00002779 /* Receive info. */
2780 struct {
2781 /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
2782 T3_RCV_PROD_RING RcvProdRing;
wdenkc6097192002-11-03 00:24:07 +00002783
wdenk8bde7f72003-06-27 21:31:46 +00002784 /* Receive buffer size */
2785 LM_UINT32 RxBufferSize;
wdenkc6097192002-11-03 00:24:07 +00002786
wdenk8bde7f72003-06-27 21:31:46 +00002787 /* Checksum information. */
2788 LM_UINT16 IpChecksum;
2789 LM_UINT16 TcpUdpChecksum;
wdenkc6097192002-11-03 00:24:07 +00002790
wdenk8bde7f72003-06-27 21:31:46 +00002791 } Rx;
wdenkc6097192002-11-03 00:24:07 +00002792 } u;
2793} LM_PACKET;
2794
2795
wdenkc6097192002-11-03 00:24:07 +00002796/******************************************************************************/
2797/* Tigon3 device block. */
2798/******************************************************************************/
2799
2800typedef struct _LM_DEVICE_BLOCK {
2801 int index; /* Device ID */
2802 /* Memory view. */
2803 PT3_STD_MEM_MAP pMemView;
2804
2805 /* Base address of the block of memory in which the LM_PACKET descriptors */
2806 /* are allocated from. */
2807 PLM_VOID pPacketDescBase;
2808
2809 LM_UINT32 MiscHostCtrl;
2810 LM_UINT32 GrcLocalCtrl;
2811 LM_UINT32 DmaReadWriteCtrl;
2812 LM_UINT32 PciState;
2813
2814 /* Rx info */
2815 LM_UINT32 RxStdDescCnt;
2816 LM_UINT32 RxStdQueuedCnt;
2817 LM_UINT32 RxStdProdIdx;
2818
2819 PT3_RCV_BD pRxStdBdVirt;
2820 LM_PHYSICAL_ADDRESS RxStdBdPhy;
2821
2822 LM_UINT32 RxPacketDescCnt;
2823 LM_RX_PACKET_Q RxPacketFreeQ;
2824 LM_RX_PACKET_Q RxPacketReceivedQ;
2825
2826 /* Receive info. */
2827 PT3_RCV_BD pRcvRetBdVirt;
2828 LM_PHYSICAL_ADDRESS RcvRetBdPhy;
2829 LM_UINT32 RcvRetConIdx;
2830
2831#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
2832 LM_UINT32 RxJumboDescCnt;
2833 LM_UINT32 RxJumboBufferSize;
2834 LM_UINT32 RxJumboQueuedCnt;
2835
2836 LM_UINT32 RxJumboProdIdx;
2837
2838 PT3_RCV_BD pRxJumboBdVirt;
2839 LM_PHYSICAL_ADDRESS RxJumboBdPhy;
2840#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
2841
2842 /* These values are used by the upper module to inform the protocol */
2843 /* of the maximum transmit/receive packet size. */
2844 LM_UINT32 TxMtu; /* Does not include CRC. */
2845 LM_UINT32 RxMtu; /* Does not include CRC. */
2846
2847 /* We need to shadow the EMAC, Rx, Tx mode registers. With B0 silicon, */
2848 /* we may have problems reading any MAC registers in 10mb mode. */
2849 LM_UINT32 MacMode;
2850 LM_UINT32 RxMode;
2851 LM_UINT32 TxMode;
2852
2853 /* MiMode register. */
2854 LM_UINT32 MiMode;
2855
2856 /* Host coalesce mode register. */
2857 LM_UINT32 CoalesceMode;
2858
2859 /* Send info. */
2860 LM_UINT32 TxPacketDescCnt;
2861
2862 /* Tx info. */
2863 LM_TX_PACKET_Q TxPacketFreeQ;
2864 LM_TX_PACKET_Q TxPacketActiveQ;
2865 LM_TX_PACKET_Q TxPacketXmittedQ;
2866
2867 /* Pointers to SendBd. */
2868 PT3_SND_BD pSendBdVirt;
2869 LM_PHYSICAL_ADDRESS SendBdPhy; /* Only valid for Host based Send BD. */
2870
2871 /* Send producer and consumer indices. */
2872 LM_UINT32 SendProdIdx;
2873 LM_UINT32 SendConIdx;
2874
2875 /* Number of BD left. */
2876 atomic_t SendBdLeft;
2877
2878 T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
2879
2880 /* Counters. */
2881 LM_RX_COUNTERS RxCounters;
2882 LM_TX_COUNTERS TxCounters;
2883
2884 /* Host coalescing parameters. */
2885 LM_UINT32 RxCoalescingTicks;
2886 LM_UINT32 TxCoalescingTicks;
2887 LM_UINT32 RxMaxCoalescedFrames;
2888 LM_UINT32 TxMaxCoalescedFrames;
2889 LM_UINT32 StatsCoalescingTicks;
2890 LM_UINT32 RxCoalescingTicksDuringInt;
2891 LM_UINT32 TxCoalescingTicksDuringInt;
2892 LM_UINT32 RxMaxCoalescedFramesDuringInt;
2893 LM_UINT32 TxMaxCoalescedFramesDuringInt;
2894
2895 /* DMA water marks. */
2896 LM_UINT32 DmaMbufLowMark;
2897 LM_UINT32 RxMacMbufLowMark;
2898 LM_UINT32 MbufHighMark;
2899
2900 /* Status block. */
2901 PT3_STATUS_BLOCK pStatusBlkVirt;
2902 LM_PHYSICAL_ADDRESS StatusBlkPhy;
2903
2904 /* Statistics block. */
2905 PT3_STATS_BLOCK pStatsBlkVirt;
2906 LM_PHYSICAL_ADDRESS StatsBlkPhy;
2907
2908 /* Current receive mask. */
2909 LM_UINT32 ReceiveMask;
2910
2911 /* Task offload capabilities. */
2912 LM_TASK_OFFLOAD TaskOffloadCap;
2913
2914 /* Task offload selected. */
2915 LM_TASK_OFFLOAD TaskToOffload;
2916
2917 /* Wake up capability. */
2918 LM_WAKE_UP_MODE WakeUpModeCap;
2919
2920 /* Wake up capability. */
2921 LM_WAKE_UP_MODE WakeUpMode;
2922
2923 /* Flow control. */
2924 LM_FLOW_CONTROL FlowControlCap;
2925 LM_FLOW_CONTROL FlowControl;
2926
2927 /* Enable or disable PCI MWI. */
2928 LM_UINT32 EnableMWI;
2929
2930 /* Enable 5701 tagged status mode. */
2931 LM_UINT32 UseTaggedStatus;
2932
2933 /* NIC will not compute the pseudo header checksum. The driver or OS */
2934 /* must seed the checksum field with the pseudo checksum. */
2935 LM_UINT32 NoTxPseudoHdrChksum;
2936
2937 /* The receive checksum in the BD does not include the pseudo checksum. */
2938 /* The OS or the driver must calculate the pseudo checksum and add it to */
2939 /* the checksum in the BD. */
2940 LM_UINT32 NoRxPseudoHdrChksum;
2941
2942 /* Current node address. */
2943 LM_UINT8 NodeAddress[8];
2944
2945 /* The adapter's node address. */
2946 LM_UINT8 PermanentNodeAddress[8];
2947
2948 /* Adapter info. */
2949 LM_UINT16 BusNum;
2950 LM_UINT8 DevNum;
2951 LM_UINT8 FunctNum;
2952 LM_UINT16 PciVendorId;
2953 LM_UINT16 PciDeviceId;
2954 LM_UINT32 BondId;
2955 LM_UINT8 Irq;
2956 LM_UINT8 IntPin;
2957 LM_UINT8 CacheLineSize;
2958 LM_UINT8 PciRevId;
2959#if PCIX_TARGET_WORKAROUND
2960 LM_UINT32 EnablePciXFix;
2961#endif
2962 LM_UINT32 UndiFix; /* new, jimmy */
2963 LM_UINT32 PciCommandStatusWords;
2964 LM_UINT32 ChipRevId;
2965 LM_UINT16 SubsystemVendorId;
2966 LM_UINT16 SubsystemId;
2967#if 0 /* Jimmy, deleted in new driver */
2968 LM_UINT32 MemBaseLow;
2969 LM_UINT32 MemBaseHigh;
2970 LM_UINT32 MemBaseSize;
2971#endif
2972 PLM_UINT8 pMappedMemBase;
2973
2974 /* Saved PCI configuration registers for restoring after a reset. */
2975 LM_UINT32 SavedCacheLineReg;
2976
2977 /* Phy info. */
2978 LM_UINT32 PhyAddr;
2979 LM_UINT32 PhyId;
2980
2981 /* Requested phy settings. */
2982 LM_REQUESTED_MEDIA_TYPE RequestedMediaType;
2983
2984 /* Disable auto-negotiation. */
2985 LM_UINT32 DisableAutoNeg;
2986
2987 /* Ways for the MAC to get link change interrupt. */
2988 LM_UINT32 PhyIntMode;
2989 #define T3_PHY_INT_MODE_AUTO 0
2990 #define T3_PHY_INT_MODE_MI_INTERRUPT 1
2991 #define T3_PHY_INT_MODE_LINK_READY 2
2992 #define T3_PHY_INT_MODE_AUTO_POLLING 3
2993
2994 /* Ways to determine link change status. */
2995 LM_UINT32 LinkChngMode;
2996 #define T3_LINK_CHNG_MODE_AUTO 0
2997 #define T3_LINK_CHNG_MODE_USE_STATUS_REG 1
2998 #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK 2
2999
3000
3001 /* LED mode. */
3002 LM_UINT32 LedMode;
3003
3004 #define LED_MODE_AUTO 0
3005
3006 /* 5700/01 LED mode. */
3007 #define LED_MODE_THREE_LINK 1
3008 #define LED_MODE_LINK10 2
3009
3010 /* 5703/02/04 LED mode. */
3011 #define LED_MODE_OPEN_DRAIN 1
3012 #define LED_MODE_OUTPUT 2
3013
3014 /* WOL Speed */
3015 LM_UINT32 WolSpeed;
3016 #define WOL_SPEED_10MB 1
3017 #define WOL_SPEED_100MB 2
3018
3019 /* Reset the PHY on initialization. */
3020 LM_UINT32 ResetPhyOnInit;
3021
3022 LM_UINT32 RestoreOnWakeUp;
3023 LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType;
3024 LM_UINT32 WakeUpDisableAutoNeg;
3025
3026 /* Current phy settings. */
3027 LM_MEDIA_TYPE MediaType;
3028 LM_LINE_SPEED LineSpeed;
3029 LM_LINE_SPEED OldLineSpeed;
3030 LM_DUPLEX_MODE DuplexMode;
3031 LM_STATUS LinkStatus;
3032 LM_UINT32 advertising; /* Jimmy, new! */
3033 LM_UINT32 advertising1000; /* Jimmy, new! */
3034
3035 /* Multicast address list. */
3036 LM_UINT32 McEntryCount;
3037 LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];
3038
3039 /* Use NIC or Host based send BD. */
3040 LM_UINT32 NicSendBd;
3041
3042 /* Athlon fix. */
3043 LM_UINT32 DelayPciGrant;
3044
3045 /* Enable OneDmaAtOnce */
3046 LM_UINT32 OneDmaAtOnce;
3047
3048 /* Split Mode flags, Jimmy new */
3049 LM_UINT32 SplitModeEnable;
3050 LM_UINT32 SplitModeMaxReq;
3051
3052 /* Init flag. */
3053 LM_BOOL InitDone;
3054
3055 /* Shutdown flag. Set by the upper module. */
3056 LM_BOOL ShuttingDown;
3057
3058 /* Flag to determine whether to call LM_QueueRxPackets or not in */
3059 /* LM_ResetAdapter routine. */
3060 LM_BOOL QueueRxPackets;
3061
3062 LM_UINT32 MbufBase;
3063 LM_UINT32 MbufSize;
3064
3065 /* TRUE if we have a SERDES PHY. */
3066 LM_UINT32 EnableTbi;
3067
3068 /* Ethernet@WireSpeed. */
3069 LM_UINT32 EnableWireSpeed;
3070
3071 LM_UINT32 EepromWp;
3072
3073#if INCLUDE_TBI_SUPPORT
3074 /* Autoneg state info. */
3075 AN_STATE_INFO AnInfo;
3076 LM_UINT32 PollTbiLink;
3077 LM_UINT32 IgnoreTbiLinkChange;
3078#endif
3079 char PartNo[24];
3080 char BootCodeVer[16];
3081 char BusSpeedStr[24]; /* Jimmy, new! */
3082 LM_UINT32 PhyCrcCount;
3083} LM_DEVICE_BLOCK;
3084
3085
3086#define T3_REG_CPU_VIEW 0xc0000000
3087
3088#define T3_BLOCK_DMA_RD (1 << 0)
3089#define T3_BLOCK_DMA_COMP (1 << 1)
3090#define T3_BLOCK_RX_BD_INITIATOR (1 << 2)
3091#define T3_BLOCK_RX_BD_COMP (1 << 3)
3092#define T3_BLOCK_DMA_WR (1 << 4)
3093#define T3_BLOCK_MSI_HANDLER (1 << 5)
3094#define T3_BLOCK_RX_LIST_PLMT (1 << 6)
3095#define T3_BLOCK_RX_LIST_SELECTOR (1 << 7)
3096#define T3_BLOCK_RX_DATA_INITIATOR (1 << 8)
3097#define T3_BLOCK_RX_DATA_COMP (1 << 9)
3098#define T3_BLOCK_HOST_COALESING (1 << 10)
3099#define T3_BLOCK_MAC_RX_ENGINE (1 << 11)
3100#define T3_BLOCK_MBUF_CLUSTER_FREE (1 << 12)
3101#define T3_BLOCK_SEND_BD_INITIATOR (1 << 13)
3102#define T3_BLOCK_SEND_BD_COMP (1 << 14)
3103#define T3_BLOCK_SEND_BD_SELECTOR (1 << 15)
3104#define T3_BLOCK_SEND_DATA_INITIATOR (1 << 16)
3105#define T3_BLOCK_SEND_DATA_COMP (1 << 17)
3106#define T3_BLOCK_MAC_TX_ENGINE (1 << 18)
3107#define T3_BLOCK_MEM_ARBITOR (1 << 19)
3108#define T3_BLOCK_MBUF_MANAGER (1 << 20)
3109#define T3_BLOCK_MAC_GLOBAL (1 << 21)
3110
3111#define LM_ENABLE 1
3112#define LM_DISABLE 2
3113
3114#define RX_CPU_EVT_SW0 0
3115#define RX_CPU_EVT_SW1 1
3116#define RX_CPU_EVT_RLP 2
3117#define RX_CPU_EVT_SW3 3
3118#define RX_CPU_EVT_RLS 4
3119#define RX_CPU_EVT_SW4 5
3120#define RX_CPU_EVT_RX_BD_COMP 6
3121#define RX_CPU_EVT_SW5 7
3122#define RX_CPU_EVT_RDI 8
3123#define RX_CPU_EVT_DMA_WR 9
3124#define RX_CPU_EVT_DMA_RD 10
3125#define RX_CPU_EVT_SWQ 11
3126#define RX_CPU_EVT_SW6 12
3127#define RX_CPU_EVT_RDC 13
3128#define RX_CPU_EVT_SW7 14
3129#define RX_CPU_EVT_HOST_COALES 15
3130#define RX_CPU_EVT_SW8 16
3131#define RX_CPU_EVT_HIGH_DMA_WR 17
3132#define RX_CPU_EVT_HIGH_DMA_RD 18
3133#define RX_CPU_EVT_SW9 19
3134#define RX_CPU_EVT_DMA_ATTN 20
3135#define RX_CPU_EVT_LOW_P_MBOX 21
3136#define RX_CPU_EVT_HIGH_P_MBOX 22
3137#define RX_CPU_EVT_SW10 23
3138#define RX_CPU_EVT_TX_CPU_ATTN 24
3139#define RX_CPU_EVT_MAC_ATTN 25
3140#define RX_CPU_EVT_RX_CPU_ATTN 26
3141#define RX_CPU_EVT_FLOW_ATTN 27
3142#define RX_CPU_EVT_SW11 28
3143#define RX_CPU_EVT_TIMER 29
3144#define RX_CPU_EVT_SW12 30
3145#define RX_CPU_EVT_SW13 31
3146
3147/* RX-CPU event */
3148#define RX_CPU_EVENT_SW_EVENT0 (1 << RX_CPU_EVT_SW0)
3149#define RX_CPU_EVENT_SW_EVENT1 (1 << RX_CPU_EVT_SW1)
3150#define RX_CPU_EVENT_RLP (1 << RX_CPU_EVT_RLP)
3151#define RX_CPU_EVENT_SW_EVENT3 (1 << RX_CPU_EVT_SW3)
3152#define RX_CPU_EVENT_RLS (1 << RX_CPU_EVT_RLS)
3153#define RX_CPU_EVENT_SW_EVENT4 (1 << RX_CPU_EVT_SW4)
3154#define RX_CPU_EVENT_RX_BD_COMP (1 << RX_CPU_EVT_RX_BD_COMP)
3155#define RX_CPU_EVENT_SW_EVENT5 (1 << RX_CPU_EVT_SW5)
3156#define RX_CPU_EVENT_RDI (1 << RX_CPU_EVT_RDI)
3157#define RX_CPU_EVENT_DMA_WR (1 << RX_CPU_EVT_DMA_WR)
3158#define RX_CPU_EVENT_DMA_RD (1 << RX_CPU_EVT_DMA_RD)
3159#define RX_CPU_EVENT_SWQ (1 << RX_CPU_EVT_SWQ)
3160#define RX_CPU_EVENT_SW_EVENT6 (1 << RX_CPU_EVT_SW6)
3161#define RX_CPU_EVENT_RDC (1 << RX_CPU_EVT_RDC)
3162#define RX_CPU_EVENT_SW_EVENT7 (1 << RX_CPU_EVT_SW7)
3163#define RX_CPU_EVENT_HOST_COALES (1 << RX_CPU_EVT_HOST_COALES)
3164#define RX_CPU_EVENT_SW_EVENT8 (1 << RX_CPU_EVT_SW8)
3165#define RX_CPU_EVENT_HIGH_DMA_WR (1 << RX_CPU_EVT_HIGH_DMA_WR)
3166#define RX_CPU_EVENT_HIGH_DMA_RD (1 << RX_CPU_EVT_HIGH_DMA_RD)
3167#define RX_CPU_EVENT_SW_EVENT9 (1 << RX_CPU_EVT_SW9)
3168#define RX_CPU_EVENT_DMA_ATTN (1 << RX_CPU_EVT_DMA_ATTN)
3169#define RX_CPU_EVENT_LOW_P_MBOX (1 << RX_CPU_EVT_LOW_P_MBOX)
3170#define RX_CPU_EVENT_HIGH_P_MBOX (1 << RX_CPU_EVT_HIGH_P_MBOX)
3171#define RX_CPU_EVENT_SW_EVENT10 (1 << RX_CPU_EVT_SW10)
3172#define RX_CPU_EVENT_TX_CPU_ATTN (1 << RX_CPU_EVT_TX_CPU_ATTN)
3173#define RX_CPU_EVENT_MAC_ATTN (1 << RX_CPU_EVT_MAC_ATTN)
3174#define RX_CPU_EVENT_RX_CPU_ATTN (1 << RX_CPU_EVT_RX_CPU_ATTN)
3175#define RX_CPU_EVENT_FLOW_ATTN (1 << RX_CPU_EVT_FLOW_ATTN)
3176#define RX_CPU_EVENT_SW_EVENT11 (1 << RX_CPU_EVT_SW11)
3177#define RX_CPU_EVENT_TIMER (1 << RX_CPU_EVT_TIMER)
3178#define RX_CPU_EVENT_SW_EVENT12 (1 << RX_CPU_EVT_SW12)
3179#define RX_CPU_EVENT_SW_EVENT13 (1 << RX_CPU_EVT_SW13)
3180
3181#define RX_CPU_MASK (RX_CPU_EVENT_SW_EVENT0 | \
3182 RX_CPU_EVENT_RLP | \
3183 RX_CPU_EVENT_RDI | \
3184 RX_CPU_EVENT_RDC)
3185
3186#define TX_CPU_EVT_SW0 0
3187#define TX_CPU_EVT_SW1 1
3188#define TX_CPU_EVT_SW2 2
3189#define TX_CPU_EVT_SW3 3
3190#define TX_CPU_EVT_TX_MAC 4
3191#define TX_CPU_EVT_SW4 5
3192#define TX_CPU_EVT_SBDC 6
3193#define TX_CPU_EVT_SW5 7
3194#define TX_CPU_EVT_SDI 8
3195#define TX_CPU_EVT_DMA_WR 9
3196#define TX_CPU_EVT_DMA_RD 10
3197#define TX_CPU_EVT_SWQ 11
3198#define TX_CPU_EVT_SW6 12
3199#define TX_CPU_EVT_SDC 13
3200#define TX_CPU_EVT_SW7 14
3201#define TX_CPU_EVT_HOST_COALES 15
3202#define TX_CPU_EVT_SW8 16
3203#define TX_CPU_EVT_HIGH_DMA_WR 17
3204#define TX_CPU_EVT_HIGH_DMA_RD 18
3205#define TX_CPU_EVT_SW9 19
3206#define TX_CPU_EVT_DMA_ATTN 20
3207#define TX_CPU_EVT_LOW_P_MBOX 21
3208#define TX_CPU_EVT_HIGH_P_MBOX 22
3209#define TX_CPU_EVT_SW10 23
3210#define TX_CPU_EVT_RX_CPU_ATTN 24
3211#define TX_CPU_EVT_MAC_ATTN 25
3212#define TX_CPU_EVT_TX_CPU_ATTN 26
3213#define TX_CPU_EVT_FLOW_ATTN 27
3214#define TX_CPU_EVT_SW11 28
3215#define TX_CPU_EVT_TIMER 29
3216#define TX_CPU_EVT_SW12 30
3217#define TX_CPU_EVT_SW13 31
3218
3219
3220/* TX-CPU event */
3221#define TX_CPU_EVENT_SW_EVENT0 (1 << TX_CPU_EVT_SW0)
3222#define TX_CPU_EVENT_SW_EVENT1 (1 << TX_CPU_EVT_SW1)
3223#define TX_CPU_EVENT_SW_EVENT2 (1 << TX_CPU_EVT_SW2)
3224#define TX_CPU_EVENT_SW_EVENT3 (1 << TX_CPU_EVT_SW3)
3225#define TX_CPU_EVENT_TX_MAC (1 << TX_CPU_EVT_TX_MAC)
3226#define TX_CPU_EVENT_SW_EVENT4 (1 << TX_CPU_EVT_SW4)
3227#define TX_CPU_EVENT_SBDC (1 << TX_CPU_EVT_SBDC)
3228#define TX_CPU_EVENT_SW_EVENT5 (1 << TX_CPU_EVT_SW5)
3229#define TX_CPU_EVENT_SDI (1 << TX_CPU_EVT_SDI)
3230#define TX_CPU_EVENT_DMA_WR (1 << TX_CPU_EVT_DMA_WR)
3231#define TX_CPU_EVENT_DMA_RD (1 << TX_CPU_EVT_DMA_RD)
3232#define TX_CPU_EVENT_SWQ (1 << TX_CPU_EVT_SWQ)
3233#define TX_CPU_EVENT_SW_EVENT6 (1 << TX_CPU_EVT_SW6)
3234#define TX_CPU_EVENT_SDC (1 << TX_CPU_EVT_SDC)
3235#define TX_CPU_EVENT_SW_EVENT7 (1 << TX_CPU_EVT_SW7)
3236#define TX_CPU_EVENT_HOST_COALES (1 << TX_CPU_EVT_HOST_COALES)
3237#define TX_CPU_EVENT_SW_EVENT8 (1 << TX_CPU_EVT_SW8)
3238#define TX_CPU_EVENT_HIGH_DMA_WR (1 << TX_CPU_EVT_HIGH_DMA_WR)
3239#define TX_CPU_EVENT_HIGH_DMA_RD (1 << TX_CPU_EVT_HIGH_DMA_RD)
3240#define TX_CPU_EVENT_SW_EVENT9 (1 << TX_CPU_EVT_SW9)
3241#define TX_CPU_EVENT_DMA_ATTN (1 << TX_CPU_EVT_DMA_ATTN)
3242#define TX_CPU_EVENT_LOW_P_MBOX (1 << TX_CPU_EVT_LOW_P_MBOX)
3243#define TX_CPU_EVENT_HIGH_P_MBOX (1 << TX_CPU_EVT_HIGH_P_MBOX)
3244#define TX_CPU_EVENT_SW_EVENT10 (1 << TX_CPU_EVT_SW10)
3245#define TX_CPU_EVENT_RX_CPU_ATTN (1 << TX_CPU_EVT_RX_CPU_ATTN)
3246#define TX_CPU_EVENT_MAC_ATTN (1 << TX_CPU_EVT_MAC_ATTN)
3247#define TX_CPU_EVENT_TX_CPU_ATTN (1 << TX_CPU_EVT_TX_CPU_ATTN)
3248#define TX_CPU_EVENT_FLOW_ATTN (1 << TX_CPU_EVT_FLOW_ATTN)
3249#define TX_CPU_EVENT_SW_EVENT11 (1 << TX_CPU_EVT_SW11)
3250#define TX_CPU_EVENT_TIMER (1 << TX_CPU_EVT_TIMER)
3251#define TX_CPU_EVENT_SW_EVENT12 (1 << TX_CPU_EVT_SW12)
3252#define TX_CPU_EVENT_SW_EVENT13 (1 << TX_CPU_EVT_SW13)
3253
3254
3255#define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \
3256 TX_CPU_EVENT_SDI | \
3257 TX_CPU_EVENT_SDC)
3258
3259
3260#define T3_FTQ_TYPE1_UNDERFLOW_BIT (1 << 29)
3261#define T3_FTQ_TYPE1_PASS_BIT (1 << 30)
3262#define T3_FTQ_TYPE1_SKIP_BIT (1 << 31)
3263
3264#define T3_FTQ_TYPE2_UNDERFLOW_BIT (1 << 13)
3265#define T3_FTQ_TYPE2_PASS_BIT (1 << 14)
3266#define T3_FTQ_TYPE2_SKIP_BIT (1 << 15)
3267
3268#define T3_QID_DMA_READ 1
3269#define T3_QID_DMA_HIGH_PRI_READ 2
3270#define T3_QID_DMA_COMP_DX 3
3271#define T3_QID_SEND_BD_COMP 4
3272#define T3_QID_SEND_DATA_INITIATOR 5
3273#define T3_QID_DMA_WRITE 6
3274#define T3_QID_DMA_HIGH_PRI_WRITE 7
3275#define T3_QID_SW_TYPE_1 8
3276#define T3_QID_SEND_DATA_COMP 9
3277#define T3_QID_HOST_COALESCING 10
3278#define T3_QID_MAC_TX 11
3279#define T3_QID_MBUF_CLUSTER_FREE 12
3280#define T3_QID_RX_BD_COMP 13
3281#define T3_QID_RX_LIST_PLM 14
3282#define T3_QID_RX_DATA_BD_INITIATOR 15
3283#define T3_QID_RX_DATA_COMP 16
3284#define T3_QID_SW_TYPE2 17
3285
3286LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
wdenk8bde7f72003-06-27 21:31:46 +00003287 PT3_FWIMG_INFO pFwImg,
3288 LM_UINT32 LoadCpu,
3289 LM_UINT32 StartCpu);
wdenkc6097192002-11-03 00:24:07 +00003290
3291/******************************************************************************/
3292/* NIC register read/write macros. */
3293/******************************************************************************/
3294
3295#if 0 /* Jimmy */
3296/* MAC register access. */
3297LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
3298LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
3299 LM_UINT32 Value32);
3300
3301/* MAC memory access. */
3302LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
3303LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
3304 LM_UINT32 Value32);
3305
3306#if PCIX_TARGET_WORKAROUND
3307
3308/* use memory-mapped accesses for mailboxes and reads, UNDI accesses
3309 for writes to all other registers */
3310#define REG_RD(pDevice, OffsetName) \
3311 readl(&((pDevice)->pMemView->OffsetName))
3312
3313#define REG_WR(pDevice, OffsetName, Value32) \
3314 (((OFFSETOF(T3_STD_MEM_MAP, OffsetName) >=0x200 ) && \
3315 (OFFSETOF(T3_STD_MEM_MAP, OffsetName) <0x400)) || \
3316 ((pDevice)->EnablePciXFix == FALSE)) ? \
3317 (void) writel(Value32, &((pDevice)->pMemView->OffsetName)) : \
3318 LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32)
3319
3320#define MB_REG_RD(pDevice, OffsetName) \
3321 readl(&((pDevice)->pMemView->OffsetName))
3322
3323#define MB_REG_WR(pDevice, OffsetName, Value32) \
3324 writel(Value32, &((pDevice)->pMemView->OffsetName))
3325
3326#define REG_RD_OFFSET(pDevice, Offset) \
3327 readl(&((LM_UINT8 *) (pDevice)->pMemView + Offset))
3328
3329#define REG_WR_OFFSET(pDevice, Offset, Value32) \
3330 (((Offset >=0x200 ) && (Offset < 0x400)) || \
3331 ((pDevice)->EnablePciXFix == FALSE)) ? \
3332 (void) writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) : \
3333 LM_RegWrInd(pDevice, Offset, Value32)
3334
3335#define MEM_RD(pDevice, AddrName) \
3336 LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName))
3337#define MEM_WR(pDevice, AddrName, Value32) \
3338 LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32)
3339
3340#define MEM_RD_OFFSET(pDevice, Offset) \
3341 LM_MemRdInd(pDevice, Offset)
3342#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
3343 LM_MemWrInd(pDevice, Offset, Value32)
3344
3345#else /* normal target access path below */
3346
3347/* Register access. */
3348#define REG_RD(pDevice, OffsetName) \
3349 readl(&((pDevice)->pMemView->OffsetName))
3350#define REG_WR(pDevice, OffsetName, Value32) \
3351 writel(Value32, &((pDevice)->pMemView->OffsetName))
3352
3353#define REG_RD_OFFSET(pDevice, Offset) \
3354 readl(((LM_UINT8 *) (pDevice)->pMemView + Offset))
3355#define REG_WR_OFFSET(pDevice, Offset, Value32) \
3356 writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset))
3357
3358
3359/* There could be problem access the memory window directly. For now, */
3360/* we have to go through the PCI configuration register. */
3361#define MEM_RD(pDevice, AddrName) \
3362 LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName))
3363#define MEM_WR(pDevice, AddrName, Value32) \
3364 LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32)
3365
3366#define MEM_RD_OFFSET(pDevice, Offset) \
3367 LM_MemRdInd(pDevice, Offset)
3368#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
3369 LM_MemWrInd(pDevice, Offset, Value32)
3370
3371#endif /* PCIX_TARGET_WORKAROUND */
3372
3373#endif /* Jimmy, merging */
3374
3375 /* Jimmy...rest of file is new stuff! */
3376/******************************************************************************/
3377/* NIC register read/write macros. */
3378/******************************************************************************/
3379
3380/* MAC register access. */
3381LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
3382LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
3383 LM_UINT32 Value32);
3384
3385/* MAC memory access. */
3386LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
3387LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
3388 LM_UINT32 Value32);
3389
3390#define MB_REG_WR(pDevice, OffsetName, Value32) \
3391 ((pDevice)->UndiFix) ? \
wdenk8bde7f72003-06-27 21:31:46 +00003392 LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \
3393 Value32) : \
3394 (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName))
wdenkc6097192002-11-03 00:24:07 +00003395
3396#define MB_REG_RD(pDevice, OffsetName) \
3397 (((pDevice)->UndiFix) ? \
wdenk8bde7f72003-06-27 21:31:46 +00003398 LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \
3399 __raw_readl(&((pDevice)->pMemView->OffsetName)))
wdenkc6097192002-11-03 00:24:07 +00003400
3401#define REG_RD(pDevice, OffsetName) \
3402 (((pDevice)->UndiFix) ? \
wdenk8bde7f72003-06-27 21:31:46 +00003403 LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \
3404 __raw_readl(&((pDevice)->pMemView->OffsetName)))
wdenkc6097192002-11-03 00:24:07 +00003405
3406#if PCIX_TARGET_WORKAROUND
3407
3408#define REG_WR(pDevice, OffsetName, Value32) \
3409 ((pDevice)->EnablePciXFix == FALSE) ? \
3410 (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) : \
3411 LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32)
3412
3413#else
3414
3415#define REG_WR(pDevice, OffsetName, Value32) \
3416 __raw_writel(Value32, &((pDevice)->pMemView->OffsetName))
3417
3418#endif
3419
3420#define MEM_RD(pDevice, AddrName) \
3421 LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName))
3422#define MEM_WR(pDevice, AddrName, Value32) \
3423 LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32)
3424
3425#define MEM_RD_OFFSET(pDevice, Offset) \
3426 LM_MemRdInd(pDevice, Offset)
3427#define MEM_WR_OFFSET(pDevice, Offset, Value32) \
3428 LM_MemWrInd(pDevice, Offset, Value32)
3429
3430#endif /* TIGON3_H */