Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | menu "MIPS architecture" |
| 2 | depends on MIPS |
| 3 | |
| 4 | config SYS_ARCH |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 5 | default "mips" |
| 6 | |
Daniel Schwierzeck | b9863b6 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 7 | config SYS_CPU |
| 8 | default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2 |
| 9 | default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2 |
| 10 | |
Masahiro Yamada | 7bfd5ee | 2014-10-24 01:30:46 +0900 | [diff] [blame] | 11 | config USE_PRIVATE_LIBGCC |
| 12 | default y |
| 13 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 14 | choice |
| 15 | prompt "Target select" |
| 16 | |
| 17 | config TARGET_QEMU_MIPS |
| 18 | bool "Support qemu-mips" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 19 | select SUPPORTS_BIG_ENDIAN |
| 20 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 21 | select SUPPORTS_CPU_MIPS32_R1 |
| 22 | select SUPPORTS_CPU_MIPS32_R2 |
Daniel Schwierzeck | aa45f75 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 23 | select SUPPORTS_CPU_MIPS64_R1 |
| 24 | select SUPPORTS_CPU_MIPS64_R2 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 25 | |
| 26 | config TARGET_MALTA |
| 27 | bool "Support malta" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 28 | select SUPPORTS_BIG_ENDIAN |
| 29 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 30 | select SUPPORTS_CPU_MIPS32_R1 |
| 31 | select SUPPORTS_CPU_MIPS32_R2 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 32 | |
| 33 | config TARGET_VCT |
| 34 | bool "Support vct" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 35 | select SUPPORTS_BIG_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 36 | select SUPPORTS_CPU_MIPS32_R1 |
| 37 | select SUPPORTS_CPU_MIPS32_R2 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 38 | |
| 39 | config TARGET_DBAU1X00 |
| 40 | bool "Support dbau1x00" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 41 | select SUPPORTS_BIG_ENDIAN |
| 42 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 43 | select SUPPORTS_CPU_MIPS32_R1 |
| 44 | select SUPPORTS_CPU_MIPS32_R2 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 45 | |
| 46 | config TARGET_PB1X00 |
| 47 | bool "Support pb1x00" |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 48 | select SUPPORTS_LITTLE_ENDIAN |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 49 | select SUPPORTS_CPU_MIPS32_R1 |
| 50 | select SUPPORTS_CPU_MIPS32_R2 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 51 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 52 | |
| 53 | endchoice |
| 54 | |
| 55 | source "board/dbau1x00/Kconfig" |
| 56 | source "board/imgtec/malta/Kconfig" |
| 57 | source "board/micronas/vct/Kconfig" |
| 58 | source "board/pb1x00/Kconfig" |
| 59 | source "board/qemu-mips/Kconfig" |
| 60 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 61 | if MIPS |
| 62 | |
| 63 | choice |
| 64 | prompt "Endianness selection" |
| 65 | help |
| 66 | Some MIPS boards can be configured for either little or big endian |
| 67 | byte order. These modes require different U-Boot images. In general there |
| 68 | is one preferred byteorder for a particular system but some systems are |
| 69 | just as commonly used in the one or the other endianness. |
| 70 | |
| 71 | config SYS_BIG_ENDIAN |
| 72 | bool "Big endian" |
| 73 | depends on SUPPORTS_BIG_ENDIAN |
| 74 | |
| 75 | config SYS_LITTLE_ENDIAN |
| 76 | bool "Little endian" |
| 77 | depends on SUPPORTS_LITTLE_ENDIAN |
| 78 | |
| 79 | endchoice |
| 80 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 81 | choice |
| 82 | prompt "CPU selection" |
| 83 | default CPU_MIPS32_R2 |
| 84 | |
| 85 | config CPU_MIPS32_R1 |
| 86 | bool "MIPS32 Release 1" |
| 87 | depends on SUPPORTS_CPU_MIPS32_R1 |
| 88 | select 32BIT |
| 89 | help |
| 90 | Choose this option to build an U-Boot for release 1 or later of the |
| 91 | MIPS32 architecture. |
| 92 | |
| 93 | config CPU_MIPS32_R2 |
| 94 | bool "MIPS32 Release 2" |
| 95 | depends on SUPPORTS_CPU_MIPS32_R2 |
| 96 | select 32BIT |
| 97 | help |
| 98 | Choose this option to build an U-Boot for release 2 or later of the |
| 99 | MIPS32 architecture. |
| 100 | |
| 101 | config CPU_MIPS64_R1 |
| 102 | bool "MIPS64 Release 1" |
| 103 | depends on SUPPORTS_CPU_MIPS64_R1 |
| 104 | select 64BIT |
| 105 | help |
| 106 | Choose this option to build a kernel for release 1 or later of the |
| 107 | MIPS64 architecture. |
| 108 | |
| 109 | config CPU_MIPS64_R2 |
| 110 | bool "MIPS64 Release 2" |
| 111 | depends on SUPPORTS_CPU_MIPS64_R2 |
| 112 | select 64BIT |
| 113 | help |
| 114 | Choose this option to build a kernel for release 2 or later of the |
| 115 | MIPS64 architecture. |
| 116 | |
| 117 | endchoice |
| 118 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 119 | config SUPPORTS_BIG_ENDIAN |
| 120 | bool |
| 121 | |
| 122 | config SUPPORTS_LITTLE_ENDIAN |
| 123 | bool |
| 124 | |
Daniel Schwierzeck | 02611cb | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 125 | config SUPPORTS_CPU_MIPS32_R1 |
| 126 | bool |
| 127 | |
| 128 | config SUPPORTS_CPU_MIPS32_R2 |
| 129 | bool |
| 130 | |
| 131 | config SUPPORTS_CPU_MIPS64_R1 |
| 132 | bool |
| 133 | |
| 134 | config SUPPORTS_CPU_MIPS64_R2 |
| 135 | bool |
| 136 | |
| 137 | config 32BIT |
| 138 | bool |
| 139 | |
| 140 | config 64BIT |
| 141 | bool |
| 142 | |
Daniel Schwierzeck | 0e1dc34 | 2014-10-26 14:14:07 +0100 | [diff] [blame] | 143 | endif |
| 144 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 145 | endmenu |