| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2008-2013 Tensilica Inc. |
| 3 | * Copyright (C) 2016 Cadence Design Systems Inc. |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef _XTENSA_ADDRSPACE_H |
| 9 | #define _XTENSA_ADDRSPACE_H |
| 10 | |
| 11 | #include <asm/arch/core.h> |
| 12 | |
| 13 | /* |
| 14 | * MMU Memory Map |
| 15 | * |
| 16 | * noMMU and v3 MMU have identity mapped address space on reset. |
| 17 | * V2 MMU: |
| 18 | * IO (uncached) f0000000..ffffffff -> f000000 |
| 19 | * IO (cached) e0000000..efffffff -> f000000 |
| 20 | * MEM (uncached) d8000000..dfffffff -> 0000000 |
| 21 | * MEM (cached) d0000000..d7ffffff -> 0000000 |
| 22 | * |
| 23 | * The actual location of memory and IO is the board property. |
| 24 | */ |
| 25 | |
| 26 | #define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) |
| 27 | #define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x)) |
| 28 | #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ |
| 29 | XCHAL_VECBASE_RESET_PADDR) |
| 30 | |
| 31 | #endif /* _XTENSA_ADDRSPACE_H */ |