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wdenk5c952cf2004-10-10 21:27:30 +00001/*
2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <config.h>
26#include <version.h>
27
28/*************************************************************************
29 * RESTART
30 ************************************************************************/
31
32 .text
33 .global _start
34
35_start:
36 /* ICACHE INIT -- only the icache line at the reset address
37 * is invalidated at reset. So the init must stay within
38 * the cache line size (8 words). If GERMS is used, we'll
39 * just be invalidating the cache a second time. If cache
40 * is not implemented initi behaves as nop.
41 */
wdenk0c1c117c2005-03-30 23:28:18 +000042 ori r4, r0, %lo(CFG_ICACHELINE_SIZE)
wdenk5c952cf2004-10-10 21:27:30 +000043 movhi r5, %hi(CFG_ICACHE_SIZE)
44 ori r5, r5, %lo(CFG_ICACHE_SIZE)
45 mov r6, r0
460: initi r6
47 add r6, r6, r4
48 bltu r6, r5, 0b
wdenk0c1c117c2005-03-30 23:28:18 +000049 br _except_end /* Skip the tramp */
50
51 /* EXCEPTION TRAMPOLINE -- the following gets copied
52 * to the exception address (below), but is otherwise at the
53 * default exception vector offset (0x0020).
54 */
55_except_start:
56 movhi et, %hi(_exception)
57 ori et, et, %lo(_exception)
58 jmp et
59_except_end:
wdenk5c952cf2004-10-10 21:27:30 +000060
61 /* INTERRUPTS -- for now, all interrupts masked and globally
62 * disabled.
63 */
64 wrctl status, r0 /* Disable interrupts */
65 wrctl ienable, r0 /* All disabled */
66
67 /* DCACHE INIT -- if dcache not implemented, initd behaves as
68 * nop.
69 */
70 movhi r4, %hi(CFG_DCACHELINE_SIZE)
71 ori r4, r4, %lo(CFG_DCACHELINE_SIZE)
72 movhi r5, %hi(CFG_DCACHE_SIZE)
73 ori r5, r5, %lo(CFG_DCACHE_SIZE)
74 mov r6, r0
751: initd 0(r6)
76 add r6, r6, r4
77 bltu r6, r5, 1b
78
79 /* RELOCATE CODE, DATA & COMMAND TABLE -- the following code
80 * assumes code, data and the command table are all
81 * contiguous. This lets us relocate everything as a single
82 * block. Make sure the linker script matches this ;-)
83 */
84 nextpc r4
85_cur: movhi r5, %hi(_cur - _start)
86 ori r5, r5, %lo(_cur - _start)
87 sub r4, r4, r5 /* r4 <- cur _start */
88 mov r8, r4
89 movhi r5, %hi(_start)
90 ori r5, r5, %lo(_start) /* r5 <- linked _start */
91 beq r4, r5, 3f
92
93 movhi r6, %hi(_edata)
94 ori r6, r6, %lo(_edata)
952: ldwio r7, 0(r4)
96 addi r4, r4, 4
97 stwio r7, 0(r5)
98 addi r5, r5, 4
99 bne r5, r6, 2b
1003:
101
102 /* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
103 * and between __bss_start and _end.
104 */
105 movhi r5, %hi(__bss_start)
106 ori r5, r5, %lo(__bss_start)
107 movhi r6, %hi(_end)
108 ori r6, r6, %lo(_end)
109 beq r5, r6, 5f
110
1114: stwio r0, 0(r5)
112 addi r5, r5, 4
113 bne r5, r6, 4b
1145:
115
116 /* GLOBAL POINTER -- the global pointer is used to reference
117 * "small data" (see -G switch). The linker script must
118 * provide the gp address.
119 */
120 movhi gp, %hi(_gp)
121 ori gp, gp, %lo(_gp)
122
123 /* JUMP TO RELOC ADDR */
124 movhi r4, %hi(_reloc)
125 ori r4, r4, %lo(_reloc)
126 jmp r4
127_reloc:
128
129 /* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
wdenk0c1c117c2005-03-30 23:28:18 +0000130 * exception address. Define CONFIG_ROM_STUBS to prevent
131 * the copy (e.g. exception in flash or in other
132 * softare/firmware component).
wdenk5c952cf2004-10-10 21:27:30 +0000133 */
134#if !defined(CONFIG_ROM_STUBS)
135 movhi r4, %hi(_except_start)
136 ori r4, r4, %lo(_except_start)
137 movhi r5, %hi(_except_end)
138 ori r5, r5, %lo(_except_end)
139 movhi r6, %hi(CFG_EXCEPTION_ADDR)
140 ori r6, r6, %lo(CFG_EXCEPTION_ADDR)
wdenk0c1c117c2005-03-30 23:28:18 +0000141 beq r4, r6, 7f /* Skip if at proper addr */
wdenk5c952cf2004-10-10 21:27:30 +0000142
1436: ldwio r7, 0(r4)
144 stwio r7, 0(r6)
145 addi r4, r4, 4
146 addi r6, r6, 4
147 bne r4, r5, 6b
wdenk0c1c117c2005-03-30 23:28:18 +00001487:
wdenk5c952cf2004-10-10 21:27:30 +0000149#endif
150
151 /* STACK INIT -- zero top two words for call back chain.
152 */
153 movhi sp, %hi(CFG_INIT_SP)
154 ori sp, sp, %lo(CFG_INIT_SP)
155 addi sp, sp, -8
156 stw r0, 0(sp)
157 stw r0, 4(sp)
158 mov fp, sp
159
160 /*
161 * Call board_init -- never returns
162 */
163 movhi r4, %hi(board_init@h)
164 ori r4, r4, %lo(board_init@h)
165 callr r4
166
167 /* NEVER RETURNS -- but branch to the _start just
168 * in case ;-)
169 */
170 br _start
171
wdenk5c952cf2004-10-10 21:27:30 +0000172
173/*
174 * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in
175 * the core. For simple delay loops, we do our best by counting
176 * instruction cycles.
177 *
178 * Instruction performance varies based on the core. For cores
179 * with icache and static/dynamic branch prediction (II/f, II/s):
180 *
181 * Normal ALU (e.g. add, cmp, etc): 1 cycle
182 * Branch (correctly predicted, taken): 2 cycles
183 * Negative offset is predicted (II/s).
184 *
185 * For cores without icache and no branch prediction (II/e):
186 *
187 * Normal ALU (e.g. add, cmp, etc): 6 cycles
188 * Branch (no prediction): 6 cycles
189 *
190 * For simplicity, if an instruction cache is implemented we
191 * assume II/f or II/s. Otherwise, we use the II/e.
192 *
193 */
194 .globl dly_clks
195
196dly_clks:
197
198#if (CFG_ICACHE_SIZE > 0)
199 subi r4, r4, 3 /* 3 clocks/loop */
200#else
201 subi r4, r4, 12 /* 12 clocks/loop */
202#endif
203 bge r4, r0, dly_clks
204 ret
205
206
207#if !defined(CONFIG_IDENT_STRING)
208#define CONFIG_IDENT_STRING ""
209#endif
210 .data
211 .globl version_string
212
213version_string:
214 .ascii U_BOOT_VERSION
215 .ascii " (", __DATE__, " - ", __TIME__, ")"
216 .ascii CONFIG_IDENT_STRING, "\0"