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wdenkfe8c2802002-11-03 00:38:21 +00001/*
wdenk10a36a92004-07-10 23:02:23 +00002 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
wdenkfe8c2802002-11-03 00:38:21 +00004 *
wdenk10a36a92004-07-10 23:02:23 +00005 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
wdenkfe8c2802002-11-03 00:38:21 +000015 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
wdenk10a36a92004-07-10 23:02:23 +000038/* Enable debug prints */
39#undef DEBUG /* General debug */
40#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
wdenkfe8c2802002-11-03 00:38:21 +000041
wdenk10a36a92004-07-10 23:02:23 +000042/*****************************************************************************
43 *
44 * These settings must match the way _your_ board is set up
45 *
46 *****************************************************************************/
wdenkfe8c2802002-11-03 00:38:21 +000047
wdenk10a36a92004-07-10 23:02:23 +000048/* What is the oscillator's (UX2) frequency in Hz? */
49#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
wdenk466b7412004-07-10 22:35:59 +000050
51/*-----------------------------------------------------------------------
wdenk10a36a92004-07-10 23:02:23 +000052 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
53 *-----------------------------------------------------------------------
54 * What should MODCK_H be? It is dependent on the oscillator
55 * frequency, MODCK[1-3], and desired CPM and core frequencies.
56 * Here are some example values (all frequencies are in MHz):
57 *
58 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
59 * ------- ---------- --- --- ---- ----- ----- -----
60 * 0x1 0x5 33 100 133 Open Close Open
61 * 0x1 0x6 33 100 166 Open Open Close
62 * 0x1 0x7 33 100 200 Open Open Open
63 *
64 * 0x2 0x2 33 133 133 Close Open Close
65 * 0x2 0x3 33 133 166 Close Open Open
66 * 0x2 0x4 33 133 200 Open Close Close
67 * 0x2 0x5 33 133 233 Open Close Open
68 * 0x2 0x6 33 133 266 Open Open Close
69 *
70 * 0x5 0x5 66 133 133 Open Close Open
71 * 0x5 0x6 66 133 166 Open Open Close
72 * 0x5 0x7 66 133 200 Open Open Open
73 * 0x6 0x0 66 133 233 Close Close Close
74 * 0x6 0x1 66 133 266 Close Close Open
75 * 0x6 0x2 66 133 300 Close Open Close
76 */
77#define CFG_SBC_MODCK_H 0x05
78
79/* Define this if you want to boot from 0x00000100. If you don't define
80 * this, you will need to program the bootloader to 0xfff00000, and
81 * get the hardware reset config words at 0xfe000000. The simplest
82 * way to do that is to program the bootloader at both addresses.
83 * It is suggested that you just let U-Boot live at 0x00000000.
84 */
85#define CFG_SBC_BOOT_LOW 1
86
87/* What should the base address of the main FLASH be and how big is
88 * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
89 * The main FLASH is whichever is connected to *CS0. U-Boot expects
90 * this to be the SIMM.
91 */
92#define CFG_FLASH0_BASE 0x40000000
93#define CFG_FLASH0_SIZE 4
94
95/* What should the base address of the secondary FLASH be and how big
96 * is it (in Mbytes)? The secondary FLASH is whichever is connected
97 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
98 * want it enabled, don't define these constants.
99 */
100#define CFG_FLASH1_BASE 0x60000000
101#define CFG_FLASH1_SIZE 2
102
103/* What should be the base address of SDRAM DIMM and how big is
104 * it (in Mbytes)?
105*/
106#define CFG_SDRAM0_BASE 0x00000000
107#define CFG_SDRAM0_SIZE 64
108
109/* What should be the base address of the LEDs and switch S0?
110 * If you don't want them enabled, don't define this.
111 */
112#define CFG_LED_BASE 0xa0000000
113
114
115/*
116 * SBC8260 with 16 MB DIMM:
117 *
118 * 0x0000 0000 Exception Vector code, 8k
119 * :
120 * 0x0000 1FFF
121 * 0x0000 2000 Free for Application Use
122 * :
123 * :
124 *
125 * :
126 * :
127 * 0x00F5 FF30 Monitor Stack (Growing downward)
128 * Monitor Stack Buffer (0x80)
129 * 0x00F5 FFB0 Board Info Data
130 * 0x00F6 0000 Malloc Arena
131 * : CFG_ENV_SECT_SIZE, 256k
132 * : CFG_MALLOC_LEN, 128k
133 * 0x00FC 0000 RAM Copy of Monitor Code
134 * : CFG_MONITOR_LEN, 256k
135 * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
wdenk466b7412004-07-10 22:35:59 +0000136 */
137
wdenk10a36a92004-07-10 23:02:23 +0000138/*
139 * SBC8260 with 64 MB DIMM:
140 *
141 * 0x0000 0000 Exception Vector code, 8k
142 * :
143 * 0x0000 1FFF
144 * 0x0000 2000 Free for Application Use
145 * :
146 * :
147 *
148 * :
149 * :
150 * 0x03F5 FF30 Monitor Stack (Growing downward)
151 * Monitor Stack Buffer (0x80)
152 * 0x03F5 FFB0 Board Info Data
153 * 0x03F6 0000 Malloc Arena
154 * : CFG_ENV_SECT_SIZE, 256k
155 * : CFG_MALLOC_LEN, 128k
156 * 0x03FC 0000 RAM Copy of Monitor Code
157 * : CFG_MONITOR_LEN, 256k
158 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
159 */
160
161
162/*
163 * select serial console configuration
164 *
165 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
166 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
167 * for SCC).
168 *
169 * if CONFIG_CONS_NONE is defined, then the serial console routines must
170 * defined elsewhere.
171 */
172#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
173#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
174#undef CONFIG_CONS_NONE /* define if console on neither */
175#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
176
177/*
178 * select ethernet configuration
179 *
180 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
181 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
182 * for FCC)
183 *
184 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
185 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
186 * from CONFIG_COMMANDS to remove support for networking.
187 */
188
189#undef CONFIG_ETHER_ON_SCC
190#define CONFIG_ETHER_ON_FCC
191#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
192
193#ifdef CONFIG_ETHER_ON_SCC
194#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
195#endif /* CONFIG_ETHER_ON_SCC */
196
197#ifdef CONFIG_ETHER_ON_FCC
198#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
199#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
200#define CONFIG_MII /* MII PHY management */
201#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
202/*
203 * Port pins used for bit-banged MII communictions (if applicable).
204 */
205#define MDIO_PORT 2 /* Port C */
206#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
207#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
208#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
209
210#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
211 else iop->pdat &= ~0x00400000
212
213#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
214 else iop->pdat &= ~0x00200000
215
216#define MIIDELAY udelay(1)
217#endif /* CONFIG_ETHER_ON_FCC */
218
219#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
220
221/*
222 * - RX clk is CLK11
223 * - TX clk is CLK12
224 */
225# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
226
227#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
228
229/*
230 * - Rx-CLK is CLK13
231 * - Tx-CLK is CLK14
232 * - Select bus for bd/buffers (see 28-13)
233 * - Enable Full Duplex in FSMR
234 */
235# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
236# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
237# define CFG_CPMFCR_RAMTYPE 0
238# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
239
240#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
241
242/*
243 * Select SPI support configuration
244 */
245#undef CONFIG_SPI /* Disable SPI driver */
246
247/*
248 * Select i2c support configuration
249 *
250 * Supported configurations are {none, software, hardware} drivers.
251 * If the software driver is chosen, there are some additional
252 * configuration items that the driver uses to drive the port pins.
253 */
254#undef CONFIG_HARD_I2C /* I2C with hardware support */
255#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
256#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
257#define CFG_I2C_SLAVE 0x7F
258
259/*
260 * Software (bit-bang) I2C driver configuration
261 */
262#ifdef CONFIG_SOFT_I2C
263#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
264#define I2C_ACTIVE (iop->pdir |= 0x00010000)
265#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
266#define I2C_READ ((iop->pdat & 0x00010000) != 0)
267#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
268 else iop->pdat &= ~0x00010000
269#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
270 else iop->pdat &= ~0x00020000
271#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
272#endif /* CONFIG_SOFT_I2C */
273
274
275/* Define this to reserve an entire FLASH sector (256 KB) for
276 * environment variables. Otherwise, the environment will be
277 * put in the same sector as U-Boot, and changing variables
278 * will erase U-Boot temporarily
279 */
280#define CFG_ENV_IN_OWN_SECT 1
281
282/* Define to allow the user to overwrite serial and ethaddr */
283#define CONFIG_ENV_OVERWRITE
284
285/* What should the console's baud rate be? */
286#define CONFIG_BAUDRATE 9600
287
288/* Ethernet MAC address
289 * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
290 * http://standards.ieee.org/regauth/oui/index.shtml
291 */
292#define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb
293
294/*
295 * Define this to set the last octet of the ethernet address from the
296 * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
297 * switch and the LEDs are backwards with respect to each other. DS7
298 * is on the board edge side of both the LED strip and the DS0-DS7
299 * switch.
300 */
301#undef CONFIG_MISC_INIT_R
302
303/* Set to a positive value to delay for running BOOTCOMMAND */
304#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
305
306/* Be selective on what keys can delay or stop the autoboot process
307 * To stop use: " "
308 */
309#undef CONFIG_AUTOBOOT_KEYED
310#ifdef CONFIG_AUTOBOOT_KEYED
311# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
312# define CONFIG_AUTOBOOT_STOP_STR " "
313# undef CONFIG_AUTOBOOT_DELAY_STR
314# define DEBUG_BOOTKEYS 0
wdenk466b7412004-07-10 22:35:59 +0000315#endif
wdenk466b7412004-07-10 22:35:59 +0000316
wdenk10a36a92004-07-10 23:02:23 +0000317/* Define this to contain any number of null terminated strings that
318 * will be part of the default enviroment compiled into the boot image.
319 *
320 * Variable Usage
321 * -------------- -------------------------------------------------------
322 * serverip server IP address
323 * ipaddr my IP address
324 * reprog Reload flash with a new copy of U-Boot
325 * zapenv Erase the environment area in flash
326 * root-on-initrd Set the bootcmd variable to allow booting of an initial
327 * ram disk.
328 * root-on-nfs Set the bootcmd variable to allow booting of a NFS
329 * mounted root filesystem.
330 * boot-hook Convenient stub to do something useful before the
331 * bootm command is executed.
332 *
333 * Example usage of root-on-initrd and root-on-nfs :
334 *
335 * Note: The lines have been wrapped to improved its readability.
336 *
337 * => printenv bootcmd
338 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100339 * nfsroot=${serverip}:${rootpath}
340 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000341 *
342 * => run root-on-initrd
343 * => printenv bootcmd
344 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100345 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000346 *
347 * => run root-on-nfs
348 * => printenv bootcmd
349 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100350 * nfsroot=${serverip}:${rootpath}
351 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000352 *
353 */
354#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkb9283e22004-07-11 21:49:42 +0000355 "serverip=192.168.123.205\0" \
wdenk10a36a92004-07-10 23:02:23 +0000356 "ipaddr=192.168.123.213\0" \
357 "reprog="\
358 "bootp;" \
359 "tftpboot 0x140000 /bdi2000/u-boot.bin;" \
360 "protect off 1:0;" \
361 "erase 1:0;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100362 "cp.b 140000 40000000 ${filesize};" \
wdenk10a36a92004-07-10 23:02:23 +0000363 "protect on 1:0\0" \
364 "zapenv="\
365 "protect off 1:1;" \
366 "erase 1:1;" \
367 "protect on 1:1\0" \
368 "root-on-initrd="\
369 "setenv bootcmd "\
370 "version;" \
371 "echo;" \
372 "bootp;" \
373 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100374 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000375 "run boot-hook;" \
376 "bootm\0" \
377 "root-on-nfs="\
378 "setenv bootcmd "\
379 "version;" \
380 "echo;" \
381 "bootp;" \
382 "setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100383 "nfsroot=${serverip}:${rootpath} " \
384 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000385 "run boot-hook;" \
386 "bootm\0" \
387 "boot-hook=echo\0"
wdenk466b7412004-07-10 22:35:59 +0000388
wdenk10a36a92004-07-10 23:02:23 +0000389/* Define a command string that is automatically executed when no character
390 * is read on the console interface withing "Boot Delay" after reset.
391 */
392#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
393#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenk466b7412004-07-10 22:35:59 +0000394
wdenk10a36a92004-07-10 23:02:23 +0000395#ifdef CONFIG_BOOT_ROOT_INITRD
396#define CONFIG_BOOTCOMMAND \
397 "version;" \
398 "echo;" \
399 "bootp;" \
400 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100401 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000402 "bootm"
403#endif /* CONFIG_BOOT_ROOT_INITRD */
404
405#ifdef CONFIG_BOOT_ROOT_NFS
406#define CONFIG_BOOTCOMMAND \
407 "version;" \
408 "echo;" \
409 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100410 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
411 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000412 "bootm"
413#endif /* CONFIG_BOOT_ROOT_NFS */
414
415/* Add support for a few extra bootp options like:
416 * - File size
417 * - DNS (up to 2 servers)
418 * - Send hostname to DHCP server
419 */
420#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
421 CONFIG_BOOTP_BOOTFILESIZE | \
422 CONFIG_BOOTP_DNS | \
423 CONFIG_BOOTP_DNS2 | \
424 CONFIG_BOOTP_SEND_HOSTNAME)
425
426/* undef this to save memory */
427#define CFG_LONGHELP
428
429/* Monitor Command Prompt */
430#define CFG_PROMPT "=> "
431
432#undef CFG_HUSH_PARSER
433#ifdef CFG_HUSH_PARSER
434#define CFG_PROMPT_HUSH_PS2 "> "
435#endif
436
437/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
438 * of an image is printed by image commands like bootm or iminfo.
439 */
440#define CONFIG_TIMESTAMP
441
442/* If this variable is defined, an environment variable named "ver"
443 * is created by U-Boot showing the U-Boot version.
444 */
445#define CONFIG_VERSION_VARIABLE
446
447/* What U-Boot subsytems do you want enabled? */
448#ifdef CONFIG_ETHER_ON_FCC
449# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
450 CFG_CMD_ASKENV | \
wdenk10a36a92004-07-10 23:02:23 +0000451 CFG_CMD_ELF | \
452 CFG_CMD_I2C | \
453 CFG_CMD_IMMAP | \
454 CFG_CMD_MII | \
455 CFG_CMD_PING | \
456 CFG_CMD_REGINFO | \
457 CFG_CMD_SDRAM )
wdenk466b7412004-07-10 22:35:59 +0000458#else
wdenk10a36a92004-07-10 23:02:23 +0000459# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
460 CFG_CMD_ASKENV | \
wdenk10a36a92004-07-10 23:02:23 +0000461 CFG_CMD_ELF | \
462 CFG_CMD_I2C | \
463 CFG_CMD_IMMAP | \
464 CFG_CMD_PING | \
465 CFG_CMD_REGINFO | \
466 CFG_CMD_SDRAM )
467#endif /* CONFIG_ETHER_ON_FCC */
wdenk466b7412004-07-10 22:35:59 +0000468
wdenk10a36a92004-07-10 23:02:23 +0000469#undef CONFIG_WATCHDOG /* disable the watchdog */
wdenk466b7412004-07-10 22:35:59 +0000470
wdenk10a36a92004-07-10 23:02:23 +0000471/* Where do the internal registers live? */
472#define CFG_IMMR 0xF0000000
wdenk466b7412004-07-10 22:35:59 +0000473
wdenk10a36a92004-07-10 23:02:23 +0000474/*****************************************************************************
475 *
476 * You should not have to modify any of the following settings
477 *
478 *****************************************************************************/
wdenk466b7412004-07-10 22:35:59 +0000479
wdenk10a36a92004-07-10 23:02:23 +0000480#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
481#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500482#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk466b7412004-07-10 22:35:59 +0000483
wdenk10a36a92004-07-10 23:02:23 +0000484/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
wdenkfe8c2802002-11-03 00:38:21 +0000485#include <cmd_confdefs.h>
486
487/*
488 * Miscellaneous configurable options
489 */
490#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000491# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000492#else
wdenk10a36a92004-07-10 23:02:23 +0000493# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000494#endif
wdenk10a36a92004-07-10 23:02:23 +0000495
496/* Print Buffer Size */
497#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
498
499#define CFG_MAXARGS 32 /* max number of command args */
500
501#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
502
503#define CFG_LOAD_ADDR 0x400000 /* default load address */
504#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
505
506#define CFG_ALT_MEMTEST /* Select full-featured memory test */
507#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
508 /* the exception vector table */
509 /* to the end of the DRAM */
510 /* less monitor and malloc area */
511#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
512#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
513 + CFG_MALLOC_LEN \
514 + CFG_ENV_SECT_SIZE \
515 + CFG_STACK_USAGE )
516
517#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
518 - CFG_MEM_END_USAGE )
519
520/* valid baudrates */
521#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
522
523/*
524 * Low Level Configuration Settings
525 * (address mappings, register initial values, etc.)
526 * You should know what you are doing if you make changes here.
527 */
528
529#define CFG_FLASH_BASE CFG_FLASH0_BASE
530#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
531#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
532#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
533
534/*-----------------------------------------------------------------------
535 * Hard Reset Configuration Words
536 */
537#if defined(CFG_SBC_BOOT_LOW)
538# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
539#else
540# define CFG_SBC_HRCW_BOOT_FLAGS (0)
541#endif /* defined(CFG_SBC_BOOT_LOW) */
542
543/* get the HRCW ISB field from CFG_IMMR */
544#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
545 ((CFG_IMMR & 0x01000000) >> 7) | \
546 ((CFG_IMMR & 0x00100000) >> 4) )
547
548#define CFG_HRCW_MASTER ( HRCW_BPS11 | \
549 HRCW_DPPC11 | \
550 CFG_SBC_HRCW_IMMR | \
551 HRCW_MMR00 | \
552 HRCW_LBPC11 | \
553 HRCW_APPC10 | \
554 HRCW_CS10PC00 | \
555 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
556 CFG_SBC_HRCW_BOOT_FLAGS )
557
558/* no slaves */
559#define CFG_HRCW_SLAVE1 0
560#define CFG_HRCW_SLAVE2 0
561#define CFG_HRCW_SLAVE3 0
562#define CFG_HRCW_SLAVE4 0
563#define CFG_HRCW_SLAVE5 0
564#define CFG_HRCW_SLAVE6 0
565#define CFG_HRCW_SLAVE7 0
566
567/*-----------------------------------------------------------------------
568 * Definitions for initial stack pointer and data area (in DPRAM)
569 */
570#define CFG_INIT_RAM_ADDR CFG_IMMR
571#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
572#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
573#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
574#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
575
576/*-----------------------------------------------------------------------
577 * Start addresses for the final memory configuration
578 * (Set up by the startup code)
579 * Please note that CFG_SDRAM_BASE _must_ start at 0
580 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
581 */
582#define CFG_MONITOR_BASE CFG_FLASH0_BASE
583
584#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
585# define CFG_RAMBOOT
586#endif
587
588#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
589#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000590
591/*
592 * For booting Linux, the board info and command line data
593 * have to be in the first 8 MB of memory, since this is
594 * the maximum mapped by the Linux kernel during initialization.
595 */
wdenk10a36a92004-07-10 23:02:23 +0000596#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000597
wdenk10a36a92004-07-10 23:02:23 +0000598/*-----------------------------------------------------------------------
599 * FLASH and environment organization
600 */
601#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
602#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
603
604#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
605#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
606
607#ifndef CFG_RAMBOOT
608# define CFG_ENV_IS_IN_FLASH 1
609
610# ifdef CFG_ENV_IN_OWN_SECT
611# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
612# define CFG_ENV_SECT_SIZE 0x40000
613# else
614# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
615# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
616# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
617# endif /* CFG_ENV_IN_OWN_SECT */
618
619#else
620# define CFG_ENV_IS_IN_NVRAM 1
621# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
622# define CFG_ENV_SIZE 0x200
623#endif /* CFG_RAMBOOT */
624
625/*-----------------------------------------------------------------------
626 * Cache Configuration
627 */
628#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
629
wdenkfe8c2802002-11-03 00:38:21 +0000630#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000631# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000632#endif
633
wdenk10a36a92004-07-10 23:02:23 +0000634/*-----------------------------------------------------------------------
635 * HIDx - Hardware Implementation-dependent Registers 2-11
636 *-----------------------------------------------------------------------
637 * HID0 also contains cache control - initially enable both caches and
638 * invalidate contents, then the final state leaves only the instruction
639 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
640 * but Soft reset does not.
641 *
642 * HID1 has only read-only information - nothing to set.
643 */
644#define CFG_HID0_INIT (HID0_ICE |\
645 HID0_DCE |\
646 HID0_ICFI |\
647 HID0_DCI |\
648 HID0_IFEM |\
649 HID0_ABE)
650
651#define CFG_HID0_FINAL (HID0_ICE |\
652 HID0_IFEM |\
653 HID0_ABE |\
654 HID0_EMCP)
655#define CFG_HID2 0
656
657/*-----------------------------------------------------------------------
658 * RMR - Reset Mode Register
659 *-----------------------------------------------------------------------
660 */
661#define CFG_RMR 0
662
663/*-----------------------------------------------------------------------
664 * BCR - Bus Configuration 4-25
665 *-----------------------------------------------------------------------
666 */
667#define CFG_BCR (BCR_ETM)
668
669/*-----------------------------------------------------------------------
670 * SIUMCR - SIU Module Configuration 4-31
671 *-----------------------------------------------------------------------
672 */
673
674#define CFG_SIUMCR (SIUMCR_DPPC11 |\
675 SIUMCR_L2CPC00 |\
676 SIUMCR_APPC10 |\
677 SIUMCR_MMR00)
678
679
680/*-----------------------------------------------------------------------
681 * SYPCR - System Protection Control 11-9
682 * SYPCR can only be written once after reset!
683 *-----------------------------------------------------------------------
684 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
685 */
686#if defined(CONFIG_WATCHDOG)
687#define CFG_SYPCR (SYPCR_SWTC |\
688 SYPCR_BMT |\
689 SYPCR_PBME |\
690 SYPCR_LBME |\
691 SYPCR_SWRI |\
692 SYPCR_SWP |\
693 SYPCR_SWE)
694#else
695#define CFG_SYPCR (SYPCR_SWTC |\
696 SYPCR_BMT |\
697 SYPCR_PBME |\
698 SYPCR_LBME |\
699 SYPCR_SWRI |\
700 SYPCR_SWP)
701#endif /* CONFIG_WATCHDOG */
702
703/*-----------------------------------------------------------------------
704 * TMCNTSC - Time Counter Status and Control 4-40
705 *-----------------------------------------------------------------------
706 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
707 * and enable Time Counter
708 */
709#define CFG_TMCNTSC (TMCNTSC_SEC |\
710 TMCNTSC_ALR |\
711 TMCNTSC_TCF |\
712 TMCNTSC_TCE)
713
714/*-----------------------------------------------------------------------
715 * PISCR - Periodic Interrupt Status and Control 4-42
716 *-----------------------------------------------------------------------
717 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
718 * Periodic timer
719 */
720#define CFG_PISCR (PISCR_PS |\
721 PISCR_PTF |\
722 PISCR_PTE)
723
724/*-----------------------------------------------------------------------
725 * SCCR - System Clock Control 9-8
726 *-----------------------------------------------------------------------
727 */
728#define CFG_SCCR 0
729
730/*-----------------------------------------------------------------------
731 * RCCR - RISC Controller Configuration 13-7
732 *-----------------------------------------------------------------------
733 */
734#define CFG_RCCR 0
735
736/*
737 * Initialize Memory Controller:
738 *
739 * Bank Bus Machine PortSz Device
740 * ---- --- ------- ------ ------
741 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) *
742 * 1 60x GPCM 32 bit FLASH (SIMM - Unused)
743 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
744 * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused)
745 * 4 Local SDRAM 32 bit SDRAM (on board - 4MB)
746 * 5 60x GPCM 8 bit EEPROM (8KB)
747 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
748 * 7 60x GPCM 8 bit LEDs, switches
749 *
750 * (*) This configuration requires the SBC8260 be configured
751 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
752 * the on board FLASH. In other words, JP24 should have
753 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
754 *
755 */
756
757/*-----------------------------------------------------------------------
758 * BR0,BR1 - Base Register
759 * Ref: Section 10.3.1 on page 10-14
760 * OR0,OR1 - Option Register
761 * Ref: Section 10.3.2 on page 10-18
762 *-----------------------------------------------------------------------
763 */
764
765/* Bank 0,1 - FLASH SIMM
766 *
767 * This expects the FLASH SIMM to be connected to *CS0
768 * It consists of 4 AM29F080B parts.
769 *
770 * Note: For the 4 MB SIMM, *CS1 is unused.
771 */
772
773/* BR0 is configured as follows:
774 *
775 * - Base address of 0x40000000
776 * - 32 bit port size
777 * - Data errors checking is disabled
778 * - Read and write access
779 * - GPCM 60x bus
780 * - Access are handled by the memory controller according to MSEL
781 * - Not used for atomic operations
782 * - No data pipelining is done
783 * - Valid
784 */
785#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
786 BRx_PS_32 |\
787 BRx_MS_GPCM_P |\
788 BRx_V)
789
790/* OR0 is configured as follows:
791 *
792 * - 4 MB
793 * - *BCTL0 is asserted upon access to the current memory bank
794 * - *CW / *WE are negated a quarter of a clock earlier
795 * - *CS is output at the same time as the address lines
796 * - Uses a clock cycle length of 5
797 * - *PSDVAL is generated internally by the memory controller
798 * unless *GTA is asserted earlier externally.
799 * - Relaxed timing is generated by the GPCM for accesses
800 * initiated to this memory region.
801 * - One idle clock is inserted between a read access from the
802 * current bank and the next access.
803 */
804#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
805 ORxG_CSNT |\
806 ORxG_ACS_DIV1 |\
807 ORxG_SCY_5_CLK |\
808 ORxG_TRLX |\
809 ORxG_EHTR)
810
811/*-----------------------------------------------------------------------
812 * BR2,BR3 - Base Register
813 * Ref: Section 10.3.1 on page 10-14
814 * OR2,OR3 - Option Register
815 * Ref: Section 10.3.2 on page 10-16
816 *-----------------------------------------------------------------------
817 */
818
819/* Bank 2,3 - SDRAM DIMM
820 *
821 * 16MB DIMM: P/N
822 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST
823 *
824 * Note: *CS3 is unused for this DIMM
825 */
826
827/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
828 *
829 * - Base address of 0x00000000
830 * - 64 bit port size (60x bus only)
831 * - Data errors checking is disabled
832 * - Read and write access
833 * - SDRAM 60x bus
834 * - Access are handled by the memory controller according to MSEL
835 * - Not used for atomic operations
836 * - No data pipelining is done
837 * - Valid
838 */
839#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
840 BRx_PS_64 |\
841 BRx_MS_SDRAM_P |\
842 BRx_V)
843
844#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
845 BRx_PS_64 |\
846 BRx_MS_SDRAM_P |\
847 BRx_V)
848
849/* With a 16 MB DIMM, the OR2 is configured as follows:
850 *
851 * - 16 MB
852 * - 2 internal banks per device
853 * - Row start address bit is A9 with PSDMR[PBI] = 0
854 * - 11 row address lines
855 * - Back-to-back page mode
856 * - Internal bank interleaving within save device enabled
857 */
858#if (CFG_SDRAM0_SIZE == 16)
859#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
860 ORxS_BPD_2 |\
861 ORxS_ROWST_PBI0_A9 |\
862 ORxS_NUMR_11)
863#endif
864
865/* With a 64 MB DIMM, the OR2 is configured as follows:
866 *
867 * - 64 MB
868 * - 4 internal banks per device
869 * - Row start address bit is A8 with PSDMR[PBI] = 0
870 * - 12 row address lines
871 * - Back-to-back page mode
872 * - Internal bank interleaving within save device enabled
873 */
874#if (CFG_SDRAM0_SIZE == 64)
875#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
876 ORxS_BPD_4 |\
877 ORxS_ROWST_PBI0_A8 |\
878 ORxS_NUMR_12)
879#endif
880
881/*-----------------------------------------------------------------------
882 * PSDMR - 60x Bus SDRAM Mode Register
883 * Ref: Section 10.3.3 on page 10-21
884 *-----------------------------------------------------------------------
885 */
886
887/* Address that the DIMM SPD memory lives at.
888 */
889#define SDRAM_SPD_ADDR 0x54
890
891#if (CFG_SDRAM0_SIZE == 16)
892/* With a 16 MB DIMM, the PSDMR is configured as follows:
893 *
894 * - Bank Based Interleaving,
895 * - Refresh Enable,
896 * - Address Multiplexing where A5 is output on A14 pin
897 * (A6 on A15, and so on),
898 * - use address pins A16-A18 as bank select,
899 * - A9 is output on SDA10 during an ACTIVATE command,
900 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
901 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
902 * is 3 clocks,
903 * - earliest timing for READ/WRITE command after ACTIVATE command is
904 * 2 clocks,
905 * - earliest timing for PRECHARGE after last data was read is 1 clock,
906 * - earliest timing for PRECHARGE after last data was written is 1 clock,
907 * - CAS Latency is 2.
908 */
909#define CFG_PSDMR (PSDMR_RFEN |\
910 PSDMR_SDAM_A14_IS_A5 |\
911 PSDMR_BSMA_A16_A18 |\
912 PSDMR_SDA10_PBI0_A9 |\
913 PSDMR_RFRC_7_CLK |\
914 PSDMR_PRETOACT_3W |\
915 PSDMR_ACTTORW_2W |\
916 PSDMR_LDOTOPRE_1C |\
917 PSDMR_WRC_1C |\
918 PSDMR_CL_2)
919#endif
920
921#if (CFG_SDRAM0_SIZE == 64)
922/* With a 64 MB DIMM, the PSDMR is configured as follows:
923 *
924 * - Bank Based Interleaving,
925 * - Refresh Enable,
926 * - Address Multiplexing where A5 is output on A14 pin
927 * (A6 on A15, and so on),
928 * - use address pins A14-A16 as bank select,
929 * - A9 is output on SDA10 during an ACTIVATE command,
930 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
931 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
932 * is 3 clocks,
933 * - earliest timing for READ/WRITE command after ACTIVATE command is
934 * 2 clocks,
935 * - earliest timing for PRECHARGE after last data was read is 1 clock,
936 * - earliest timing for PRECHARGE after last data was written is 1 clock,
937 * - CAS Latency is 2.
938 */
939#define CFG_PSDMR (PSDMR_RFEN |\
940 PSDMR_SDAM_A14_IS_A5 |\
941 PSDMR_BSMA_A14_A16 |\
942 PSDMR_SDA10_PBI0_A9 |\
943 PSDMR_RFRC_7_CLK |\
944 PSDMR_PRETOACT_3W |\
945 PSDMR_ACTTORW_2W |\
946 PSDMR_LDOTOPRE_1C |\
947 PSDMR_WRC_1C |\
948 PSDMR_CL_2)
949#endif
950
951/*
952 * Shoot for approximately 1MHz on the prescaler.
953 */
954#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
955#define CFG_MPTPR MPTPR_PTP_DIV64
956#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
957#define CFG_MPTPR MPTPR_PTP_DIV32
958#else
959#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
960#define CFG_MPTPR MPTPR_PTP_DIV32
961#endif
962#define CFG_PSRT 14
963
964
965/* Bank 4 - On board SDRAM
966 *
967 * This is not implemented yet.
968 */
969
970/*-----------------------------------------------------------------------
971 * BR6 - Base Register
972 * Ref: Section 10.3.1 on page 10-14
973 * OR6 - Option Register
974 * Ref: Section 10.3.2 on page 10-18
975 *-----------------------------------------------------------------------
976 */
977
978/* Bank 6 - On board FLASH
979 *
980 * This expects the on board FLASH SIMM to be connected to *CS6
981 * It consists of 1 AM29F016A part.
982 */
983#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
984
985/* BR6 is configured as follows:
986 *
987 * - Base address of 0x60000000
988 * - 8 bit port size
989 * - Data errors checking is disabled
990 * - Read and write access
991 * - GPCM 60x bus
992 * - Access are handled by the memory controller according to MSEL
993 * - Not used for atomic operations
994 * - No data pipelining is done
995 * - Valid
996 */
997# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
998 BRx_PS_8 |\
999 BRx_MS_GPCM_P |\
1000 BRx_V)
1001
1002/* OR6 is configured as follows:
1003 *
1004 * - 2 MB
1005 * - *BCTL0 is asserted upon access to the current memory bank
1006 * - *CW / *WE are negated a quarter of a clock earlier
1007 * - *CS is output at the same time as the address lines
1008 * - Uses a clock cycle length of 5
1009 * - *PSDVAL is generated internally by the memory controller
1010 * unless *GTA is asserted earlier externally.
1011 * - Relaxed timing is generated by the GPCM for accesses
1012 * initiated to this memory region.
1013 * - One idle clock is inserted between a read access from the
1014 * current bank and the next access.
1015 */
1016# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
1017 ORxG_CSNT |\
1018 ORxG_ACS_DIV1 |\
1019 ORxG_SCY_5_CLK |\
1020 ORxG_TRLX |\
1021 ORxG_EHTR)
1022#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
1023
1024/*-----------------------------------------------------------------------
1025 * BR7 - Base Register
1026 * Ref: Section 10.3.1 on page 10-14
1027 * OR7 - Option Register
1028 * Ref: Section 10.3.2 on page 10-18
1029 *-----------------------------------------------------------------------
1030 */
1031
1032/* Bank 7 - LEDs and switches
1033 *
1034 * LEDs are at 0x00001 (write only)
1035 * switches are at 0x00001 (read only)
1036 */
1037#ifdef CFG_LED_BASE
1038
1039/* BR7 is configured as follows:
1040 *
1041 * - Base address of 0xA0000000
1042 * - 8 bit port size
1043 * - Data errors checking is disabled
1044 * - Read and write access
1045 * - GPCM 60x bus
1046 * - Access are handled by the memory controller according to MSEL
1047 * - Not used for atomic operations
1048 * - No data pipelining is done
1049 * - Valid
1050 */
1051# define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
1052 BRx_PS_8 |\
1053 BRx_MS_GPCM_P |\
1054 BRx_V)
1055
1056/* OR7 is configured as follows:
1057 *
1058 * - 1 byte
1059 * - *BCTL0 is asserted upon access to the current memory bank
1060 * - *CW / *WE are negated a quarter of a clock earlier
1061 * - *CS is output at the same time as the address lines
1062 * - Uses a clock cycle length of 15
1063 * - *PSDVAL is generated internally by the memory controller
1064 * unless *GTA is asserted earlier externally.
1065 * - Relaxed timing is generated by the GPCM for accesses
1066 * initiated to this memory region.
1067 * - One idle clock is inserted between a read access from the
1068 * current bank and the next access.
1069 */
1070# define CFG_OR7_PRELIM (ORxG_AM_MSK |\
1071 ORxG_CSNT |\
1072 ORxG_ACS_DIV1 |\
1073 ORxG_SCY_15_CLK |\
1074 ORxG_TRLX |\
1075 ORxG_EHTR)
1076#endif /* CFG_LED_BASE */
1077
wdenkfe8c2802002-11-03 00:38:21 +00001078/*
1079 * Internal Definitions
1080 *
1081 * Boot Flags
1082 */
wdenk10a36a92004-07-10 23:02:23 +00001083#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1084#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenkfe8c2802002-11-03 00:38:21 +00001085
1086#endif /* __CONFIG_H */