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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 737f9eb02d7335df2b3e4d7a4d3348784d1da207 / . / cpu / ppc4xx / gpio.c
blob: 5235203ea28eae86266010fe16ca20dd75d97d51 [file] [log] [blame]
Stefan Roese3cb86f32007-03-24 15:45:34 +0100[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <asm/io.h>
27#include <asm/gpio.h>
28
29#if defined(CFG_440_GPIO_TABLE)
30gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
31#endif
32
33#if defined(GPIO0_OSRL)
34/* Only some 4xx variants support alternate funtions on the GPIO's */
35void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
36{
37 u32 mask;
38 u32 mask2;
39 u32 val;
40 u32 offs = 0;
41 u32 offs2 = 0;
42 int pin2 = pin << 1;
43
44 if (pin >= GPIO_MAX) {
45 offs = 0x100;
46 pin -= GPIO_MAX;
47 }
48
49 if (pin >= GPIO_MAX/2) {
50 offs2 = 0x100;
51 pin2 = (pin - GPIO_MAX/2) << 1;
52 }
53
54 mask = 0x80000000 >> pin;
55 mask2 = 0xc0000000 >> (pin2 << 1);
56
57 /* first set TCR to 0 */
58 out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);
59
60 if (in_out == GPIO_OUT) {
61 val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
62 switch (gpio_alt) {
63 case GPIO_ALT1:
64 val |= GPIO_ALT1_SEL >> pin2;
65 break;
66 case GPIO_ALT2:
67 val |= GPIO_ALT2_SEL >> pin2;
68 break;
69 case GPIO_ALT3:
70 val |= GPIO_ALT3_SEL >> pin2;
71 break;
72 }
73 out32(GPIO0_OSRL + offs + offs2, val);
74
75 /* setup requested output value */
76 if (out_val == GPIO_OUT_0)
77 out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
78 else if (out_val == GPIO_OUT_1)
79 out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask);
80
81 /* now configure TCR to drive output if selected */
82 out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask);
83 } else {
84 val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
85 val |= GPIO_IN_SEL >> pin2;
86 out32(GPIO0_ISR1L + offs + offs2, val);
87 }
88}
89#endif /* GPIO_OSRL */
90
91void gpio_write_bit(int pin, int val)
92{
93 u32 offs = 0;
94
95 if (pin >= GPIO_MAX) {
96 offs = 0x100;
97 pin -= GPIO_MAX;
98 }
99
100 if (val)
101 out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin));
102 else
103 out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
104}
105
Stefan Roese85f73732007-06-15 07:39:43 +0200[diff] [blame]106int gpio_read_out_bit(int pin)
107{
108 u32 offs = 0;
109
110 if (pin >= GPIO_MAX) {
111 offs = 0x100;
112 pin -= GPIO_MAX;
113 }
114
115 return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
116}
117
Stefan Roese3cb86f32007-03-24 15:45:34 +0100[diff] [blame]118#if defined(CFG_440_GPIO_TABLE)
119void gpio_set_chip_configuration(void)
120{
121 unsigned char i=0, j=0, offs=0, gpio_core;
122 unsigned long reg, core_add;
123
124 for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
125 j = 0;
126 offs = 0;
127 /* GPIO config of the GPIOs 0 to 31 */
128 for (i=0; i<GPIO_MAX; i++, j++) {
129 if (i == GPIO_MAX/2) {
130 offs = 4;
131 j = i-16;
132 }
133
134 core_add = gpio_tab[gpio_core][i].add;
135
136 if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
137 (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
138
139 switch (gpio_tab[gpio_core][i].alt_nb) {
140 case GPIO_SEL:
141 break;
142
143 case GPIO_ALT1:
144 reg = in32(GPIO_IS1(core_add+offs))
145 & ~(GPIO_MASK >> (j*2));
146 reg = reg | (GPIO_IN_SEL >> (j*2));
147 out32(GPIO_IS1(core_add+offs), reg);
148 break;
149
150 case GPIO_ALT2:
151 reg = in32(GPIO_IS2(core_add+offs))
152 & ~(GPIO_MASK >> (j*2));
153 reg = reg | (GPIO_IN_SEL >> (j*2));
154 out32(GPIO_IS2(core_add+offs), reg);
155 break;
156
157 case GPIO_ALT3:
158 reg = in32(GPIO_IS3(core_add+offs))
159 & ~(GPIO_MASK >> (j*2));
160 reg = reg | (GPIO_IN_SEL >> (j*2));
161 out32(GPIO_IS3(core_add+offs), reg);
162 break;
163 }
164 }
165
166 if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
167 (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
168
169 switch (gpio_tab[gpio_core][i].alt_nb) {
170 case GPIO_SEL:
171 if (gpio_core == GPIO0) {
Stefan Roese85f73732007-06-15 07:39:43 +0200[diff] [blame]172 /*
173 * Setup output value
174 * 1 -> high level
175 * 0 -> low level
176 * else -> don't touch
177 */
178 reg = in32(GPIO0_OR);
179 if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
180 reg |= (0x80000000 >> (i));
181 else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
182 reg &= ~(0x80000000 >> (i));
183 out32(GPIO0_OR, reg);
184
Benoît Moninfba3fb02007-06-08 09:55:24 +0200[diff] [blame]185 reg = in32(GPIO0_TCR) | (0x80000000 >> (i));
Stefan Roese3cb86f32007-03-24 15:45:34 +0100[diff] [blame]186 out32(GPIO0_TCR, reg);
187 }
188
189 if (gpio_core == GPIO1) {
Stefan Roese85f73732007-06-15 07:39:43 +0200[diff] [blame]190 /*
191 * Setup output value
192 * 1 -> high level
193 * 0 -> low level
194 * else -> don't touch
195 */
196 reg = in32(GPIO0_OR);
197 if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
198 reg |= (0x80000000 >> (i));
199 else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
200 reg &= ~(0x80000000 >> (i));
201 out32(GPIO0_OR, reg);
202
Benoît Moninfba3fb02007-06-08 09:55:24 +0200[diff] [blame]203 reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
Stefan Roese3cb86f32007-03-24 15:45:34 +0100[diff] [blame]204 out32(GPIO1_TCR, reg);
205 }
206
207 reg = in32(GPIO_OS(core_add+offs))
208 & ~(GPIO_MASK >> (j*2));
209 out32(GPIO_OS(core_add+offs), reg);
210 reg = in32(GPIO_TS(core_add+offs))
211 & ~(GPIO_MASK >> (j*2));
212 out32(GPIO_TS(core_add+offs), reg);
213 break;
214
215 case GPIO_ALT1:
216 reg = in32(GPIO_OS(core_add+offs))
217 & ~(GPIO_MASK >> (j*2));
218 reg = reg | (GPIO_ALT1_SEL >> (j*2));
219 out32(GPIO_OS(core_add+offs), reg);
220 reg = in32(GPIO_TS(core_add+offs))
221 & ~(GPIO_MASK >> (j*2));
222 reg = reg | (GPIO_ALT1_SEL >> (j*2));
223 out32(GPIO_TS(core_add+offs), reg);
224 break;
225
226 case GPIO_ALT2:
227 reg = in32(GPIO_OS(core_add+offs))
228 & ~(GPIO_MASK >> (j*2));
229 reg = reg | (GPIO_ALT2_SEL >> (j*2));
230 out32(GPIO_OS(core_add+offs), reg);
231 reg = in32(GPIO_TS(core_add+offs))
232 & ~(GPIO_MASK >> (j*2));
233 reg = reg | (GPIO_ALT2_SEL >> (j*2));
234 out32(GPIO_TS(core_add+offs), reg);
235 break;
236
237 case GPIO_ALT3:
238 reg = in32(GPIO_OS(core_add+offs))
239 & ~(GPIO_MASK >> (j*2));
240 reg = reg | (GPIO_ALT3_SEL >> (j*2));
241 out32(GPIO_OS(core_add+offs), reg);
242 reg = in32(GPIO_TS(core_add+offs))
243 & ~(GPIO_MASK >> (j*2));
244 reg = reg | (GPIO_ALT3_SEL >> (j*2));
245 out32(GPIO_TS(core_add+offs), reg);
246 break;
247 }
248 }
249 }
250 }
251}
252#endif /* CFG_440_GPIO_TABLE */