| Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 1 | CONFIG_PPC=y |
| 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 |
| Tom Rini | a09fea1 | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 3 | CONFIG_ENV_SIZE=0x2000 |
| 4 | CONFIG_ENV_SECT_SIZE=0x20000 |
| Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 5 | CONFIG_SYS_CLK_FREQ=66000000 |
| 6 | CONFIG_MPC83xx=y |
| 7 | CONFIG_TARGET_MPC837XEMDS=y |
| 8 | CONFIG_DDR_MC_CLOCK_MODE_1_1=y |
| 9 | CONFIG_SYSTEM_PLL_FACTOR_6_1=y |
| 10 | CONFIG_CORE_PLL_RATIO_15_1=y |
| 11 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y |
| 12 | CONFIG_TSEC1_MODE_RGMII=y |
| 13 | CONFIG_TSEC2_MODE_RGMII=y |
| 14 | CONFIG_LDP_PIN_MUX_STATE_0=y |
| Mario Six | 30915ab | 2019-01-21 09:17:57 +0100 | [diff] [blame] | 15 | CONFIG_BAT0=y |
| 16 | CONFIG_BAT0_NAME="SDRAM_LOWER" |
| 17 | CONFIG_BAT0_BASE=0x00000000 |
| 18 | CONFIG_BAT0_LENGTH_256_MBYTES=y |
| 19 | CONFIG_BAT0_ACCESS_RW=y |
| 20 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y |
| 21 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y |
| 22 | CONFIG_BAT0_USER_MODE_VALID=y |
| 23 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y |
| 24 | CONFIG_BAT1=y |
| 25 | CONFIG_BAT1_NAME="SDRAM_UPPER" |
| 26 | CONFIG_BAT1_BASE=0x10000000 |
| 27 | CONFIG_BAT1_LENGTH_256_MBYTES=y |
| 28 | CONFIG_BAT1_ACCESS_RW=y |
| 29 | CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y |
| 30 | CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y |
| 31 | CONFIG_BAT1_USER_MODE_VALID=y |
| 32 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y |
| 33 | CONFIG_BAT2=y |
| 34 | CONFIG_BAT2_NAME="IMMR" |
| 35 | CONFIG_BAT2_BASE=0xE0000000 |
| 36 | CONFIG_BAT2_LENGTH_8_MBYTES=y |
| 37 | CONFIG_BAT2_ACCESS_RW=y |
| 38 | CONFIG_BAT2_ICACHE_INHIBITED=y |
| 39 | CONFIG_BAT2_ICACHE_GUARDED=y |
| 40 | CONFIG_BAT2_DCACHE_INHIBITED=y |
| 41 | CONFIG_BAT2_DCACHE_GUARDED=y |
| 42 | CONFIG_BAT2_USER_MODE_VALID=y |
| 43 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y |
| 44 | CONFIG_BAT3=y |
| 45 | CONFIG_BAT3_NAME="BCSR" |
| 46 | CONFIG_BAT3_BASE=0xF8000000 |
| 47 | CONFIG_BAT3_ACCESS_RW=y |
| 48 | CONFIG_BAT3_ICACHE_INHIBITED=y |
| 49 | CONFIG_BAT3_ICACHE_GUARDED=y |
| 50 | CONFIG_BAT3_DCACHE_INHIBITED=y |
| 51 | CONFIG_BAT3_DCACHE_GUARDED=y |
| 52 | CONFIG_BAT3_USER_MODE_VALID=y |
| 53 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y |
| Mario Six | 9c5df7a | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 54 | CONFIG_LBLAW0=y |
| 55 | CONFIG_LBLAW0_BASE=0xFE000000 |
| 56 | CONFIG_LBLAW0_NAME="FLASH" |
| 57 | CONFIG_LBLAW0_LENGTH_32_MBYTES=y |
| 58 | CONFIG_LBLAW1=y |
| 59 | CONFIG_LBLAW1_BASE=0xF8000000 |
| 60 | CONFIG_LBLAW1_NAME="BCSR" |
| 61 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y |
| 62 | CONFIG_LBLAW3=y |
| 63 | CONFIG_LBLAW3_BASE=0xE0600000 |
| 64 | CONFIG_LBLAW3_NAME="NAND" |
| 65 | CONFIG_LBLAW3_LENGTH_32_KBYTES=y |
| Tom Rini | 344a0e4 | 2019-05-26 14:45:25 -0400 | [diff] [blame] | 66 | CONFIG_ELBC_BR0_OR0=y |
| 67 | CONFIG_BR0_OR0_NAME="FLASH" |
| 68 | CONFIG_BR0_OR0_BASE=0xFE000000 |
| 69 | CONFIG_BR0_PORTSIZE_16BIT=y |
| 70 | CONFIG_OR0_AM_32_MBYTES=y |
| 71 | CONFIG_OR0_XAM_SET=y |
| 72 | CONFIG_OR0_SCY_15=y |
| 73 | CONFIG_OR0_CSNT_EARLIER=y |
| 74 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y |
| 75 | CONFIG_OR0_XACS_EXTENDED=y |
| 76 | CONFIG_OR0_TRLX_RELAXED=y |
| 77 | CONFIG_OR0_EHTR_8_CYCLE=y |
| 78 | CONFIG_OR0_EAD_EXTRA=y |
| 79 | CONFIG_ELBC_BR1_OR1=y |
| 80 | CONFIG_BR1_OR1_NAME="BCSR" |
| 81 | CONFIG_BR1_OR1_BASE=0xF8000000 |
| 82 | CONFIG_OR1_XAM_SET=y |
| 83 | CONFIG_OR1_SCY_15=y |
| 84 | CONFIG_OR1_CSNT_EARLIER=y |
| 85 | CONFIG_OR1_XACS_EXTENDED=y |
| 86 | CONFIG_OR1_TRLX_RELAXED=y |
| 87 | CONFIG_OR1_EHTR_8_CYCLE=y |
| 88 | CONFIG_OR1_EAD_EXTRA=y |
| 89 | CONFIG_ELBC_BR3_OR3=y |
| 90 | CONFIG_BR3_OR3_NAME="NAND" |
| 91 | CONFIG_BR3_OR3_BASE=0xE0600000 |
| 92 | CONFIG_BR3_ERRORCHECKING_BOTH=y |
| 93 | CONFIG_BR3_MACHINE_FCM=y |
| 94 | CONFIG_OR3_BCTLD_NOT_ASSERTED=y |
| 95 | CONFIG_OR3_SCY_1=y |
| 96 | CONFIG_OR3_CST_ONE_CLOCK=y |
| 97 | CONFIG_OR3_CHT_TWO_CLOCK=y |
| 98 | CONFIG_OR3_RST_ONE_CLOCK=y |
| 99 | CONFIG_OR3_TRLX_RELAXED=y |
| 100 | CONFIG_OR3_EHTR_8_CYCLE=y |
| Mario Six | be5abb0 | 2019-01-21 09:18:09 +0100 | [diff] [blame] | 101 | CONFIG_HID0_FINAL_EMCP=y |
| 102 | CONFIG_HID0_FINAL_ICE=y |
| 103 | CONFIG_HID2_HBE=y |
| Mario Six | 73df96a | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 104 | CONFIG_ACR_PIPE_DEP_4=y |
| 105 | CONFIG_ACR_RPTCNT_4=y |
| Mario Six | e35012e | 2019-01-21 09:18:13 +0100 | [diff] [blame] | 106 | CONFIG_SPCR_TSECEP_3=y |
| Tom Rini | 344a0e4 | 2019-05-26 14:45:25 -0400 | [diff] [blame] | 107 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y |
| 108 | CONFIG_LCRR_CLKDIV_8=y |
| Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 109 | CONFIG_OF_BOARD_SETUP=y |
| 110 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
| 111 | CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" |
| 112 | CONFIG_BOOTDELAY=6 |
| 113 | CONFIG_HUSH_PARSER=y |
| 114 | CONFIG_CMD_IMLS=y |
| 115 | CONFIG_CMD_I2C=y |
| 116 | CONFIG_CMD_MMC=y |
| 117 | CONFIG_CMD_NAND=y |
| 118 | # CONFIG_CMD_SETEXPR is not set |
| 119 | CONFIG_CMD_MII=y |
| 120 | CONFIG_CMD_PING=y |
| 121 | CONFIG_CMD_DATE=y |
| 122 | CONFIG_CMD_EXT2=y |
| 123 | CONFIG_CMD_FAT=y |
| Tom Rini | a09fea1 | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 124 | CONFIG_ENV_ADDR=0xFE080000 |
| Tom Rini | 0cfccb5 | 2019-12-04 17:18:38 -0500 | [diff] [blame] | 125 | CONFIG_MTD=y |
| Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 126 | CONFIG_MTD_NOR_FLASH=y |
| 127 | CONFIG_FLASH_CFI_DRIVER=y |
| 128 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y |
| 129 | CONFIG_SYS_FLASH_CFI=y |
| Tom Rini | 0cfccb5 | 2019-12-04 17:18:38 -0500 | [diff] [blame] | 130 | CONFIG_MTD_RAW_NAND=y |
| Tom Rini | 306881a | 2020-04-24 15:35:53 -0400 | [diff] [blame] | 131 | CONFIG_PHY_ATHEROS=y |
| 132 | CONFIG_PHY_BROADCOM=y |
| 133 | CONFIG_PHY_DAVICOM=y |
| 134 | CONFIG_PHY_LXT=y |
| 135 | CONFIG_PHY_NATSEMI=y |
| 136 | CONFIG_PHY_REALTEK=y |
| 137 | CONFIG_PHY_SMSC=y |
| 138 | CONFIG_PHY_VITESSE=y |
| Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 139 | CONFIG_TSEC_ENET=y |
| 140 | # CONFIG_PCI is not set |
| 141 | CONFIG_SYS_NS16550=y |
| 142 | CONFIG_OF_LIBFDT=y |