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wdenke2211742002-11-02 23:30:20 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenke2211742002-11-02 23:30:20 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_IP860 1 /* ...on a IP860 board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038
39#define CONFIG_SYS_TEXT_BASE 0x10000000
40
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050042#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenke2211742002-11-02 23:30:20 +000043
44#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010048#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010049"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
wdenke2211742002-11-02 23:30:20 +000050
wdenke2211742002-11-02 23:30:20 +000051#undef CONFIG_BOOTARGS
52#define CONFIG_BOOTCOMMAND \
53 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010054 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
55 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenke2211742002-11-02 23:30:20 +000056 "bootm"
57
58#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke2211742002-11-02 23:30:20 +000060
61#undef CONFIG_WATCHDOG /* watchdog disabled */
62
63
64/* enable I2C and select the hardware/software driver */
65#undef CONFIG_HARD_I2C /* I2C with hardware support */
66#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
67/*
68 * Software (bit-bang) I2C driver configuration
69 */
70#define PB_SCL 0x00000020 /* PB 26 */
71#define PB_SDA 0x00000010 /* PB 27 */
72
73#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
74#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
75#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
76#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
77#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
78 else immr->im_cpm.cp_pbdat &= ~PB_SDA
79#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
80 else immr->im_cpm.cp_pbdat &= ~PB_SCL
81#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
82
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084# define CONFIG_SYS_I2C_SPEED 50000
85# define CONFIG_SYS_I2C_SLAVE 0xFE
86# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
87# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenke2211742002-11-02 23:30:20 +000088/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
90#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
91#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
wdenke2211742002-11-02 23:30:20 +000092
wdenk414eec32005-04-02 22:37:54 +000093#define CONFIG_TIMESTAMP /* Print image info with timestamp */
94
Jon Loeliger348f2582007-07-08 13:46:18 -050095
96/*
97 * Command line configuration.
98 */
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_BEDBUG
102#define CONFIG_CMD_I2C
103#define CONFIG_CMD_EEPROM
104#define CONFIG_CMD_NFS
105#define CONFIG_CMD_SNTP
wdenke2211742002-11-02 23:30:20 +0000106
Jon Loeliger7be044e2007-07-09 21:24:19 -0500107/*
108 * BOOTP options
109 */
110#define CONFIG_BOOTP_SUBNETMASK
111#define CONFIG_BOOTP_GATEWAY
112#define CONFIG_BOOTP_HOSTNAME
113#define CONFIG_BOOTP_BOOTPATH
wdenke2211742002-11-02 23:30:20 +0000114
wdenke2211742002-11-02 23:30:20 +0000115/*
116 * Miscellaneous configurable options
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_LONGHELP /* undef to save memory */
119#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500120#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000122#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000124#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
126#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
127#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
130#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
wdenke2211742002-11-02 23:30:20 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +0000139
140/*
141 * Low Level Configuration Settings
142 * (address mappings, register initial values, etc.)
143 * You should know what you are doing if you make changes here.
144 */
145/*-----------------------------------------------------------------------
146 * Internal Memory Mapped Register
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_IMMR 0xF1000000 /* Non-standard value!! */
wdenke2211742002-11-02 23:30:20 +0000149
150/*-----------------------------------------------------------------------
151 * Definitions for initial stack pointer and data area (in DPRAM)
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200154#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200155#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000157
158/*-----------------------------------------------------------------------
159 * Start addresses for the final memory configuration
160 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_SDRAM_BASE 0x00000000
164#define CONFIG_SYS_FLASH_BASE 0x10000000
wdenke2211742002-11-02 23:30:20 +0000165#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
wdenke2211742002-11-02 23:30:20 +0000167#else
168#if 0 /* need more space for I2C tests */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenke2211742002-11-02 23:30:20 +0000170#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MONITOR_LEN (256 << 10)
wdenke2211742002-11-02 23:30:20 +0000172#endif
173#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
175#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000176
177/*
178 * For booting Linux, the board info and command line data
179 * have to be in the first 8 MB of memory, since this is
180 * the maximum mapped by the Linux kernel during initialization.
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000183/*-----------------------------------------------------------------------
184 * FLASH organization
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
187#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
190#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000191
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200192#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200193#undef CONFIG_ENV_IS_IN_NVRAM
194#undef CONFIG_ENV_IS_IN_NVRAM
wdenke2211742002-11-02 23:30:20 +0000195#undef DEBUG_I2C
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200196#define CONFIG_ENV_IS_IN_EEPROM
wdenke2211742002-11-02 23:30:20 +0000197
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200198#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200199#define CONFIG_ENV_ADDR 0x20000000 /* use SRAM */
200#define CONFIG_ENV_SIZE (16<<10) /* use 16 kB */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200201#endif /* CONFIG_ENV_IS_IN_NVRAM */
wdenke2211742002-11-02 23:30:20 +0000202
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200203#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200204#define CONFIG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
205#define CONFIG_ENV_SIZE 1536 /* Use remaining space */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200206#endif /* CONFIG_ENV_IS_IN_EEPROM */
wdenke2211742002-11-02 23:30:20 +0000207
208/*-----------------------------------------------------------------------
209 * Cache Configuration
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500212#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000214#endif
Heiko Schocher506f3912009-03-12 07:37:15 +0100215#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
216 * running in RAM.
217 */
wdenke2211742002-11-02 23:30:20 +0000218
219/*-----------------------------------------------------------------------
220 * SYPCR - System Protection Control 11-9
221 * SYPCR can only be written once after reset!
222 *-----------------------------------------------------------------------
223 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
224 * +0x0004
225 */
226#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke2211742002-11-02 23:30:20 +0000228 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
229#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenke2211742002-11-02 23:30:20 +0000231#endif
232
233/*-----------------------------------------------------------------------
234 * SIUMCR - SIU Module Configuration 11-6
235 *-----------------------------------------------------------------------
236 * +0x0000 => 0x80600800
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \
wdenke2211742002-11-02 23:30:20 +0000239 SIUMCR_DBGC11 | SIUMCR_MLRC10)
240
241/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000242 * Clock Setting - get clock frequency from Board Revision Register
wdenke2211742002-11-02 23:30:20 +0000243 *-----------------------------------------------------------------------
244 */
wdenk3bac3512003-03-12 10:41:04 +0000245#ifndef __ASSEMBLY__
246extern unsigned long ip860_get_clk_freq (void);
247#endif
248#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq()
wdenke2211742002-11-02 23:30:20 +0000249
250/*-----------------------------------------------------------------------
251 * TBSCR - Time Base Status and Control 11-26
252 *-----------------------------------------------------------------------
253 * Clear Reference Interrupt Status, Timebase freezing enabled
254 * +0x0200 => 0x00C2
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenke2211742002-11-02 23:30:20 +0000257
258/*-----------------------------------------------------------------------
259 * PISCR - Periodic Interrupt Status and Control 11-31
260 *-----------------------------------------------------------------------
261 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
262 * +0x0240 => 0x0082
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenke2211742002-11-02 23:30:20 +0000265
266/*-----------------------------------------------------------------------
267 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
268 *-----------------------------------------------------------------------
269 * Reset PLL lock status sticky bit, timer expired status bit and timer
270 * interrupt status bit, set PLL multiplication factor !
271 */
272/* +0x0286 => was: 0x0000D000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_PLPRCR \
wdenke2211742002-11-02 23:30:20 +0000274 ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
275 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
276 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
277 )
278
279/*-----------------------------------------------------------------------
280 * SCCR - System Clock and reset Control Register 15-27
281 *-----------------------------------------------------------------------
282 * Set clock output, timebase and RTC source and divider,
283 * power management and some other internal clocks
284 */
285#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
wdenke2211742002-11-02 23:30:20 +0000287 SCCR_RTDIV | SCCR_RTSEL | \
288 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
289 SCCR_EBDF00 | SCCR_DFSYNC00 | \
290 SCCR_DFBRG00 | SCCR_DFNL000 | \
291 SCCR_DFNH000)
292
293/*-----------------------------------------------------------------------
294 * RTCSC - Real-Time Clock Status and Control Register 11-27
295 *-----------------------------------------------------------------------
296 */
297/* +0x0220 => 0x00C3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenke2211742002-11-02 23:30:20 +0000299
300
301/*-----------------------------------------------------------------------
302 * RCCR - RISC Controller Configuration Register 19-4
303 *-----------------------------------------------------------------------
304 */
305/* +0x09C4 => TIMEP=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_RCCR 0x0100
wdenke2211742002-11-02 23:30:20 +0000307
308/*-----------------------------------------------------------------------
309 * RMDS - RISC Microcode Development Support Control Register
310 *-----------------------------------------------------------------------
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_RMDS 0
wdenke2211742002-11-02 23:30:20 +0000313
314/*-----------------------------------------------------------------------
315 * DER - Debug Event Register
316 *-----------------------------------------------------------------------
317 *
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_DER 0
wdenke2211742002-11-02 23:30:20 +0000320
321/*
322 * Init Memory Controller:
323 */
324
325/*
326 * MAMR settings for SDRAM - 16-14
327 * => 0xC3804114
328 */
329
330/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_MAMR_PTA 0xC3
wdenke2211742002-11-02 23:30:20 +0000332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke2211742002-11-02 23:30:20 +0000334 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
335 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
336/*
337 * BR1 and OR1 (FLASH)
338 */
339#define FLASH_BASE 0x10000000 /* FLASH bank #0 */
340
341/* used to re-map FLASH
342 * restrict access enough to keep SRAM working (if any)
343 * but not too much to meddle with FLASH accesses
344 */
345/* allow for max 8 MB of Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
347#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
wdenke2211742002-11-02 23:30:20 +0000348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
wdenke2211742002-11-02 23:30:20 +0000350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
352#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenke2211742002-11-02 23:30:20 +0000353/* 16 bit, bank valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
wdenke2211742002-11-02 23:30:20 +0000355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
357#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR0_PRELIM
wdenke2211742002-11-02 23:30:20 +0000358
359/*
360 * BR2/OR2 - SDRAM
361 */
362#define SDRAM_BASE 0x00000000 /* SDRAM bank */
363#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
364#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
365
366#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
369#define CONFIG_SYS_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000370
371/*
372 * BR3/OR3 - SRAM (16 bit)
373 */
374#define SRAM_BASE 0x20000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
376#define CONFIG_SYS_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
377#define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
378#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */
379#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */
Wolfgang Denk36116652010-08-11 09:38:31 +0200380#define CONFIG_SYS_SRAM_BASE SRAM_BASE
381#define CONFIG_SYS_SRAM_SIZE SRAM_SIZE
wdenke2211742002-11-02 23:30:20 +0000382
383/*
384 * BR4/OR4 - Board Control & Status (8 bit)
385 */
386#define BCSR_BASE 0xFC000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_OR4 0xFFFF0120 /* BI (internal) */
388#define CONFIG_SYS_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000389
390/*
391 * BR5/OR5 - IP Slot A/B (16 bit)
392 */
393#define IP_SLOT_BASE 0x40000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
395#define CONFIG_SYS_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000396
397/*
398 * BR6/OR6 - VME STD (16 bit)
399 */
400#define VME_STD_BASE 0xFE000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
402#define CONFIG_SYS_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000403
404/*
405 * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
406 */
407#define VME_SHORT_BASE 0xFF000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
409#define CONFIG_SYS_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000410
411/*-----------------------------------------------------------------------
412 * Board Control and Status Region:
413 *-----------------------------------------------------------------------
414 */
415#ifndef __ASSEMBLY__
416typedef struct ip860_bcsr_s {
417 unsigned char shmem_addr; /* +00 shared memory address register */
418 unsigned char reserved0;
419 unsigned char mbox_addr; /* +02 mailbox address register */
420 unsigned char reserved1;
421 unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
422 unsigned char reserved2;
423 unsigned char vme_int_pend; /* +06 VME interrupt pending register */
424 unsigned char reserved3;
425 unsigned char bd_int_mask; /* +08 board interrupt mask register */
426 unsigned char reserved4;
427 unsigned char bd_int_pend; /* +0A board interrupt pending register */
428 unsigned char reserved5;
429 unsigned char bd_ctrl; /* +0C board control register */
430 unsigned char reserved6;
431 unsigned char bd_status; /* +0E board status register */
432 unsigned char reserved7;
433 unsigned char vme_irq; /* +10 VME interrupt request register */
434 unsigned char reserved8;
435 unsigned char vme_ivec; /* +12 VME interrupt vector register */
436 unsigned char reserved9;
437 unsigned char cli_mbox; /* +14 clear mailbox irq */
438 unsigned char reservedA;
439 unsigned char rtc; /* +16 RTC control register */
440 unsigned char reservedB;
441 unsigned char mbox_data; /* +18 mailbox read/write register */
442 unsigned char reservedC;
443 unsigned char wd_trigger; /* +1A Watchdog trigger register */
444 unsigned char reservedD;
445 unsigned char rmw_req; /* +1C RMW request register */
wdenk3bac3512003-03-12 10:41:04 +0000446 unsigned char reservedE;
447 unsigned char bd_rev; /* +1E Board Revision register */
wdenke2211742002-11-02 23:30:20 +0000448} ip860_bcsr_t;
449#endif /* __ASSEMBLY__ */
450
451/*-----------------------------------------------------------------------
452 * Board Control Register: bd_ctrl (Offset 0x0C)
453 *-----------------------------------------------------------------------
454 */
455#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
456#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
457#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
458#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
459
wdenke2211742002-11-02 23:30:20 +0000460#endif /* __CONFIG_H */