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TsiChung Liew05316f82008-08-11 13:41:49 +00001/*
2 * Configuation settings for the Freescale MCF54451 EVB board.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _M54451EVB_H
31#define _M54451EVB_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF5445x /* define processor family */
38#define CONFIG_M54451 /* define processor type */
39#define CONFIG_M54451EVB /* M54451EVB board */
40
41#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew05316f82008-08-11 13:41:49 +000043#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
TsiChung Liew05316f82008-08-11 13:41:49 +000045
46#undef CONFIG_WATCHDOG
47
48#define CONFIG_TIMESTAMP /* Print image info with timestamp */
49
50/*
51 * BOOTP options
52 */
53#define CONFIG_BOOTP_BOOTFILESIZE
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57
58/* Command line configuration */
59#include <config_cmd_default.h>
60
61#define CONFIG_CMD_BOOTD
62#define CONFIG_CMD_CACHE
63#define CONFIG_CMD_DATE
64#define CONFIG_CMD_DHCP
65#define CONFIG_CMD_ELF
66#define CONFIG_CMD_FLASH
67#define CONFIG_CMD_I2C
68#undef CONFIG_CMD_JFFS2
69#define CONFIG_CMD_MEMORY
70#define CONFIG_CMD_MISC
71#define CONFIG_CMD_MII
72#define CONFIG_CMD_NET
TsiChung Liew709b3842009-06-11 15:39:57 +000073#define CONFIG_CMD_NFS
TsiChung Liew05316f82008-08-11 13:41:49 +000074#define CONFIG_CMD_PING
75#define CONFIG_CMD_REGINFO
76#define CONFIG_CMD_SPI
77#define CONFIG_CMD_SF
78
79#undef CONFIG_CMD_LOADB
80#undef CONFIG_CMD_LOADS
81
82/* Network configuration */
83#define CONFIG_MCFFEC
84#ifdef CONFIG_MCFFEC
85# define CONFIG_NET_MULTI 1
86# define CONFIG_MII 1
87# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088# define CONFIG_SYS_DISCOVER_PHY
89# define CONFIG_SYS_RX_ETH_BUFFER 8
90# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew05316f82008-08-11 13:41:49 +000091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092# define CONFIG_SYS_FEC0_PINMUX 0
93# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChung Liew05316f82008-08-11 13:41:49 +000094# define MCFFEC_TOUT_LOOP 50000
95
96# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
TsiChung Liew052c0892009-07-08 07:41:24 +000097# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
TsiChung Liew05316f82008-08-11 13:41:49 +000098# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
99# define CONFIG_ETHPRIME "FEC0"
100# define CONFIG_IPADDR 192.162.1.2
101# define CONFIG_NETMASK 255.255.255.0
102# define CONFIG_SERVERIP 192.162.1.1
103# define CONFIG_GATEWAYIP 192.162.1.1
104# define CONFIG_OVERWRITE_ETHADDR_ONCE
105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
107# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChung Liew05316f82008-08-11 13:41:49 +0000108# define FECDUPLEX FULL
109# define FECSPEED _100BASET
110# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
112# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChung Liew05316f82008-08-11 13:41:49 +0000113# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChung Liew05316f82008-08-11 13:41:49 +0000115#endif
116
117#define CONFIG_HOSTNAME M54451EVB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#ifdef CONFIG_SYS_STMICRO_BOOT
TsiChung Liew05316f82008-08-11 13:41:49 +0000119/* ST Micro serial flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_LOAD_ADDR2 0x40010007
TsiChung Liew05316f82008-08-11 13:41:49 +0000121#define CONFIG_EXTRA_ENV_SETTINGS \
122 "netdev=eth0\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000124 "loadaddr=0x40010000\0" \
125 "sbfhdr=sbfhdr.bin\0" \
126 "uboot=u-boot.bin\0" \
127 "load=tftp ${loadaddr} ${sbfhdr};" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000129 "upd=run load; run prog\0" \
130 "prog=sf probe 0:1 10000 1;" \
131 "sf erase 0 30000;" \
132 "sf write ${loadaddr} 0 30000;" \
133 "save\0" \
134 ""
135#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_UBOOT_END 0x3FFFF
TsiChung Liew05316f82008-08-11 13:41:49 +0000137#define CONFIG_EXTRA_ENV_SETTINGS \
138 "netdev=eth0\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000140 "loadaddr=40010000\0" \
141 "u-boot=u-boot.bin\0" \
142 "load=tftp ${loadaddr) ${u-boot}\0" \
143 "upd=run load; run prog\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 "prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END) \
145 "; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;" \
TsiChung Liew05316f82008-08-11 13:41:49 +0000146 "cp.b ${loadaddr} 0 ${filesize};" \
147 "save\0" \
148 ""
149#endif
150
151/* Realtime clock */
152#define CONFIG_MCFRTC
153#undef RTC_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
TsiChung Liew05316f82008-08-11 13:41:49 +0000155
156/* Timer */
157#define CONFIG_MCFTMR
158#undef CONFIG_MCFPIT
159
160/* I2c */
161#define CONFIG_FSL_I2C
162#define CONFIG_HARD_I2C /* I2C with hardware support */
163#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
165#define CONFIG_SYS_I2C_SLAVE 0x7F
166#define CONFIG_SYS_I2C_OFFSET 0x58000
TsiChung Liew709b3842009-06-11 15:39:57 +0000167#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChung Liew05316f82008-08-11 13:41:49 +0000168
169/* DSPI and Serial Flash */
TsiChung Liewee0a8462009-06-30 14:18:29 +0000170#define CONFIG_CF_SPI
TsiChung Liew05316f82008-08-11 13:41:49 +0000171#define CONFIG_CF_DSPI
172#define CONFIG_SERIAL_FLASH
173#define CONFIG_HARD_SPI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_SBFHDR_SIZE 0x7
TsiChung Liew05316f82008-08-11 13:41:49 +0000175#ifdef CONFIG_CMD_SPI
176# define CONFIG_SPI_FLASH
177# define CONFIG_SPI_FLASH_STMICRO
178
TsiChung Liewee0a8462009-06-30 14:18:29 +0000179# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
180 DSPI_CTAR_PCSSCK_1CLK | \
181 DSPI_CTAR_PASC(0) | \
182 DSPI_CTAR_PDT(0) | \
183 DSPI_CTAR_CSSCK(0) | \
184 DSPI_CTAR_ASC(0) | \
185 DSPI_CTAR_DT(1))
186# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
187# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
TsiChung Liew05316f82008-08-11 13:41:49 +0000188#endif
189
190/* Input, PCI, Flexbus, and VCO */
191#define CONFIG_EXTRA_CLOCK
192
TsiChung Liew709b3842009-06-11 15:39:57 +0000193#define CONFIG_PRAM 2048 /* 2048 KB */
TsiChung Liew05316f82008-08-11 13:41:49 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_PROMPT "-> "
196#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChung Liew05316f82008-08-11 13:41:49 +0000197
198#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChung Liew05316f82008-08-11 13:41:49 +0000200#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChung Liew05316f82008-08-11 13:41:49 +0000202#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
204#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
205#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChung Liew05316f82008-08-11 13:41:49 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
TsiChung Liew05316f82008-08-11 13:41:49 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_HZ 1000
TsiChung Liew05316f82008-08-11 13:41:49 +0000210
TsiChung Liew709b3842009-06-11 15:39:57 +0000211#define CONFIG_SYS_MBAR 0xFC000000
TsiChung Liew05316f82008-08-11 13:41:49 +0000212
213/*
214 * Low Level Configuration Settings
215 * (address mappings, register initial values, etc.)
216 * You should know what you are doing if you make changes here.
217 */
218
219/*-----------------------------------------------------------------------
220 * Definitions for initial stack pointer and data area (in DPRAM)
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200223#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200225#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk553f0982010-10-26 13:32:32 +0200227#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
TsiChung Liew05316f82008-08-11 13:41:49 +0000228
229/*-----------------------------------------------------------------------
230 * Start addresses for the final memory configuration
231 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChung Liew05316f82008-08-11 13:41:49 +0000233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_SDRAM_BASE 0x40000000
235#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
236#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
237#define CONFIG_SYS_SDRAM_CFG2 0x57670000
238#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
239#define CONFIG_SYS_SDRAM_EMOD 0x80810000
240#define CONFIG_SYS_SDRAM_MODE 0x008D0000
241#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
TsiChung Liew05316f82008-08-11 13:41:49 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
244#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChung Liew05316f82008-08-11 13:41:49 +0000245
246#ifdef CONFIG_CF_SBF
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200247# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
TsiChung Liew05316f82008-08-11 13:41:49 +0000248#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liew05316f82008-08-11 13:41:49 +0000250#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
252#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
253#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChung Liew05316f82008-08-11 13:41:49 +0000254
255/*
256 * For booting Linux, the board info and command line data
257 * have to be in the first 8 MB of memory, since this is
258 * the maximum mapped by the Linux kernel during initialization ??
259 */
260/* Initial Memory map for Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liew05316f82008-08-11 13:41:49 +0000262
263/* Configuration for environment
264 * Environment is embedded in u-boot in the second sector of the flash
265 */
TsiChung Liew709b3842009-06-11 15:39:57 +0000266#if defined(CONFIG_SYS_STMICRO_BOOT)
Jean-Christophe PLAGNIOL-VILLARD0b5099a2008-09-10 22:48:00 +0200267# define CONFIG_ENV_IS_IN_SPI_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200268# define CONFIG_ENV_SPI_CS 1
269# define CONFIG_ENV_OFFSET 0x20000
270# define CONFIG_ENV_SIZE 0x2000
271# define CONFIG_ENV_SECT_SIZE 0x10000
TsiChung Liew05316f82008-08-11 13:41:49 +0000272#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200273# define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew709b3842009-06-11 15:39:57 +0000274# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
275# define CONFIG_ENV_SIZE 0x2000
276# define CONFIG_ENV_SECT_SIZE 0x8000
TsiChung Liew05316f82008-08-11 13:41:49 +0000277#endif
278#undef CONFIG_ENV_OVERWRITE
TsiChung Liew05316f82008-08-11 13:41:49 +0000279
TsiChung Liewee0a8462009-06-30 14:18:29 +0000280/* FLASH organization */
281#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
TsiChung Liew05316f82008-08-11 13:41:49 +0000282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_FLASH_CFI
284#ifdef CONFIG_SYS_FLASH_CFI
TsiChung Liew05316f82008-08-11 13:41:49 +0000285
286# define CONFIG_FLASH_CFI_DRIVER 1
TsiChung Liew709b3842009-06-11 15:39:57 +0000287# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
289# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
290# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
291# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
292# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
293# define CONFIG_SYS_FLASH_CHECKSUM
294# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
TsiChung Liew05316f82008-08-11 13:41:49 +0000295
296#endif
297
298/*
299 * This is setting for JFFS2 support in u-boot.
300 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
301 */
TsiChung Liew709b3842009-06-11 15:39:57 +0000302#ifdef CONFIG_CMD_JFFS2
TsiChung Liew05316f82008-08-11 13:41:49 +0000303# define CONFIG_JFFS2_DEV "nor0"
304# define CONFIG_JFFS2_PART_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
TsiChung Liew05316f82008-08-11 13:41:49 +0000306#endif
307
TsiChung Liew709b3842009-06-11 15:39:57 +0000308/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChung Liew05316f82008-08-11 13:41:49 +0000310
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600311#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200312 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600313#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200314 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600315#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
316#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
317#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
318 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
319 CF_ACR_EN | CF_ACR_SM_ALL)
320#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
321 CF_CACR_ICINVA | CF_CACR_EUSP)
322#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
323 CF_CACR_DEC | CF_CACR_DDCM_P | \
324 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
325
TsiChung Liew05316f82008-08-11 13:41:49 +0000326/*-----------------------------------------------------------------------
327 * Memory bank definitions
328 */
329/*
TsiChung Liew709b3842009-06-11 15:39:57 +0000330 * CS0 - NOR Flash 16MB
TsiChung Liew05316f82008-08-11 13:41:49 +0000331 * CS1 - Available
332 * CS2 - Available
333 * CS3 - Available
334 * CS4 - Available
335 * CS5 - Available
336 */
337
TsiChung Liew709b3842009-06-11 15:39:57 +0000338 /* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_CS0_BASE 0x00000000
TsiChung Liew709b3842009-06-11 15:39:57 +0000340#define CONFIG_SYS_CS0_MASK 0x00FF0001
341#define CONFIG_SYS_CS0_CTRL 0x00004D80
TsiChung Liew05316f82008-08-11 13:41:49 +0000342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
TsiChung Liew05316f82008-08-11 13:41:49 +0000344
345#endif /* _M54451EVB_H */