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Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04001/*
2 * (C) Copyright 2010
3 * ISEE 2007 SL, <www.iseebcn.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef __CONFIG_H
22#define __CONFIG_H
23#include <asm/sizes.h>
24
25/*
26 * High Level Configuration Options
27 */
28#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
29#define CONFIG_OMAP 1 /* in a TI OMAP core */
30#define CONFIG_OMAP34XX 1 /* which is a 34XX */
31#define CONFIG_OMAP3430 1 /* which is in a 3430 */
32#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */
33
34#define CONFIG_SDRC /* The chip has SDRC controller */
35
36#include <asm/arch/cpu.h>
37#include <asm/arch/omap3.h>
38
39/*
40 * Display CPU and Board information
41 */
42#define CONFIG_DISPLAY_CPUINFO 1
43#define CONFIG_DISPLAY_BOARDINFO 1
44
45/* Clock Defines */
46#define V_OSCK 26000000 /* Clock output from T2 */
47#define V_SCLK (V_OSCK >> 1)
48
49#define CONFIG_MISC_INIT_R
50
51#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
52#define CONFIG_SETUP_MEMORY_TAGS 1
53#define CONFIG_INITRD_TAG 1
54#define CONFIG_REVISION_TAG 1
55
56/*
57 * NS16550 Configuration
58 */
59
60#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
61
62#define CONFIG_SYS_NS16550
63#define CONFIG_SYS_NS16550_SERIAL
64#define CONFIG_SYS_NS16550_REG_SIZE (-4)
65#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
66
67/* select serial console configuration */
68#define CONFIG_CONS_INDEX 3
69#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
70#define CONFIG_SERIAL3 3
71
72/* allow to overwrite serial and ethaddr */
73#define CONFIG_ENV_OVERWRITE
74#define CONFIG_BAUDRATE 115200
75#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
Enric Balletbo i Serraf49d7b62010-11-04 15:34:33 -040076#define CONFIG_GENERIC_MMC 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040077#define CONFIG_MMC 1
Enric Balletbo i Serraf49d7b62010-11-04 15:34:33 -040078#define CONFIG_OMAP_HSMMC 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040079#define CONFIG_DOS_PARTITION 1
80
81/* DDR */
82#define CONFIG_OMAP3_NUMONYX_DDR 1
83
84/* USB */
85#define CONFIG_MUSB_UDC 1
86#define CONFIG_USB_OMAP3 1
87#define CONFIG_TWL4030_USB 1
88
89/* USB device configuration */
90#define CONFIG_USB_DEVICE 1
91#define CONFIG_USB_TTY 1
92#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
93
94/* Change these to suit your needs */
95#define CONFIG_USBD_VENDORID 0x0451
96#define CONFIG_USBD_PRODUCTID 0x5678
97#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
98#define CONFIG_USBD_PRODUCT_NAME "IGEP"
99
100/* commands to include */
101#include <config_cmd_default.h>
102
103#define CONFIG_CMD_CACHE
104#define CONFIG_CMD_EXT2 /* EXT2 Support */
105#define CONFIG_CMD_FAT /* FAT support */
106#define CONFIG_CMD_I2C /* I2C serial bus support */
107#define CONFIG_CMD_MMC /* MMC support */
108#define CONFIG_CMD_ONENAND /* ONENAND support */
109#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
110#define CONFIG_CMD_DHCP
111#define CONFIG_CMD_PING
112#define CONFIG_CMD_NFS /* NFS support */
113#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
114#define CONFIG_MTD_DEVICE
115
116#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
117#undef CONFIG_CMD_IMLS /* List all found images */
118
119#define CONFIG_SYS_NO_FLASH
120#define CONFIG_HARD_I2C 1
121#define CONFIG_SYS_I2C_SPEED 100000
122#define CONFIG_SYS_I2C_SLAVE 1
123#define CONFIG_SYS_I2C_BUS 0
124#define CONFIG_SYS_I2C_BUS_SELECT 1
125#define CONFIG_DRIVER_OMAP34XX_I2C 1
126
127/*
128 * TWL4030
129 */
130#define CONFIG_TWL4030_POWER 1
131
132/* Environment information */
133#define CONFIG_BOOTCOMMAND \
134 "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
135
136#define CONFIG_BOOTDELAY 3
137
138#define CONFIG_EXTRA_ENV_SETTINGS \
139 "usbtty=cdc_acm\0"
140
141#define CONFIG_AUTO_COMPLETE 1
142
143/*
144 * Miscellaneous configurable options
145 */
146#define CONFIG_SYS_LONGHELP /* undef to save memory */
147#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
148#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
149#define CONFIG_SYS_PROMPT "U-Boot # "
150#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
151/* Print Buffer Size */
152#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
153 sizeof(CONFIG_SYS_PROMPT) + 16)
154#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
155/* Boot Argument Buffer Size */
156#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
157
158#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
159 /* works on */
160#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
161 0x01F00000) /* 31MB */
162
163#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
164 /* load address */
165
166#define CONFIG_SYS_MONITOR_LEN (256 << 10)
167
168/*
169 * OMAP3 has 12 GP timers, they can be driven by the system clock
170 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
171 * This rate is divided by a local divisor.
172 */
173#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
174#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
175#define CONFIG_SYS_HZ 1000
176
177/*
178 * Stack sizes
179 *
180 * The stack sizes are set up in start.S using the settings below
181 */
182#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
183
184/*
185 * Physical Memory Map
186 *
187 */
188#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
189#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
190#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
191#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
192
193/* SDRAM Bank Allocation method */
194#define SDRC_R_B_C 1
195
196/*
197 * FLASH and environment organization
198 */
199
200#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
201
202#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
203
204#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
205
206#define CONFIG_ENV_IS_IN_ONENAND 1
207#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
208#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
209
210/*
211 * Size of malloc() pool
212 */
213#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400214
215/*
216 * SMSC911x Ethernet
217 */
218#if defined(CONFIG_CMD_NET)
219#define CONFIG_NET_MULTI
220#define CONFIG_SMC911X
221#define CONFIG_SMC911X_32_BIT
222#define CONFIG_SMC911X_BASE 0x2C000000
223#endif /* (CONFIG_CMD_NET) */
224
225#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Steve Sakoman31bfcf12010-10-27 05:04:30 -0700226#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
227#define CONFIG_SYS_INIT_RAM_SIZE 0x800
228#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
229 CONFIG_SYS_INIT_RAM_SIZE - \
230 GENERATED_GBL_DATA_SIZE)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400231
232#endif /* __CONFIG_H */