blob: 77bcc29aa6f9e742940c956ed188adac4c467ed5 [file] [log] [blame]
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -05002 * Copyright 2004, 2007 Freescale Semiconductor.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Jon Loeligerd9b94f22005-07-25 14:05:07 -050015 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8548cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8548 1 /* MPC8548 specific */
37#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
38
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050039#define CONFIG_PCI /* enable any pci type devices */
40#define CONFIG_PCI1 /* PCI controller 1 */
41#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
42#undef CONFIG_RIO
43#undef CONFIG_PCI2
44#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ff3de62007-12-07 12:17:34 -060045#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050046
47#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050048#define CONFIG_ENV_OVERWRITE
49#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
50#define CONFIG_DDR_DLL /* possible DLL fix needed */
ebony.zhu@freescale.com39b18c42006-12-18 16:25:15 +080051#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050052
53#define CONFIG_DDR_ECC /* only for ECC DDR module */
54#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
55#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050056#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050057
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060058#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Kumar Gala0db37dc2008-01-17 01:01:09 -060059#define CONFIG_FSL_INIT_TLBS 1 /* Use common FSL init code */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050060
61/*
62 * When initializing flash, if we cannot find the manufacturer ID,
63 * assume this is the AMD flash associated with the CDS board.
64 * This allows booting from a promjet.
65 */
66#define CONFIG_ASSUME_AMD_FLASH
67
68#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
69
70#ifndef __ASSEMBLY__
71extern unsigned long get_clock_freq(void);
72#endif
73#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
74
75/*
76 * These can be toggled for performance analysis, otherwise use default.
77 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050078#define CONFIG_L2_CACHE /* toggle L2 cache */
79#define CONFIG_BTB /* toggle branch predition */
80#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
81#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050082
83/*
84 * Only possible on E500 Version 2 or newer cores.
85 */
86#define CONFIG_ENABLE_36BIT_PHYS 1
87
Jon Loeligerd9b94f22005-07-25 14:05:07 -050088#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
89
90#undef CFG_DRAM_TEST /* memory test, takes time */
91#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
92#define CFG_MEMTEST_END 0x00400000
93
94/*
95 * Base addresses -- Note these are effective addresses where the
96 * actual resources get mapped (not physical addresses)
97 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050098#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050099#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
100#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
101
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500102#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
103#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
104#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
105
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500106/*
107 * DDR Setup
108 */
109#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
110#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
111
112#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
113
114/*
115 * Make sure required options are set
116 */
117#ifndef CONFIG_SPD_EEPROM
118#error ("CONFIG_SPD_EEPROM is required")
119#endif
120
121#undef CONFIG_CLOCKS_IN_MHZ
122
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500123/*
124 * Local Bus Definitions
125 */
126
127/*
128 * FLASH on the Local Bus
129 * Two banks, 8M each, using the CFI driver.
130 * Boot from BR0/OR0 bank at 0xff00_0000
131 * Alternate BR1/OR1 bank at 0xff80_0000
132 *
133 * BR0, BR1:
134 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
135 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
136 * Port Size = 16 bits = BRx[19:20] = 10
137 * Use GPCM = BRx[24:26] = 000
138 * Valid = BRx[31] = 1
139 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500140 * 0 4 8 12 16 20 24 28
141 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
142 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500143 *
144 * OR0, OR1:
145 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
146 * Reserved ORx[17:18] = 11, confusion here?
147 * CSNT = ORx[20] = 1
148 * ACS = half cycle delay = ORx[21:22] = 11
149 * SCY = 6 = ORx[24:27] = 0110
150 * TRLX = use relaxed timing = ORx[29] = 1
151 * EAD = use external address latch delay = OR[31] = 1
152 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500153 * 0 4 8 12 16 20 24 28
154 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500155 */
156
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500157#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */
158#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500159
160#define CFG_BR0_PRELIM 0xff801001
161#define CFG_BR1_PRELIM 0xff001001
162
163#define CFG_OR0_PRELIM 0xff806e65
164#define CFG_OR1_PRELIM 0xff806e65
165
166#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
167#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
168#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
169#undef CFG_FLASH_CHECKSUM
170#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
171#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
172
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500173#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500174
175#define CFG_FLASH_CFI_DRIVER
176#define CFG_FLASH_CFI
177#define CFG_FLASH_EMPTY_INFO
178
179
180/*
181 * SDRAM on the Local Bus
182 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500183#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
184#define CFG_LBC_CACHE_SIZE 64
185#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
186#define CFG_LBC_NONCACHE_SIZE 64
187
188#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500189#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
190
191/*
192 * Base Register 2 and Option Register 2 configure SDRAM.
193 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
194 *
195 * For BR2, need:
196 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
197 * port-size = 32-bits = BR2[19:20] = 11
198 * no parity checking = BR2[21:22] = 00
199 * SDRAM for MSEL = BR2[24:26] = 011
200 * Valid = BR[31] = 1
201 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500202 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500203 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
204 *
205 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
206 * FIXME: the top 17 bits of BR2.
207 */
208
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500209#define CFG_BR2_PRELIM 0xf0001861
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500210
211/*
212 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
213 *
214 * For OR2, need:
215 * 64MB mask for AM, OR2[0:7] = 1111 1100
216 * XAM, OR2[17:18] = 11
217 * 9 columns OR2[19-21] = 010
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500218 * 13 rows OR2[23-25] = 100
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500219 * EAD set for extra time OR[31] = 1
220 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500221 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500222 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
223 */
224
225#define CFG_OR2_PRELIM 0xfc006901
226
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500227#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
228#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
229#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
230#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500231
232/*
233 * LSDMR masks
234 */
235#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
236#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
237#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
238#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
239#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
240#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
241#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
242#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
243#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
244#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
245
246#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
247#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
248#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
249#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
250#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
251#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
252#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
253#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
254
255/*
256 * Common settings for all Local Bus SDRAM commands.
257 * At run time, either BSMA1516 (for CPU 1.1)
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500258 * or BSMA1617 (for CPU 1.0) (old)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500259 * is OR'ed in too.
260 */
261#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
262 | CFG_LBC_LSDMR_PRETOACT7 \
263 | CFG_LBC_LSDMR_ACTTORW7 \
264 | CFG_LBC_LSDMR_BL8 \
265 | CFG_LBC_LSDMR_WRC4 \
266 | CFG_LBC_LSDMR_CL3 \
267 | CFG_LBC_LSDMR_RFEN \
268 )
269
270/*
271 * The CADMUS registers are connected to CS3 on CDS.
272 * The new memory map places CADMUS at 0xf8000000.
273 *
274 * For BR3, need:
275 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
276 * port-size = 8-bits = BR[19:20] = 01
277 * no parity checking = BR[21:22] = 00
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500278 * GPMC for MSEL = BR[24:26] = 000
279 * Valid = BR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500280 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500281 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500282 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
283 *
284 * For OR3, need:
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500285 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500286 * disable buffer ctrl OR[19] = 0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500287 * CSNT OR[20] = 1
288 * ACS OR[21:22] = 11
289 * XACS OR[23] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500290 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500291 * SETA OR[28] = 0
292 * TRLX OR[29] = 1
293 * EHTR OR[30] = 1
294 * EAD extra time OR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500295 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500296 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500297 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
298 */
299
300#define CADMUS_BASE_ADDR 0xf8000000
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500301#define CFG_BR3_PRELIM 0xf8000801
302#define CFG_OR3_PRELIM 0xfff00ff7
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500303
304#define CONFIG_L1_INIT_RAM
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500305#define CFG_INIT_RAM_LOCK 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500306#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500307#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500308
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500309#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
310
311#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500312#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
313#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
314
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500315#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
316#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500317
318/* Serial Port */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500319#define CONFIG_CONS_INDEX 2
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500320#undef CONFIG_SERIAL_SOFTWARE_FIFO
321#define CFG_NS16550
322#define CFG_NS16550_SERIAL
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500323#define CFG_NS16550_REG_SIZE 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500324#define CFG_NS16550_CLK get_bus_freq(0)
325
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500326#define CFG_BAUDRATE_TABLE \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
328
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500329#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
330#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500331
332/* Use the HUSH parser */
333#define CFG_HUSH_PARSER
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500334#ifdef CFG_HUSH_PARSER
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500335#define CFG_PROMPT_HUSH_PS2 "> "
336#endif
337
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500338/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600339#define CONFIG_OF_LIBFDT 1
340#define CONFIG_OF_BOARD_SETUP 1
341#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500342
Jon Loeliger20476722006-10-20 15:50:15 -0500343/*
344 * I2C
345 */
346#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
347#define CONFIG_HARD_I2C /* I2C with hardware support*/
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500348#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500349#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
350#define CFG_I2C_EEPROM_ADDR 0x57
351#define CFG_I2C_SLAVE 0x7F
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500352#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500353#define CFG_I2C_OFFSET 0x3000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500354
355/*
356 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300357 * Memory space is mapped 1-1, but I/O space must start from 0.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500358 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500359#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
360
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500361#define CFG_PCI1_MEM_BASE 0x80000000
362#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500363#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500364#define CFG_PCI1_IO_BASE 0x00000000
365#define CFG_PCI1_IO_PHYS 0xe2000000
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500366#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500367
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500368#ifdef CONFIG_PCI2
369#define CFG_PCI2_MEM_BASE 0xa0000000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500370#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500371#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
Andy Flemingffa621a2007-02-24 01:08:13 -0600372#define CFG_PCI2_IO_BASE 0x00000000
Zang Roy-r6191141fb7e02006-12-14 14:14:55 +0800373#define CFG_PCI2_IO_PHYS 0xe2800000
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500374#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
375#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500376
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500377#ifdef CONFIG_PCIE1
378#define CFG_PCIE1_MEM_BASE 0xa0000000
379#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
380#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
381#define CFG_PCIE1_IO_BASE 0x00000000
382#define CFG_PCIE1_IO_PHYS 0xe3000000
383#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
384#endif
Zang Roy-r6191141fb7e02006-12-14 14:14:55 +0800385
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500386#ifdef CONFIG_RIO
Zang Roy-r6191141fb7e02006-12-14 14:14:55 +0800387/*
388 * RapidIO MMU
389 */
390#define CFG_RIO_MEM_BASE 0xC0000000
391#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500392#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500393
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700394#ifdef CONFIG_LEGACY
395#define BRIDGE_ID 17
396#define VIA_ID 2
397#else
398#define BRIDGE_ID 28
399#define VIA_ID 4
400#endif
401
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500402#if defined(CONFIG_PCI)
403
404#define CONFIG_NET_MULTI
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500405#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500406
407#undef CONFIG_EEPRO100
408#undef CONFIG_TULIP
409
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500410#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500411
412/* PCI view of System Memory */
413#define CFG_PCI_MEMORY_BUS 0x00000000
414#define CFG_PCI_MEMORY_PHYS 0x00000000
415#define CFG_PCI_MEMORY_SIZE 0x80000000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500416
417#endif /* CONFIG_PCI */
418
419
420#if defined(CONFIG_TSEC_ENET)
421
422#ifndef CONFIG_NET_MULTI
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500423#define CONFIG_NET_MULTI 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500424#endif
425
426#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500427#define CONFIG_TSEC1 1
428#define CONFIG_TSEC1_NAME "eTSEC0"
429#define CONFIG_TSEC2 1
430#define CONFIG_TSEC2_NAME "eTSEC1"
431#define CONFIG_TSEC3 1
432#define CONFIG_TSEC3_NAME "eTSEC2"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500433#define CONFIG_TSEC4
Kim Phillips255a35772007-05-16 16:52:19 -0500434#define CONFIG_TSEC4_NAME "eTSEC3"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500435#undef CONFIG_MPC85XX_FEC
436
437#define TSEC1_PHY_ADDR 0
438#define TSEC2_PHY_ADDR 1
439#define TSEC3_PHY_ADDR 2
440#define TSEC4_PHY_ADDR 3
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500441
442#define TSEC1_PHYIDX 0
443#define TSEC2_PHYIDX 0
444#define TSEC3_PHYIDX 0
445#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500446#define TSEC1_FLAGS TSEC_GIGABIT
447#define TSEC2_FLAGS TSEC_GIGABIT
448#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
449#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500450
451/* Options are: eTSEC[0-3] */
452#define CONFIG_ETHPRIME "eTSEC0"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500453#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500454#endif /* CONFIG_TSEC_ENET */
455
456/*
457 * Environment
458 */
459#define CFG_ENV_IS_IN_FLASH 1
460#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
461#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
462#define CFG_ENV_SIZE 0x2000
463
464#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
465#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
466
Jon Loeliger2835e512007-06-13 13:22:08 -0500467/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500468 * BOOTP options
469 */
470#define CONFIG_BOOTP_BOOTFILESIZE
471#define CONFIG_BOOTP_BOOTPATH
472#define CONFIG_BOOTP_GATEWAY
473#define CONFIG_BOOTP_HOSTNAME
474
475
476/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500477 * Command line configuration.
478 */
479#include <config_cmd_default.h>
480
481#define CONFIG_CMD_PING
482#define CONFIG_CMD_I2C
483#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600484#define CONFIG_CMD_ELF
Jon Loeliger2835e512007-06-13 13:22:08 -0500485
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500486#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500487 #define CONFIG_CMD_PCI
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500488#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500489
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500490
491#undef CONFIG_WATCHDOG /* watchdog disabled */
492
493/*
494 * Miscellaneous configurable options
495 */
496#define CFG_LONGHELP /* undef to save memory */
Kumar Gala22abb2d2007-11-29 10:34:28 -0600497#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500498#define CFG_LOAD_ADDR 0x2000000 /* default load address */
499#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500500#if defined(CONFIG_CMD_KGDB)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500501#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
502#else
503#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
504#endif
505#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
506#define CFG_MAXARGS 16 /* max number of command args */
507#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
508#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
509
510/*
511 * For booting Linux, the board info and command line data
512 * have to be in the first 8 MB of memory, since this is
513 * the maximum mapped by the Linux kernel during initialization.
514 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500515#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500516
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500517/*
518 * Internal Definitions
519 *
520 * Boot Flags
521 */
522#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
523#define BOOTFLAG_WARM 0x02 /* Software reboot */
524
Jon Loeliger2835e512007-06-13 13:22:08 -0500525#if defined(CONFIG_CMD_KGDB)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500526#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
527#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
528#endif
529
530/*
531 * Environment Configuration
532 */
533
534/* The mac addresses for all ethernet interface */
535#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500536#define CONFIG_HAS_ETH0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500537#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500538#define CONFIG_HAS_ETH1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500539#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500540#define CONFIG_HAS_ETH2
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500541#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Andy Fleming09f3e092006-09-13 10:34:18 -0500542#define CONFIG_HAS_ETH3
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500543#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500544#endif
545
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500546#define CONFIG_IPADDR 192.168.1.253
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500547
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500548#define CONFIG_HOSTNAME unknown
549#define CONFIG_ROOTPATH /nfsroot
550#define CONFIG_BOOTFILE 8548cds/uImage.uboot
551#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500552
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500553#define CONFIG_SERVERIP 192.168.1.1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500554#define CONFIG_GATEWAYIP 192.168.1.1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500555#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500556
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500557#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500558
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500559#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
560#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500561
562#define CONFIG_BAUDRATE 115200
563
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500564#define CONFIG_EXTRA_ENV_SETTINGS \
565 "netdev=eth0\0" \
566 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
567 "tftpflash=tftpboot $loadaddr $uboot; " \
568 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
569 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
570 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
571 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
572 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
573 "consoledev=ttyS1\0" \
574 "ramdiskaddr=2000000\0" \
Andy Fleming6c543592007-08-13 14:38:06 -0500575 "ramdiskfile=ramdisk.uboot\0" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500576 "fdtaddr=c00000\0" \
Kumar Gala22abb2d2007-11-29 10:34:28 -0600577 "fdtfile=mpc8548cds.dtb\0"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500578
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500579#define CONFIG_NFSBOOTCOMMAND \
580 "setenv bootargs root=/dev/nfs rw " \
581 "nfsroot=$serverip:$rootpath " \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500582 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500583 "console=$consoledev,$baudrate $othbootargs;" \
584 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500585 "tftp $fdtaddr $fdtfile;" \
586 "bootm $loadaddr - $fdtaddr"
Andy Fleming8272dc22006-09-13 10:33:35 -0500587
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500588
589#define CONFIG_RAMBOOTCOMMAND \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500590 "setenv bootargs root=/dev/ram rw " \
591 "console=$consoledev,$baudrate $othbootargs;" \
592 "tftp $ramdiskaddr $ramdiskfile;" \
593 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500594 "tftp $fdtaddr $fdtfile;" \
595 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500596
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500597#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500598
599#endif /* __CONFIG_H */