blob: 0a7a90497501dcf33e8c7d46cda7d7af5378b8fa [file] [log] [blame]
Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
2 * Copyright 2007 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * sbc8548 board configuration file
27 *
28 * Please refer to doc/README.sbc85xx for more info.
29 *
30 */
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/* High Level Configuration Options */
35#define CONFIG_BOOKE 1 /* BOOKE */
36#define CONFIG_E500 1 /* BOOKE e500 family */
37#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
38#define CONFIG_MPC8548 1 /* MPC8548 specific */
39#define CONFIG_SBC8548 1 /* SBC8548 board specific */
40
41#undef CONFIG_PCI /* enable any pci type devices */
42#undef CONFIG_PCI1 /* PCI controller 1 */
43#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
44#undef CONFIG_RIO
45#undef CONFIG_PCI2
46#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
47
48#define CONFIG_TSEC_ENET /* tsec ethernet support */
49#define CONFIG_ENV_OVERWRITE
50#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
51#define CONFIG_DDR_DLL /* possible DLL fix needed */
52#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
53
54#undef CONFIG_DDR_ECC /* only for ECC DDR module */
55#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
56#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
57#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
58
Kumar Galae2b159d2008-01-16 09:05:27 -060059#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060060
61#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
62
63#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */
64
65/*
66 * These can be toggled for performance analysis, otherwise use default.
67 */
68#define CONFIG_L2_CACHE /* toggle L2 cache */
69#define CONFIG_BTB /* toggle branch predition */
70#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
71#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
72
73/*
74 * Only possible on E500 Version 2 or newer cores.
75 */
76#define CONFIG_ENABLE_36BIT_PHYS 1
77
78#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
79
80#undef CFG_DRAM_TEST /* memory test, takes time */
81#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
82#define CFG_MEMTEST_END 0x00400000
83
84/*
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
87 */
88#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
90#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
91
92#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
93#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
94#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
95
96/*
97 * DDR Setup
98 */
99#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
100#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
101
102#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
103
104/*
105 * Make sure required options are set
106 */
107#ifndef CONFIG_SPD_EEPROM
108 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
109#endif
110
111#undef CONFIG_CLOCKS_IN_MHZ
112
113/*
114 * FLASH on the Local Bus
115 * Two banks, one 8MB the other 64MB, using the CFI driver.
116 * Boot from BR0/OR0 bank at 0xff80_0000
117 * Alternate BR6/OR6 bank at 0xfb80_0000
118 *
119 * BR0:
120 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
121 * Port Size = 8 bits = BRx[19:20] = 01
122 * Use GPCM = BRx[24:26] = 000
123 * Valid = BRx[31] = 1
124 *
125 * 0 4 8 12 16 20 24 28
126 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0
127 *
128 * BR6:
129 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
130 * Port Size = 32 bits = BRx[19:20] = 11
131 * Use GPCM = BRx[24:26] = 000
132 * Valid = BRx[31] = 1
133 *
134 * 0 4 8 12 16 20 24 28
135 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6
136 *
137 * OR0:
138 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
139 * XAM = OR0[17:18] = 11
140 * CSNT = OR0[20] = 1
141 * ACS = half cycle delay = OR0[21:22] = 11
142 * SCY = 6 = OR0[24:27] = 0110
143 * TRLX = use relaxed timing = OR0[29] = 1
144 * EAD = use external address latch delay = OR0[31] = 1
145 *
146 * 0 4 8 12 16 20 24 28
147 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0
148 *
149 * OR6:
150 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
151 * XAM = OR6[17:18] = 11
152 * CSNT = OR6[20] = 1
153 * ACS = half cycle delay = OR6[21:22] = 11
154 * SCY = 6 = OR6[24:27] = 0110
155 * TRLX = use relaxed timing = OR6[29] = 1
156 * EAD = use external address latch delay = OR6[31] = 1
157 *
158 * 0 4 8 12 16 20 24 28
159 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6
160 */
161
162#define CFG_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
163#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
164
165#define CFG_BR0_PRELIM 0xff800801
166#define CFG_BR6_PRELIM 0xfb801801
167
168#define CFG_OR0_PRELIM 0xff806e65
169#define CFG_OR6_PRELIM 0xfc006e65
170
171#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
172#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
173#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
174#undef CFG_FLASH_CHECKSUM
175#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
176#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
177
178#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
179
180#define CFG_FLASH_CFI_DRIVER
181#define CFG_FLASH_CFI
182#define CFG_FLASH_EMPTY_INFO
183
184/* CS5 = Local bus peripherals controlled by the EPLD */
185
186#define CFG_BR5_PRELIM 0xf8000801
187#define CFG_OR5_PRELIM 0xff006e65
188#define CFG_EPLD_BASE 0xf8000000
189#define CFG_LED_DISP_BASE 0xf8000000
190#define CFG_USER_SWITCHES_BASE 0xf8100000
191#define CFG_BD_REV 0xf8300000
192#define CFG_EEPROM_BASE 0xf8b00000
193
194/*
195 * SDRAM on the Local Bus
196 */
197#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
198#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
199
200/*
201 * Base Register 3 and Option Register 3 configure SDRAM.
202 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
203 *
204 * For BR3, need:
205 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
206 * port-size = 32-bits = BR2[19:20] = 11
207 * no parity checking = BR2[21:22] = 00
208 * SDRAM for MSEL = BR2[24:26] = 011
209 * Valid = BR[31] = 1
210 *
211 * 0 4 8 12 16 20 24 28
212 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
213 *
214 */
215
216#define CFG_BR3_PRELIM 0xf0001861
217
218/*
219 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
220 *
221 * For OR3, need:
222 * 64MB mask for AM, OR3[0:7] = 1111 1100
223 * XAM, OR3[17:18] = 11
224 * 10 columns OR3[19-21] = 011
225 * 12 rows OR3[23-25] = 011
226 * EAD set for extra time OR[31] = 0
227 *
228 * 0 4 8 12 16 20 24 28
229 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
230 */
231
232#define CFG_OR3_PRELIM 0xfc006cc0
233
234#define CFG_LBC_LCRR 0x00000002 /* LB clock ratio reg */
235#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
236#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
237#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
238
239/*
240 * LSDMR masks
241 */
242#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
243#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
244#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
245#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
246#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
247#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
248#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
249#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
250#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
251#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
252
253#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
254#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
255#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
256#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
257#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
258#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
259#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
260#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
261
262/*
263 * Common settings for all Local Bus SDRAM commands.
264 * At run time, either BSMA1516 (for CPU 1.1)
265 * or BSMA1617 (for CPU 1.0) (old)
266 * is OR'ed in too.
267 */
268#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
269 | CFG_LBC_LSDMR_PRETOACT7 \
270 | CFG_LBC_LSDMR_ACTTORW7 \
271 | CFG_LBC_LSDMR_BL8 \
272 | CFG_LBC_LSDMR_WRC4 \
273 | CFG_LBC_LSDMR_CL3 \
274 | CFG_LBC_LSDMR_RFEN \
275 )
276
277#define CONFIG_L1_INIT_RAM
278#define CFG_INIT_RAM_LOCK 1
279#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
280#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
281
282#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
283
284#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
285#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
286#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
287
288#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
289#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
290
291/* Serial Port */
292#define CONFIG_CONS_INDEX 1
293#undef CONFIG_SERIAL_SOFTWARE_FIFO
294#define CFG_NS16550
295#define CFG_NS16550_SERIAL
296#define CFG_NS16550_REG_SIZE 1
297#define CFG_NS16550_CLK 400000000 /* get_bus_freq(0) */
298
299#define CFG_BAUDRATE_TABLE \
300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
301
302#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
303#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
304
305/* Use the HUSH parser */
306#define CFG_HUSH_PARSER
307#ifdef CFG_HUSH_PARSER
308#define CFG_PROMPT_HUSH_PS2 "> "
309#endif
310
311/* pass open firmware flat tree */
312#define CONFIG_OF_LIBFDT 1
313#define CONFIG_OF_BOARD_SETUP 1
314#define CONFIG_OF_STDOUT_VIA_ALIAS 1
315
316/*
317 * I2C
318 */
319#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
320#define CONFIG_HARD_I2C /* I2C with hardware support*/
321#undef CONFIG_SOFT_I2C /* I2C bit-banged */
322#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
323#define CFG_I2C_EEPROM_ADDR 0x50
324#define CFG_I2C_SLAVE 0x7F
325#define CFG_I2C_OFFSET 0x3000
326
327/*
328 * General PCI
329 * Memory space is mapped 1-1, but I/O space must start from 0.
330 */
331#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
332
333#define CFG_PCI1_MEM_BASE 0x80000000
334#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
335#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
336#define CFG_PCI1_IO_BASE 0x00000000
337#define CFG_PCI1_IO_PHYS 0xe2000000
338#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
339
340#ifdef CONFIG_PCI2
341#define CFG_PCI2_MEM_BASE 0xa0000000
342#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
343#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
344#define CFG_PCI2_IO_BASE 0x00000000
345#define CFG_PCI2_IO_PHYS 0xe2800000
346#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
347#endif
348
349#ifdef CONFIG_PCIE1
350#define CFG_PCIE1_MEM_BASE 0xa0000000
351#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
352#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
353#define CFG_PCIE1_IO_BASE 0x00000000
354#define CFG_PCIE1_IO_PHYS 0xe3000000
355#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
356#endif
357
358#ifdef CONFIG_RIO
359/*
360 * RapidIO MMU
361 */
362#define CFG_RIO_MEM_BASE 0xC0000000
363#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
364#endif
365
366#ifdef CONFIG_LEGACY
367#define BRIDGE_ID 17
368#define VIA_ID 2
369#else
370#define BRIDGE_ID 28
371#define VIA_ID 4
372#endif
373
374#if defined(CONFIG_PCI)
375
376#define CONFIG_NET_MULTI
377#define CONFIG_PCI_PNP /* do pci plug-and-play */
378
379#undef CONFIG_EEPRO100
380#undef CONFIG_TULIP
381
382#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
383
384/* PCI view of System Memory */
385#define CFG_PCI_MEMORY_BUS 0x00000000
386#define CFG_PCI_MEMORY_PHYS 0x00000000
387#define CFG_PCI_MEMORY_SIZE 0x80000000
388
389#endif /* CONFIG_PCI */
390
391
392#if defined(CONFIG_TSEC_ENET)
393
394#ifndef CONFIG_NET_MULTI
395#define CONFIG_NET_MULTI 1
396#endif
397
398#define CONFIG_MII 1 /* MII PHY management */
399#define CONFIG_TSEC1 1
400#define CONFIG_TSEC1_NAME "eTSEC0"
401#define CONFIG_TSEC2 1
402#define CONFIG_TSEC2_NAME "eTSEC1"
403#define CONFIG_TSEC3 1
404#define CONFIG_TSEC3_NAME "eTSEC2"
405#define CONFIG_TSEC4
406#define CONFIG_TSEC4_NAME "eTSEC3"
407#undef CONFIG_MPC85XX_FEC
408
409#define TSEC1_PHY_ADDR 0
410#define TSEC2_PHY_ADDR 1
411#define TSEC3_PHY_ADDR 2
412#define TSEC4_PHY_ADDR 3
413
414#define TSEC1_PHYIDX 0
415#define TSEC2_PHYIDX 0
416#define TSEC3_PHYIDX 0
417#define TSEC4_PHYIDX 0
418#define TSEC1_FLAGS TSEC_GIGABIT
419#define TSEC2_FLAGS TSEC_GIGABIT
420#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
421#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422
423/* Options are: eTSEC[0-3] */
424#define CONFIG_ETHPRIME "eTSEC0"
425#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
426#endif /* CONFIG_TSEC_ENET */
427
428/*
429 * Environment
430 */
431#define CFG_ENV_IS_IN_FLASH 1
432#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
433#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
434#define CFG_ENV_SIZE 0x2000
435
436#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
437#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
438
439/*
440 * BOOTP options
441 */
442#define CONFIG_BOOTP_BOOTFILESIZE
443#define CONFIG_BOOTP_BOOTPATH
444#define CONFIG_BOOTP_GATEWAY
445#define CONFIG_BOOTP_HOSTNAME
446
447
448/*
449 * Command line configuration.
450 */
451#include <config_cmd_default.h>
452
453#define CONFIG_CMD_PING
454#define CONFIG_CMD_I2C
455#define CONFIG_CMD_MII
456#define CONFIG_CMD_ELF
457
458#if defined(CONFIG_PCI)
459 #define CONFIG_CMD_PCI
460#endif
461
462
463#undef CONFIG_WATCHDOG /* watchdog disabled */
464
465/*
466 * Miscellaneous configurable options
467 */
468#define CFG_LONGHELP /* undef to save memory */
469#define CFG_LOAD_ADDR 0x2000000 /* default load address */
470#define CFG_PROMPT "=> " /* Monitor Command Prompt */
471#if defined(CONFIG_CMD_KGDB)
472#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
473#else
474#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
475#endif
476#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
477#define CFG_MAXARGS 16 /* max number of command args */
478#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
479#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
480
481/*
482 * For booting Linux, the board info and command line data
483 * have to be in the first 8 MB of memory, since this is
484 * the maximum mapped by the Linux kernel during initialization.
485 */
486#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
487
Joe Hamman9e3ed392007-12-13 06:45:14 -0600488/*
489 * Internal Definitions
490 *
491 * Boot Flags
492 */
493#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
494#define BOOTFLAG_WARM 0x02 /* Software reboot */
495
496#if defined(CONFIG_CMD_KGDB)
497#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
498#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
499#endif
500
501/*
502 * Environment Configuration
503 */
504
505/* The mac addresses for all ethernet interface */
506#if defined(CONFIG_TSEC_ENET)
507#define CONFIG_HAS_ETH0
508#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
509#define CONFIG_HAS_ETH1
510#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
511#define CONFIG_HAS_ETH2
512#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
513#define CONFIG_HAS_ETH3
514#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
515#endif
516
517#define CONFIG_IPADDR 192.168.0.55
518
519#define CONFIG_HOSTNAME sbc8548
520#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
521#define CONFIG_BOOTFILE /uImage
522#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
523
524#define CONFIG_SERVERIP 192.168.0.2
525#define CONFIG_GATEWAYIP 192.168.0.1
526#define CONFIG_NETMASK 255.255.255.0
527
528#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
529
530#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
531#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
532
533#define CONFIG_BAUDRATE 115200
534
535#define CONFIG_EXTRA_ENV_SETTINGS \
536 "netdev=eth0\0" \
537 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
538 "tftpflash=tftpboot $loadaddr $uboot; " \
539 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
540 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
541 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
542 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
543 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
544 "consoledev=ttyS0\0" \
545 "ramdiskaddr=2000000\0" \
546 "ramdiskfile=uRamdisk\0" \
547 "fdtaddr=c00000\0" \
548 "fdtfile=sbc8548.dtb\0"
549
550#define CONFIG_NFSBOOTCOMMAND \
551 "setenv bootargs root=/dev/nfs rw " \
552 "nfsroot=$serverip:$rootpath " \
553 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
554 "console=$consoledev,$baudrate $othbootargs;" \
555 "tftp $loadaddr $bootfile;" \
556 "tftp $fdtaddr $fdtfile;" \
557 "bootm $loadaddr - $fdtaddr"
558
559
560#define CONFIG_RAMBOOTCOMMAND \
561 "setenv bootargs root=/dev/ram rw " \
562 "console=$consoledev,$baudrate $othbootargs;" \
563 "tftp $ramdiskaddr $ramdiskfile;" \
564 "tftp $loadaddr $bootfile;" \
565 "tftp $fdtaddr $fdtfile;" \
566 "bootm $loadaddr $ramdiskaddr $fdtaddr"
567
568#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
569
570#endif /* __CONFIG_H */